FSA7830 ONSEMI | Alldatasheet
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© 2016 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA7830 • Rev. 1.0 FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP FSA7830 8-Channel Voltage MUX with Integrated Voltage Divider and OVP
Features
Voltage Supply, 2.7 to 5.5 V Input Voltage Range, 0 to 5.4 V Up to 8-Channel Inputs Integrated 1/3, 2/3 Voltage Divider Integrated Over-Voltage Protection and Assertion Total Introduced Offset < ±10 mV ICC < 100 µA, Ishutdown < 1 µA 1.8 V I2C Interface, Addr<1:0> to Set Address for Multi Chip Solution 16-Ball, 0.4 mm Pitch, 1.56 mm ×1.56 mm, WLCSP Package
Applications
Cell Phones Tablets
Description
The FSA7830 is an 8-Channel, low-power Voltage MUX. It integrates 8 analog switches for input voltage selection, and voltage dividers to provide 1/3, 2/3 fraction of selected voltage. With another 3 analog switches, FSA7830 provides feasibility to choose 1/3, 2/3 or 1 times of selected voltage. FSA7830 also contains output buffer to enhance driving capability. It features over-voltage protection to ensure output less than 2 V, interrupt will be alerted at the same time. FSA7830 supports 1.8 V I2C interface to communicate with processor, and 2 address pins to provide multi-chip solution.
Ordering Information
Part Number Top Mark Operating Temperature Range Package FSA7830BUCX GT -40 to +85°C 16-Ball, 0.4 mm Pitch Wafer Level Chip Scale Package (WLCSP) Package (1.56 x 1.56 mm)
Figure 1. Application Diagram
Figure 2. 16 Ball WLCSP Package(Top View)
- A fast-mode I2C-bus device can be used in a standard-mode I2 C-bus system, but the requirement tSU;DAT ≥
specification) before the I2C_SCL line is released. Figure 1. Definition of Timing for Full-Speed Mode Devices on the I2C Bus Table 1. I2CTM Slave Address
© 2016 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA7830 • Rev.1.0 6 FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dama ge the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage -0.5 6 V V1~8 Input Voltage -0.5 6 V IIK DC Input Diode Current -50 mA TSTG Storage Temperature -65 +150 °C MSL Moisture Sensitivity Level (JEDEC J-STD-020A) 1 Level ESD Human Body Model, JEDEC: JESD22- A114 All Pins 2 kV I/O to GND 2 Power to GND 2 Charged Device Model, JEDEC: JESD22-C101 500 V Recommended Operating Conditions The Recommended Operating Conditions table defines the condi tions for actual device operation. Recommended operating conditions are specified to ensure optimal perfo rmance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VCC Supply Voltage 2.7 5.5 V V1~8 Input Voltage 0 5.4 V VADDR Address Pin Voltage 0 VCC V VSCL,SDA,\\INT I2C Bus Voltage Swing 0 1.8 V TA Operating Temperature -40 +85 °C
© 2016 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA7830 • Rev.1.0 7 FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP All typical value are for V CC=3.7 V at T A=25°C, with 100 K Ω and 100 nF+10 pF loading at VO, unless otherwise specified. Symbol Parameter Condition VCC (V) TA=- 40°C to +85°C Unit Min. Typ. Max. VIK Clamp Diode Voltage IIN=-18 mA -0.7 V VIHI2C High-Level Input Voltage 2.7 to 5.5 1.26 V VILI2C Low-Level Input Voltage 2.7 to 5.5 0.54 V VHYSI2C Hysteresis of Schmitt Trigger Inputs 2.7 to 5.5 0.09 V II2C Input Current of SDA, SCL and \\INT Input Voltage 0.26 V to 2 V 2.7 to 5.5 -10 10 µA ICCTI2C VCC current when SDA or SCL is HIGH Input Voltage 1.8 V 5.5 1 µA VIHADDR High-Level Input Voltage 2.7 to 5.5 1.26 V VILADDR Low-Level Input Voltage 2.7 to 5.5 0.54 V VHYSADDR Hysteresis of Schmitt Trigger Inputs 2.7 to 5.5 0.09 V VOLSDA Low-Level Output Voltage of SDA Pin 4 mA Sink Current (Open-Drain) 2.7 to 5.5 0.36 V VOLINTN Low-Level Output Voltage of \\INT 4 mA Sink Current (Open-Drain) 2.7 to 5.5 0.36 V RON1 Switch1 On Resistance 2.7 to 5.5 100 200 Ω RON2 Switch2 On Resistance(2) 2.7 to 5.5 100 200 Ω RVD Voltage Divider On Resistance(2) 2.7 to 5.5 1 MΩ ICC Quiescent Supply Current All blocks in Enable Mode 2.7 to 5.5 100 µA ICCZ Disable Mode Leakage Current 2.7 to 5.5 -1 3.9 µA ILEAK,ON Leakage Current of each channel from V1~8 to GND in Enable Mode 2 µA ILEAK,OFF Leakage Current of each channel from V1~8 to GND in Disable Mode 1 µA VOFFSET Offset Voltage introduced by FSA7830, referring to VO 2.7 to 5.5 -10 10 mV VOVP Over-Voltage Protection Threshold (Low to High) VOVP,HYS Over-Voltage Assertion Hysteresis 2.7 to 5.5 50 mV VCLAMPING Clamping Voltage on VO when OVP happens VO,DYNAMIC VO Dynamic Range
100 KΩ between VO to
0.9 V, output buffer has the
ability to drive the target value with maximum 1% mismatch 2.7 to 5.5 0.5 2.1 V Note: 2. Guaranteed by Design.
© 2016 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA7830 • Rev.1.0 8 FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP All typical value are for V CC=4.2 V at T A=25°C, with 100 KΩ and 100 nF+10 pF loading at VO, unless otherwise specified. Symbol Parameter Condition VCC (V) TA=- 40°C to +85°C Unit Min. Typ. Max. CI Input Capacitance on V1~8(3) F=1 MHz 2.7 to 5.5 50 pF tSETTLING VO Settling Time after each Switching(3) RS=50 Ω, CO=100 nF+10 pF, RO=100 KΩ, VO reaches 99% of target value 2.7 to 5.5 200 µs tLOADRESPONSE VO Buffer Load Response, Settling Time of Load Change(3) Loading on VO switches from 100 nF to CO=100 nF+10 pF, RO=100 K. VO reaches 99% of target value 2.7 to 5.5 150 ns PSRR Power Supply Rejection Ratio of VO from VCC Power supply noise, F=217 Hz, Vpp=50 mV, CO=100 nF+10 pF, RO=100 KΩ 2.7 to 5.5 70 dB Xtalk Cross Talk between V1~8 F=500 KHz, Vpp=50 mV, CO=100 nF+10 pF, RO=100 KΩ 2.7 to 5.5 80 dB Note: 3. Guaranteed by characterization and not tested in production.
© 2016 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA7830 • Rev.1.0 9 FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP
Application Information
The \\INT pin is an active low, open drain output which indicates to the host processor that an interrupt has occurred in the FSA7830 which needs attention. The \\INT pin is HIGH-Z by default after power-up or device reset. The \\INT pin stays HIGH-Z in preparation of future interrupts. When an interruptible event occurs, \\INT is driven LOW and is HIGH-Z again when the processor clears the interrupt by reading the interrupt registers. Subsequent to the initial power up or reset; if the processor writes a “1” to one of interrupt mask bits when the system is already powered up, the \\INT pin stays HIGH-Z and ignores corresponding interrupt until the interrupt mask bit is cleared. If an event happens that would ordinarily cause an interrupt when the interrupt mask bit is set, the \\INT pin goes LOW when the interrupt mask is cleared. Figure 5. Typical Application Sequence multi-internal register values. Table 2. Register Map
Table 3. Register Map
- Do not use registers that are blank.
- Values read from undefined register bits are not defined and inval id. Do not write to undefined registers.
Table 4. Register Device ID Table 5. Control
7 Chip Enable 1
6 Output Enable 1
Table 6. SWCTL
7 SW1 Enable 1
3 SW2 Enable 1
0 SW3 Control 1
Table 7. INT
7 OVP 1 0: OVP event has not occurred
Table 8. INT_MASK
7 OVP 1 0: Do not mask OVP interrupt
Table 9. OVP The table below pertains to the WLCSP package information on the following page.
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