FSA644

FSA644 ONSEMI | Alldatasheet

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www.fairchildsemi.com © 2011 Fairchild Semiconductor Corporation FSA644 • Rev. 2 FSA644 — 2:1 MIPI D-PHY (1.5Gbps) 4-Data-Lane Switch FSA644 — 2:1 MIPI D-PHY (1.5Gbps) 4-Data Lane Switch

Features

Switch Type SPDT (10x) Signal Types MIPI, D-PHY VCC 1.65 to 4.5 V Input Signals 0 to VCC RON 6 Ω Typical HS MIPI 8 Ω Typical LP MIPI ∆RON 0.6 Ω Typical HS & LP MIPI RON_FLAT 0.3 Ω Typical ICCZ 0.5 µA Maximum ICC 32 µA Maximum OIRR -40 dB Typical XTALK -25 dB Typical Bandwidth 1100 MHz Minimum Channel-to-Channel Skew 6 ps Typical CON 5.2 pF Operating Temperature -40 to +85°C Package 36-Ball WLCSP FSA644UCX Top Mark M7 FSA644BUCX Top Mark KM

Description

The FSA644 is a four-data-lane, MIPI, D-PHY switch. This single-pole, double-throw (SPDT) switch is optimized for switching between two high-speed or low-power MIPI sources. The FSA644 is designed for the MIPI specification and allows connection to a CSI or DSI module.

Applications

 Cellular Phones, Smart Phones  Displays Related Resources  FSA644 Demonstration Board Typical Application Figure 1. Mobile Phone Example

Figure 2. Analog Symbol

Figure 3. Top Through View Table 1. Ball-to-Pin Mappings

www.fairchildsemi.com © 2011 Fairchild Semiconductor Corporation FSA644 • Rev. 2 4 FSA644 — 2:1 MIPI D-PHY (1.5Gbps) 4-Data-Lane Switch Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage -0.50 +5.25 V VCNTRL DC Input Voltage (/OE)(1) -0.5 VCC V VSW DC Switch I/O Voltage(1) -0.50 5.25 V IIK DC Input Diode Current -50 mA IOUT DC Output Current 50 mA TSTG Storage Temperature -65 +150 °C ESD Human Body Model, JEDEC: JESD22-A114 All Pins 3.5 kV I/O to GND 3.5 Power to GND 8.0 Charged Device Model, JEDEC: JESD22-C101 1.5 IEC 61000-4-2 System Contact 8.0 Air Gap 15.0 Note: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VCC Supply Voltage 1.65 4.50 V VCNTRL Control Input Voltage (S, /OE)(2) 0 VCC V VSW Switch I/O Voltage (CLKn, CLKAn, CLKBn, Dn, DAn, DBn) HS Mode 0.1 0.3 V LP Mode 0 1.2 TA Operating Temperature -40 +85 °C Note: 2. The control input must be held HIGH or LOW; it must not float.

www.fairchildsemi.com © 2011 Fairchild Semiconductor Corporation FSA644 • Rev. 2 5 FSA644 — 2:1 MIPI D-PHY (1.5Gbps) 4-Data-Lane Switch All typical values are at TA=25°C unless otherwise specified. Symbol Parameter Conditions VCC (V) TA=- 40ºC to +85ºC Unit Min. Typ. Max. VIK Clamp Diode Voltage IIN=-18 mA 2.8 -1.2 V VIH Input Voltage High 1.65 to 4.50 1.0 V VIL Input Voltage Low 1.65 to 4.50 0.4 V IIN Control Input Leakage (SEL,/OE) VSW=0 to VCC 1.65 to 4.50 -100 100 nA INO(OFF), INC(OFF) Off Leakage Current of Port CLKAn, DAn, CLKBn, DBn CLKn, Dn=0.3 V; VCC-0.3 V; CLKAn, DAn, or CLKBn; DBn= VCC-0.3 V, 0.3 V, or Floating; /OE=0 V 1.65 to 4.50 -100 100 nA IA(ON) On Leakage Current of Common Ports (CLKn, Dn) CLKn, Dn = 0.3 V; VCC-0.3 V; CLKAn, DAn, or CLKBn; DBn=VCC-0.3 V, 0.3 V, or Floating; /OE=0 V 1.65 to 4.50 -100 100 nA IOFF Power-Off Leakage Current CLKn, Dn, or CLKAn; DAn or CLKBn, DBn; VIN=0 V to

4.5 V; VCC=0 V

0 ≤ CLKn, Dn, CLKAn, CLKBn, DAn, DBn ≤ 3.6 V, /OE=High 4.5 -100 100 nA RON_MIPI_HS Switch On Resistance for HS MIPI Applications(3) ION=-10 mA, /OE=0 V, SEL=VCC or 0V, CLKA, B, DBn or DAn=0.1, 0.2, 0.3 1.8 7 12 Ω 2.5 6 9 3.6 6 9 4.5 6 9 RON_MIPI_LP Switch On Resistance for LP MIPI Applications(3) ION=-10 mA, /OE=0 V, SEL=VCC or 0V, CLKA, B, DBn or DAn=0, 0.6, 1.2 V 1.8 6.7 12.0 Ω 2.5 6.4 9.0 3.6 6.2 9.0 4.5 6.0 9.0 ∆RON_MIPI_HS On Resistance Matching Between HS MIPI Channels(4) ION=-10 mA, /OE=0 V, SEL=VCC or 0 V, CLKA, B, DBn or DAn=0.1, 0.2, 0.3 1.8 0.8 Ω 2.5 0.6 3.6 0.5 4.5 0.5 ∆RON_MIPI_LP On Resistance Matching Between LP MIPI Channels(4) ION=-10 mA, /OE=0 V, SEL=VCC or 0 V, CLKA,B, DBn or DAn= 0.0, 0.6, 1.2 V 1.8 0.8 Ω 2.5 0.6 3.6 0.5 4.5 0.5 RON_FLAT_MIPI_HS On Resistance Flatness for HS MIPI Signals(4) ION=-10 mA, /OE=0 V, SEL=VCC or 0 V, CLKA, B, DBn or DAn=0.1, 0.2, 0.3 1.8 1.5 Ω 2.5 0.5 3.6 0.3 4.5 0.2 RON_FLAT_MIPI_LP On Resistance Flatness for LP MIPI Signals(4) ION=-10 mA, /OE=0 V, SEL=VCC or 0 V, CLKA, B, DBn or DAn=0.0, 0.6, 1.2 V 1.8 3.5 Ω 2.5 2 3.6 1 4.5 0.5 Continued on the following page…

www.fairchildsemi.com © 2011 Fairchild Semiconductor Corporation FSA644 • Rev. 2 6 FSA644 — 2:1 MIPI D-PHY (1.5Gbps) 4-Data-Lane Switch All typical values are at TA=25°C unless otherwise specified. Symbol Parameter Conditions VCC (V) TA=- 40ºC to +85ºC Unit Min. Typ. Max. ICCZ Quiescent Hi-Z Supply Current VIN=0 or VCC, IOUT=0 4.5 0.5 µA ICC Quiescent Supply Current VIN=0 or VCC, IOUT=0 2.5 to 4.5 32 µA 1.8 22 ICCT Increase in ICC Current Per Control Voltage and VCC VSEL,/OE=1.65 V 4.5 4 µA 2.5 0.1 Notes: 3. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltage on the two (A or B ports). 4. Guaranteed by characterization. All typical values are for VCC=3.3V at TA=25°C unless otherwise specified. Symbol Parameter Conditions VCC (V) TA=- 40ºC to +85ºC Unit Min. Typ. Max. tINIT Initalization Time VCC to Output (5) RL=50 Ω, CL=5 pF, VSW=1.2 V 2.5 to 4.5 100 µs 1.8 150 tEN Enable Turn-On Time, /OE to Output RL=50 Ω, CL=5 pF, VSW=1.2 V 2.5 to 4.5 120 200 ns 1.8 250 500 tDIS Disable Turn-Off Time, /OE to Output RL=50 Ω, CL=5 pF, VSW=1.2 V 2.5 to 4.5 25 50 ns 1.8 50 90 tON Turn-On Time, SEL to Output RL=50 Ω, CL=5 pF, VSW=1.2 V 2.5 to 4.5 50 100 ns 1.8 75 125 tOFF Turn-Off Time SEL to Output RL=50 Ω, CL=5 pF, VSW=1.2 V 2.5 to 4.5 50 200 ns 1.8 200 325 tBBM Break-Before-Make Time RL=50 Ω, CL=5 pF, VSW=1.2 V 10 50 ns OIRR Off Isolation for MIPI(5) RL=50 Ω, f=750 MHz, /OE=VCC VSW=-1 dBm (200 mVPP) 1.65 to 4.5 -18 dB XTALK Crosstalk for MIPI(5) RL=50 Ω, f=750 MHz, VSW=-1 dBm (200 mVPP) 1.65 to 4.5 -25 dB BW -3db Bandwidth(5) RL=50 Ω, CL=0 pF 3.0 1100 1600 MHz SDD21 Differential Data Rate Inter-operability Data Rate 3.0 1.5 Gbps Note: 5. Guaranteed by characterization.

www.fairchildsemi.com © 2011 Fairchild Semiconductor Corporation FSA644 • Rev. 2 7 FSA644 — 2:1 MIPI D-PHY (1.5Gbps) 4-Data-Lane Switch High-Speed-Related AC Electrical Characteristics Symbol Parameter Conditions VCC (V) TA=- 40ºC to +85ºC Unit Min. Typ. Max. tSK(O) Channel-to-Channel Single- Ended Skew(6) TDR-Based Method (VSW=0.2 VPP, CL=CON) 3.3 6 20 ps tSK(P) Skew of Opposite Transitions of the Same Output(6) TDR-Based Method (VSW=0.2 VPP, CL=CON) 3.3 6 20 ps Note: 6. Guaranteed by characterization. Capacitance Symbol Parameter Conditions TA=- 40ºC to +85ºC Unit Min. Typ. Max. CIN Control Pin Input Capacitance VCC=0 V, f=1 MHz 2.1 pF CON Out On Capacitance VCC=3.3 V, /OE=0 V, f=1 MHz 5.2 COFF Out Off Capacitance VCC and /OE=3.3 V, f=1 MHz 2.0

Ordering Information

FSA644UCX M7 36-Ball WLCSP, Non-JEDEC 2.36 mm x 2.36 mm, 0.4 mm Pitch 2.36 mm 2.36 mm 0.18 mm 0.18 mm FSA644BUCX KM 36-Ball WLCSP, Non-JEDEC 2.415 mm x 2.415 mm,

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