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Technical content

Features

 Low On Capacitance: 7.7 pF Typical  Low On Resistance: 6 Ω Typical  Low Pow er Consumption: 1 μA Max imum - 15 μA Max imum ICCT over an Expanded Voltage Range (V IN=1.8 V, VCC=5.5 V)  Wide -3 db Bandw idth: 1.0 GHz  Packaged in Ultra Small 6-Lead TMLP  Broad VCC Operating Range: 1.6 V to 5.5 V  Over-Voltage Tolerance (OVT) on all Data Por ts up to 6 V w ithout External Components

Applications

 Cell Phone, PDA, Digital Camera, and Notebook  LCD Monitor, TV, and Set-Top Box

Description

The FSA3051 is a 6 Ω, bi -directional, low -pow er, tw o- port, high- speed, Single Pole / Double Throw (SPDT) analog sw itch. It features an extremely low on capacitance (CON) of 7.7 pF and w ide bandw idth of 1.0 GHz. The FSA3051 contains special circuitry on the sw itch I/O pins for applications w here the V CC supply is pow ered-off (V CC=0 V), w hich allow s the device to w ithstand an over -voltage condition. This device is designed to minimize current consumption even w hen the control voltage applied to the select (S) pin is low er than the supply voltage (V CC). This feature is especially valuable to ultra- portable applications, such as cell phones, allow ing for direct interface w ith the general - purpose I/Os of the baseband processor. Other applications include sw itching in portable cell phones, PDAs, digital cameras, printers, and notebook computers.

Ordering Information

FSA3051TMX NT -40 to +85°C 6-Lead, Dual, Ultra-ultrathin Molded Leadless Package (TMLP), 1.0 x 1.0 mm. Top left unit orientation in carrier tape. FSA3051TMX-F147 NT -40 to +85°C 6-Lead, Dual, Ultra-ultrathin Molded Leadless Package (TMLP), 1.0 x 1.0 mm. Bottom left unit orientation in carrier tape. MicroPak ™ is a trademark of ON Semiconductor Corporation.

Figure 1. Logic Symbol Figure 2. Analog Symbol Figure 3. 6-Lead TMLP (Top-Through View)

1 B1 Data Port

2 GND Ground

3 B0 Data Port

4 A Data Port

5 VCC Supply Voltage

6 S Sw itch Select

www.onsemi.com FSA3051 — High Performance SPDT Analog Switch with Over Voltage Tolerance Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage -0.5 6.0 V VCNTRL DC Input Voltage(3) -0.5 VCC V VSW DC Sw itch I/O Voltage(3) -0.50 6.00 V IIK DC Input Diode Current -50 mA IOUT DC Output Current 50 mA TSTG Storage Temperature -65 +150 °C MSL Moisture Sensitivity Level (JEDEC J -STD-020A) 1 Level ESD Human Body Model, ANSI/ESDA/JEDEC JS-001-2012 All Pins 2 kV I/O to GND 2 Pow er to GND 2 Charged Device Model, JEDEC: JESD22-C10 1 1 Note : 3. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VCC Supply Voltage 1.6 5.5 V VCNTRL Control Input Voltage (S) (4) 0 VCC V VSW Sw itch I/O Voltage -0.5 5.5 V TA Operating Temperature -40 +85 °C Note: 4. The control input must be held HIGH or LOW and it must not float.

www.onsemi.com FSA3051 — High Performance SPDT Analog Switch with Over Voltage Tolerance All typical value are for V CC=3.3 V at TA=25°C unless otherw ise specified. Symbol Parameter Condition VCC (V) TA=- 40°C to +85°C Unit Min. Typ. Max. tON Turn-On Time S to Output RL=50 Ω, CL=5 pF, VSW=0.8 V, Figure 6, Figure 7 3.0 to 3.6 34 ns 1.8 110 tOFF Turn-O ff T im e S to Output RL=50 Ω, CL=5 pF, VSW=0.8 V, Figure 6, Figure 7 3.0 to 3.6 23 ns 1.8 50 tPD Propagation Delay CL=5 pF, RL=50 Ω, Figure 6, Figure 8 3.3 0.2 ns 1.8 0.3 tBBM Break-Before-Make RL=50 Ω, CL=5 pF, VSW1=VSW2=0.8 V, Figure 9 3.0 to 3.6 15 50 ns 1.8 100 OIRR Off Isolation RL=50 Ω, f=240 MHz , Figure 11 1.8 -20 dB 3.0 to 3.6 -23 Xtalk Crosstalk RL=50 Ω, f=240 MHz , Figure 12 1.8 -18 dB 3.0 to 3.6 -23 dB BW -3 db Bandw idth RL=50 Ω, CL=0 pF, VSW=0.4 V 1.8 810 MHz RL=50 Ω, CL=0 pF, Figure 10 3.0 to 3.6

1 GHz

RL=50 Ω, CL=5 pF, Figure 10 750 MHz Note: 8. Guaranteed by characterization. Not production tested. Capacitance (9) Symbol Parameter Condition VCC (V) TA=- 40°C to +85°C Unit Min. Typ. Max. CIN Control Pin Input Capacitance 0 1.5 pF CON A Port On Capacitance f=1 MHz , 3.0 7.7 f=240 MHz , Figure 14 3.3 7.7 f=1 MHz , 1.8 10.0 f=240 MHz , Figure 14 1.8 5.0 COFF Bn Port Off Capacitance f=1 MHz 3.0 3.3 f=240 MHz , Figure 13 3.3 3.3 f=1 MHz 1.8 5.0 f=240 MHz , Figure 13 1.8 4.0 Note : 9. Not production tested.

Figure 15. TMLP Carrier Tape Packing

www.onsemi.com FSA3051 — High Performance SPDT Analog Switch with Over Voltage Tolerance Physical Dimensions 1.00±0.050 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009 NOTES: A. NO JEDEC STANDARD APPLIES 0.05 C AB 0.370±0.030 0.05 C C 0.35 0.20±0.0251 2 3 0.30±0.025 DETAIL A 0.60 45° CHAMFER TOP VIEW BOTTOM VIEW

0.05 C B A

0.05 C PIN 1 0.05 C 2X 1.00±0.050 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC E. DRAWING FILENAME AND REVISION: MKT-TMLP06AREV2 DETAIL A PIN 1 LEAD SCALE: 2X DESIGN. MIN 250uM 6 5 4 (0.05) 4X SIDE VIEW (0.30) 0.35 6X 0.20 0.66 0.70 1.06 0.89 RECOMMENDED LAND PATTERN 6X 0.40 (0.05) 6X 1 2 3 6 5 4 6-Lead, Dual, Ultra-ultrathin Molded Leadless Package (TMLP), 1.0 x 1.0 mm

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