FSA2257 ONSEMI | Alldatasheet
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© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA2257 • Rev. 1.0.6 FSA2257— Low RON, Low-Voltage Dual SPDT Bi-Directional Analog Switch FSA2257 Low RON, Low-Voltage Dual SPDT Bi-Directional Analog Switch
Features
Maximum 1.15 On Resistance (RON) at 4.5 V VCC 0.3 Maximum RON Flatness at +5 V VCC Space-Saving MicroPak™ Broad VCC Operating Range: 1.65 V to 5.50 V Fast Turn-On and Turn-Off Time Break-Before-Make Enable Circuitry Over-Voltage Tolerant TTL-Compatible Control Input
Applications
Cell Phone PDA Mobile Devices
Description
The FSA2257 is a high-performance bi-directional dual Single-Pole/Double-Throw (SPDT) analog switch. This switch can be configured as either a multiplexer or a de- multiplexer by select pins. The device features ultra-low RON of 1.3 maximum at 4.5 V VCC and operates over the wide V CC range of 1.65 V to 5.50 V. The device is fabricated with submicron CMOS technology to achieve fast switching speeds and is designed for break-before- make operation. The select input is TTL-level compatible.
Ordering Information
Mark Package Description Packing Method FSA2257L10X MAC10A EP 10-Lead MicroPak™, 1.6 x 2.1 mm 5000 Units Tape and Reel FSA2257MTCX MCT14 FSA2257 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4 mm Wide 2500 Units Tape and Reel FSA2257MUX MUA10A FSA 2257 10-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0 mm 4000 Units Tape and Reel Figure 1. Block Diagram
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA2257 • Rev. 1.0.6 3 FSA2257— Low RON, Low-Voltage Dual SPDT Bi-Directional Analog Switch Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage -0.5 6.0 V VSW DC Switch Voltage(1) -0.5 VCC + 0.5 V VIN DC Input Voltage(1) -0.5 6.0 V IIK Input Diode Current -50 mA Switch Current 200 Peak Switch Current (Pulsed at 1 ms duration, <10% duty cycle) 400 TSTG Storage Temperature Range -65 +150 °C TJ Maximum Junction Temperature +150 °C TL Lead Temperature (Soldering, 10 seconds) +260 °C ESD Electrostatic Discharge Capability Human Body Model, JESD22-A114 8000 V Charged Device Model, JESD22-C101 2000 Note: 1. Input and output negative ratings may be exceeded if input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VCC Supply Voltage 1.65 5.50 V VCNTRL Control Input Voltage(2) 0 VCC V VSW Switch Input Voltage 0 VCC V TA Operating Temperature -40 +85 °C Note: 2. Unused control input must be held HIGH or LOW and it must not float.
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA2257 • Rev. 1.0.6 4 FSA2257— Low RON, Low-Voltage Dual SPDT Bi-Directional Analog Switch Typical values are at 25°C unless otherwise specified. Symbol Parameter Conditions VCC(V) TA=+25°C TA=-40°C to +85°C Unit VIH Input Voltage High 1.8 to 2.7 1.0 V 2.7 to 3.6 2.0 4.5 to 5.5 2.4 VIL Input Voltage Low 1.8 to 2.7 0.4 V 2.7 to 3.6 0.6 4.5 to 5.5 0.8 IIN Control Input Leakage VIN=0 V to VCC µA INO(OFF), INC(OFF) Off Leakage Current of Port B0 and B1 A=1 V, 4.5 V, B0 or B1=1 V, 4.5 V 5.5 -2 2 -20 20 nA IA(ON) On Leakage Current of Port A A=1 V, 4.5V, B0 or B1=1 V,4.5 V or Floating 5.5 -4 2 -40 40 nA RON Switch On Resistance MicroPak(3) IOUT=100 mA, B0 or B1=1.5 V 1.8 4.6 2.7 2.6 4.0 4.3 IOUT=100 mA, Switch On Resistance MSOP/TSSOP(3) IOUT=100 mA, B0 or B1=1.5 V 2.7 2.8 4.5 IOUT=100 mA, B0 or B1=3.5 V 4.5 1.5 2.3 RON On Resistance Matching Between Channels MicroPak (4) IOUT=100 mA, B0 or B1=3.5 V 4.5 0.06 0.12 0.15 On Resistance Matching Between Channels MSOP / TSSOP(4) 4.5 0.7 0.3 RFLAT(ON) On Resistance Flatness(5) IOUT=100 mA, B0 or BI =0 V, 0.75 V,1.5 V 1.8 3.0 2.7 1.4 IOUT=100 mA, B0 or BI =0 V, 1 V, 2 V 4.5 0.2 0.3 0.4 ICC Quiescent Supply Current VIN=0 V or VCC, IOUT=0 V 3.6 0.1 0.5 1.0 µA 5.5 0.1 0.5 1.0 Notes: 3. On resistance is determined by the voltage drop between A and B pins at the indicated current through the switch. 4. ΔRON = RONmax – RONmin measured at identical VCC, temperature, and voltage. 5. Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions.
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSA2257 • Rev. 1.0.6 5 FSA2257— Low RON, Low-Voltage Dual SPDT Bi-Directional Analog Switch Typical values are at 25°C unless otherwise specified. Symbol Parameter Conditions VCC(V) TA=+25°C TA=-40°C to +85°C Unit Figure tON Turn-On Time B0 or B1=1.5 V, RL=50 , CL=35 pF 1.8 to 2.7 ns Figure 6 2.7 to 3.6 50 60 B0 or B1=3.0 V, RL=50 , CL=35 pF 4.5 to 5.5 35 40 tOFF Turn-Off Time B0 or B1=1.5 V, RL=50 , CL=35 pF 1.8 to 2.7 ns Figure 6 2.7 to 3.6 20 30 B0 or B1=3.0 V, RL=50 , CL=35 pF 4.5 to 5.5 15 20 tBBM Break- Before-Make Time B0 or B1=1.5 V, RL=50 , CL=35 pF 2.7 to 3.6 1 ns Figure 7 B0 or B1=3.0 V, RL=50 , CL=35 pF 4.5 to 5.5 20 1 Q Charge Injection CL=1.0 nF, VGEN=0 V, RGEN=0 2.7 to 3.6 20 pC Figure 9 4.5 to 5.5 10 OIRR Off Isolation f=1 MHz, RL=50 2.7 to 3.6 -70 dB Figure 8 4.5 to 5.5 -70 Xtalk Crosstalk f=1 MHz, RL=50 2.7 to 3.6 -75 dB Figure 8 4.5 to 5.5 -75 BW -3 db Bandwidth RL=50 2.7 to 3.6 200 MHz Figure 11 4.5 to 5.5 200 THD Total Harmon Distortion RL=600 VIN=0.5 VPP f=20 Hz to 20 kHz 2.7 to 3.6 0.002 % Figure 12 4.5 to 5.5 0.002 Capacitance Symbol Parameter Conditions VCC (V) TA=+25°C Unit Figure Min. Typ. Max. CIN Control Pin Input Capacitance f=1 MHz 0 3.5 pF Figure 10 COFF B Port Off Capacitance f=1 MHz 4.5 12.0 pF Figure 10 CON A Port On Capacitance f=1 MHz 4.5 40.0 pF Figure 10
5.00±0.10 ALL LEAD TIPS NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 2009. E. LANDPATTERN STANDARD: SOP65P640X110-14M. F. DRAWING FILE NAME: MKT-MTC14rev7. 0.43TYP
0.2 C B A
A B .0±0.10 3.2 6.4 PIN#1 IDENT
1.2 MAX
0.1 C ALL LEAD TIPS C 0.65 0.30 0.19
0.13 A B C
0.10±0.05 0.90+0.15 -0.10 0.20 0.09 SEE DETAIL A 12.00 723 %27720 GAGE PLANE 0.25 SEATING PLANE
0.09 MIN
0.6±0.1 1.00 DETAIL A 0 RECOMMENDED LAND PATTERN 6.10 0.65 1.65 0.45
0.50 4.40
1.40 MIN
0.30 3.00±0.10 3.00±0.10 4.90 0.381 2.45 PIN #1 ID QUADRANT A B
1.10 MAX
0.50 0.27 0.17 0.85 ±0.10 0.15 0.00 .08 M A B C 0.10 C C 0.23 0.08 A 12° TOP & BOTTOM R0.13 TYP 0.95 0.22 4°-8 0.80 0.40 DETAIL A SCALE 20 : 1 GAUGE PLANE SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED A. THIS PACKAGE CONFORMS TO JEDEC MO-187 VARIATION BA. B. ALL DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR EXTRUSIONS. D. DIMENSIONS AND TOLERANCES AS PER ASME Y14.5-1994. E. LAND PATTERN AS PER IPC7351#SOP50P490X110-10AN F. FILE NAME: MKT-MUA10AREV3 LAND PATTERN RECOMMENDATION TOP VIEW SIDE VIEW END VIEW ALL LEAD TIPS 1 5 10 6 DRAWING NUMBER 10LD, MSOP, JEDEC MKT-MUA10A APPROVED: BOBOY MALDO BY HUANG HOWARD ALLEN CHECKED: DRAWN: PROJECTION INCH [MM] APPROVALS FORMERLY: SCALE DATE 24SEP09 SIZE N/A SHEET : 1 OF 1 REV THIS DRAWING IS THE PROPERTY OF FAIRCHILD SEMICONDUCTOR CORPORATION. NO USE THEREOF SHALL BE MADE OTHER THAN AS A REFERENCE FOR PROPOSALS AS SUBMITTED TO FAIRCHILD SEMICONDUCTOR CORPORATION FOR JOBS TO BE EXECUTED IN CONFORMITY WITH SUCH PROPOSALS UNLESS THE CONSENT OF SAID FAIRCHILD SEMICONDUCTOR COR- COPIED OR DUPLICATED OR ITS CONTENTS DISCLOSED. THE INFORMATION CONTAINED PORATION HAS PREVIOUSLY BEEN OBTAINED. NO PART OF THIS DRAWING SHALL BE ON THIS DRAWING IS CONFIDENTIAL AND PROPRIETARY. NBR DESCRIPTION REVISIONS DATE BY/APP'D KH LEE 1:1 N/A APPROVED: REDREW FORMER NSC DWG H.ALLEN07JUN2006B MO-187, 3.0MM WIDE * REMOVE SITE ADDRESS AND CHANGE REVISION TO NUMERICAL & CHANGED LAND PATTERN TO IPC. * CHANGE LEAD WIDTH FROM 0.27MAX TO 0.33MAX. * REMOVE DATE OF JEDEC REVISION KHLEE/FSSZ20AUG2009 * REVERT LEAD WIDTH TO 0.27MAX. KHLEE/FSSZ24SEP20093
NOTES: A. PACKAGE CONFORMS TO JEDEC REGISTRATION MO-255, VARIATION UABD. B. DIMENSIONS ARE IN MILLIMETERS. C. PRESENCE OF CENTER PAD IS PACKAGE SUPPLIER DEPENDENT. IF PRESENT IT IS NOT INTENDED TO BE SOLDERED AND HAS A BLACK OXIDE FINISH. D. DRAWING FILENAME: MKT-MAC10ArevG. E. DIMENSIONS WITHIN ( ) ARE UNCONTROLLED.
0.10 C A B
0.05 C 1 4 9 6 10 5 0.50 0.56 1.62 1.60±0.10 2.10±0.10 (0.25) 10X0.50 (0.11) 1.12 1.62 0.20±0.05 0.15±0.05 0.30±0.05 0.30±0.05 0.20±0.05 0.60±0.05 C (0.36) 2X (0.31) 0.56 0.50±0.05 0.20±0.05 9X 0.30±0.05 9X (0.20) (0.09) 10X (0.10±0.10) A BPIN#1 IDENT IS 2X LONGER THAN OTHER LINES TOP VIEW 0.025±0.025 C SIDE VIEW BOTTOM VIEW DETAIL A ALL FEATURES DETAIL A SCALE 2:1 RECOMMENDED LAND PATTERN (0.35) 10X KEEPOUT ZONE, NO TRACES OR VIAS ALLOWED
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