FS8308

FS8308 PTC | Alldatasheet

Document overview

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Technical content

Features

‹ Up to 40 MHz external crystal oscillator reference frequency under normal condition ‹ Low current consumption (IDD,total typically 1.2 mA at fFIN = 500 MHz and VDD1 = 1.0 ‹ With Schmitt trigger added for noise-immune programming input ‹ 18-bit programmable input frequency divider (including a ÷ 64/65 prescaler) with divide ratio range from 4032 to 262143 ‹ 13-bit programmable reference frequency divider (including a ÷ 8 prescaler) with divide ratio range from 40 to 65528 ‹ Optional lock detector output (LD, fR/2, fV/2) ‹ Charge pump output for passive low-pass filter ‹ Wide tuning range of charge pump output for external VCO (VSS+0.5 to VDD2-0.5) ‹ Switchover terminal for constant of loop filter or general open drain output ‹ Reference oscillator buffer output ‹ Programmable stand-by control ‹ TSSOP 16L package (0.65mm pitch)

Applications

‹ Pager ‹ Family radio service (FRS) ‹ Wireless communication system

Advance Information FS8308 Page 2 April 2003 Package and Pin Assignment: 16L, TSSOP Note: Tolerance + 0.1mm unless otherwise specified Symbols Dimensions in mm Dimensions in inch XIN XOUT VDD2 NC DO VSS FIN VDD1 BO TEST SW LE DATA CLK LD NC HiMARK FS8308

Advance Information FS8308 Page 3 April 2003 Pin Descriptions Block Diagram Number Name I/O Description 1X I N I Reference crystal oscillator or external clock input with internally biased amplifier (any external input to XIN must be ac-coupled)

2 XOUT O Reference crystal oscill ator or external clock output

3 VDD2 POWER Nominal 3.0 V supply voltage

4 NC NC No connection

5 DO O Single-ended charge pump outp ut for passive low-pass filter

6 VSS GND Ground

7F I N I VCO frequency input with internally biased input amplifier (any external input to FIN must be ac-coupled) 8 VDD1 POWER Nominal 1.0 V supply voltage

9 NC NC No connection

10 LD O Lock detector output (high when PLL is locked)

11 CLK I Shift register clock input

12 DATA I Serial data input

13 LE I Latch enable input

14 SW O Switchover terminal for constant of loop filter or a general open drain output

15 TEST I Test mode control input wi th internal pull-down resistor

16 BO O Terminal of reference crys tal oscillator buffer outputPFD

÷ 8 ÷ 64/65 LD DO XOUT LOCK DETECTOR WINDOW GENERATOR S-LATCH SW BO SW

Advance Information FS8308 Page 4 April 2003 Absolute Maximum Ratings VSS = 0 V Recommended Operating Conditions VSS = 0 V Parameter Symbol Rating Unit Supply voltage VDD1 VSS – 0.3 to VSS + 2.0 V VDD2 VSS – 0.3 to VSS + 6.0 V Input voltage range VFIN VSS – 0.3 to VDD + 0.3 V Operating temperature range TPS –30 to 60 oC Storage temperature range TSTG –40 to 125 oC Soldering temperature range TSLD 255 oC Soldering time range tSLD 10 s Parameter Symbol Value Unit min. typ. max. Supply voltage range VDD1 0.95 1.0 2.0 V VDD2 2.4 3.0 3.6 V Operating temperature TA –30 25 60 oC

Advance Information FS8308 Page 5 April 2003

Electrical Characteristics

(VDD1 = 0.95 to 2.0 V, VDD2 = 2.4 to 3.6 V, VSS = 0 V, TA = 0 to 60°C unless otherwise noted) Parameter Symbol Condition Value Unit min. typ. max. Current consumption IDD,total VDD1 = 1.0 V fFIN = 500 MHz fXIN =24 MHz 1.2 1.5 mA Standby current consumption IDD,standby PS=”H” 10 µA FIN operating frequency range fFIN PFIN = -15dBm VDD1 = 1.0 V , PS=”L” 20 500 MHz XIN operating frequency range fXIN VDD1 = 1.0 V 7 40 MHz FIN input voltage swing PFIN -15 dBm XIN input voltage swing VXIN 0.3 Vpk-pk CLK, DATA, LE logic LOW input voltage VIL 0.3 V CLK, DATA, LE logic HIGH input voltage VIH VDD- 0.3 V XIN logic LOW input current IIL,XIN VIL = 0 V 10 µA XIN logic HIGH input current IIH,XIN VIH = VDD1 10 µA FIN logic LOW input current IIL,FIN VIL = 0 V 60 µA FIN logic HIGH input current IIH,FIN VIH = VDD1 60 µA Charge Pump Drive Current IDO VDD2 = 3.0V , VDO = 1.5V 1.0 mA Charge Pump Sink Current IDO VDD2 = 3.0V , VDO = 1.5V 1.0 mA LD, FV , FR logic LOW output current IOL VOL = 0.4 V 0.1 mA LD, FV , FR logic HIGH output current IOH VOH = VDD2 – 0.4 V 0.1 mA SW logic LOW output current ISW,OFF SW = ’L’ VSW = VDD2 = 3.0V 10 µA SW logic HIGH output current ISW,ON SW = ’H’ VSW = VDD2 = 3.0V 2.8 mA DATA to CLK setup time tSU1 2 µs CLK to LE setup time tSU2 2 µs Hold time tHOLD 2 µs

Advance Information FS8308 Page 6 April 2003 Functional Description Programmable Input Frequency Divider The VCO input to the FIN pin is divided by the programmable divider and then internally output to the phase/frequency detector (PFD) as fV. The programmable input frequency divider consists of a ÷ 64/65 (P/P+1) dual-modulus prescaler in prior to a 18-bit (N) counter, which is further comprised of a 6-bit swallow (A) counter, and a 12-bit main (B) counter. The total divide ratio, N, is related to values for P, A, and B through the relation with The minimum available programma ble divisor for continuous counting is given by and the valid total divide ratio range for the input divider is Take N=10000 for example, since P=64 and hence that B=156 and A=16. Therefore, the binary codes of B and A should be 0000 1001 1100 and 010000, respectively. An alterna- tive approach is to translate the decimal N into binary code directly. And then just take the last 6-bit as A and the remaining 12-bit as B. By far the binary code of N=10000 is 00 0010 0111 0001 0000. One can get the same result as the former method. Programmable Reference Frequency Divider The crystal oscillator output is divided by the programmable divider and then internally output to the PFD as fR. The programmable reference frequency divider consists of a fixed ÷ 8 (S) prescaler and a 13-bit reference (R) counter. The total divide ratio, T, is related to values for S and R through the relation The usable divisior range of the reference counter is and therefore, the valid total divide ratio range for the reference divider is (in steps of 8.) NP 1+() AP BA –()×+× PBA ,+×== BA .≥ M 4032 to 262143.= TS R × 8 R.×== R 5 to 8191= T 40 to 65528=

Advance Information FS8308 Page 7 April 2003 Serial Input Data Format The divsors of the input and reference dividers are input using a 20-bit serial interface consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The format of the serial data is shown in Fig. 1. The data on the DATA line is written to the shift reg- ister on the rising edge of the CLK signal and is input with MSB first. The last two bits are recognized as the latch select control bits. Data on the DATA line should be changed on the falling edge of CLK, and LE should be held low while data is being written to the shift register. Data is transferred from the shift register to either one of the frequency divider latches or the optional control latch when LE is set high. When the latch select control bits are set high-low or low-low, data is loaded to the 18-bit N-counter latch, and when the latch select control bits are set high-high, the 2 MSBs are ignored, the next 13 data bits are loaded to the 13-bit R-counter latch and the remaining 3 LSBs are used to control testing modes and should be set as follows for normal operation: R14 = high, R15 = low, R16 = low. To disable LD output (i.e. set LD low), R14 should be set low. When the latch select control bits are set low-high, the 2 MSBs are recognized as PS and SW, which are used as stand-by control and open drain output control, respectively. The detail of two control bits setting is summarized in Table 1. In normal work condition, PS is set to low. When PS is programmed to high, it will enter stand-by mode. Serial input data timing waveforms are shown in Fig. 2. Fig. 1 – Serial input data format Table 1: Control Bit Setting 1st CB 2nd CB Fetching Target of Serial Data Input X0 N - c o u n t e r 0 1 PS and SW

11 R - c o u n t e r

Advance Information FS8308 Page 8 April 2003 Fig. 2 – Serial input data timing waveforms tSU1 tSU2 tHOLD DATA CLK LE DATA CLK LE 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 71 18 19 20 1ST CB 2ND CB MSB LSB

Advance Information FS8308 Page 9 April 2003 Phase/Frequency Detector (PFD) The PFD compares an internal input frequency divider output signal, fV, with an internal reference frequency divider output signal, fR, and generates an error signal, DO, which is proportional to the phase error between fV and fR. The DO output is intended for use with a passive filter as shown in Fig. 2. Lock Detector (LD) When phase comparator detects phase difference, LD terminal outputs “L”. When phase comparator locks, LD terminal outputs “H”. On standby, outputs “H”. The criteria for lock condition is that the phase difference between fV and fR is less than 2/xin and continues for more than three consecutive times. The input/output waveforms for the PFD and LD are shown in Fig. 3. Fig. 2 – Passive low-pass filter circuit Fig. 3 – PFD input/output waveforms DO to VCO high-Z high-Z high-Z fR fV DO LD < 2/xin < 2/xin < 2/xin 2/xin

Advance Information FS8308 Page 10 April 2003 Stand-by Mode The stand-by mode for the PLL is entered by programming the PS bit to high. In the stand- by mode, the XIN and FIN amplifiers, N-counter, and R-counter are stopped, as well as the internal current bias for charge pump block, the N- and R-counters are also reset, and the DO and DB outputs are set to the high impedance state. As long as voltage is supplied to VDD2, data loaded to the latches is kept. To exit from stand-by mode to normal operation, the PS bit must be programmed to low. Reference Crystal Oscillator Buffer Output (BO) This IC provides a reference crystal oscillator buffer output intended to be used as a crys- tal local oscillator to a 2nd mixer. The terminal is represented as BO. For cases to enhance the buffer output swing, increasing VDD1 will be an efficient way. Filter Switch Control (SW) Control of SW terminal by “SW” bit. This terminal is for switching time-constant of loop filter. Output type of this terminal is open drain output. When constant of loop filter doesn’t change by this switch, general open drain output is available. Note that there is an internal 200Ω resistor connected between and drain terminal and output pin.

Advance Information FS8308 Page 11 April 2003 Application Circuit BO TEST SW LE DATA CLK LD NC XIN XOUT VDD2 NC DO VSS FIN VDD1 DC/DC converter CPU LCD driver LCD Driver ROMRAM Decoder LPF LNA 1st mixer 1st IF amplifier 2nd mixer 2nd IF amplifier Discriminator Wave shaper Frequency multiplier (×4,5) 2nd LO 1st LO HiMARK FS8308

Advance Information FS8308 Page 12 April 2003 Typical Characteristics FIN Input Sensitivity vs. Input Frequency 0 100 200 300 400 500 600 -40 -36 -32 -28 -24 -20 -16 -12 Vdd2=3.0V fXIN=24MHz, R=5 Input Sensitivity (dBm) fFIN (MHz) Vdd1=1.0V Vdd1=1.1V Vdd1=1.2V

Advance Information FS8308 Page 13 April 2003 Current Consumption of Idd1 vs. Operating Frequency Current Consumption of Idd2 vs. Supply Voltage Vdd2 0 100 200 300 400 500 600 0.0 0.4 0.8 1.2 1.6 2.0 Vdd1=1.0V Vdd1=1.1V Vdd1=1.2V Vdd2=3.0V, Pfin=-15dBm fXIN=24MHz, R=5 Idd1 (mA) fFIN (MHz) 0.16 0.20 0.24 0.28 0.32 0.36 0.40 Idd2 (mA) Vdd2 (V)

Advance Information FS8308 Page 14 April 2003 Charge Pump Output Characteristics Charge Pump Output Current vs. Power Supply Voltage -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 Vdd2=3.0V FR < FV FR > FV IDO (mA) VDO (V) Drive Current Sink Current 0.4 0.5 0.6 0.7 0.8 0.9 1.0

1.1 Charge Pump Output Current

1VDO = IDO (mA) Vdd2 (V) Drive Current Sink Current

Advance Information FS8308 Page 15 April 2003 Single Voltage Operation This IC requires two separate power supplies to operate. If only one voltage source is available, ex. use battery to serve as power source, the user can apply the configuration as shown in the following which is referred to as single voltage operation. Since there is only one voltage source provided in the so-called single voltage configura- tion, which is directly connected to Vdd2, one needs to choose a reasonable R value to set Vdd1 to operate within the safe region, whose requirement is Vdd1 > 0.95V . Keep in mind that the lower Vdd1 is, the less current this IC will consume, but the poorer crystal buffer output it drives. In order to balance the trade-off between the current consumption and crystal buffer driving capability, Vdd1 is suggested to be about 1.1V . Vdd1 vs. Vdd2 for vari- ous R at fin=470MHz is plotted in the following figure. Note that although smaller resistor R makes this IC consume more current, the reward is with wider power supply input range. Typical value of R is recommended to be around 1.6KΩ.. Single Voltage Characteristic: Vdd1 vs. Vdd2 for Various R VDD2 VDD1 HiMARK FS8308 R POWER SUPPLY 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 Safe Operation Region fin=470MHz, Pfin=-10dBm xin=24MHz, N=4032, R=5 Vdd1 (V) Vdd2 (V) R=1.2K R=1.6K R=1.8K R=2.0K