FS8170

FS8170 PTC | Alldatasheet

Document overview

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Technical content

Features

‹ Maximum input frequency: 2.5 GHz ‹ Supply voltage range from 2.4 V to 3.6 V ‹ Low current consumption in locked state: 3.5 mA typ. (V CC = VP = 2.7 V , TA = +25 °C) 4.0 mA typ. (VCC = VP = 3.0 V , TA= +25 °C) 10 µA max. in asynchronous power-down mode ‹ Digitally-filtered lock detect output ‹ 18-bit programmable input frequency divider using ÷ 32/33/64/65 multi-modulus prescaler with divide ratio range from 992 to 65631 for ÷ 32/33 mode and from 4032 to 131135 for ÷ 64/65 mode ‹ 14-bit programmable reference frequency divider with divide ratio range from 3 to 16383 ‹ Programmable charge pump current: 1.5 mA or 6 mA ‹ Pin compatible with Fujitsu MB15E07, MB15E07L, MB15E07SL ‹ 16 pin, plastic TSSOP (0.65 mm pitch) Package and Pin Assignment 16 pin, plastic TSSOP (dimensions in mm) XIN XOUT VP VCC DO VSS XFIN FIN φR φP FOLD ZC EN LE DA TA CLK HiMARK FS8170

Number Name I/O Description

1 XIN I Reference crystal oscillator or external clock input with internally biased amplifier

2 XOUT O Reference crystal oscillator output

3 VP — Power supply voltage for the charge pump

4 VCC — Power supply voltage

5 DO O Single-ended charge pump output

6 VSS — Ground

7 XFIN I Complementary input for prescaler (normally ac-bypassed via a capacitor)

8 FIN I VCO frequency input with internally biased input amplifier

9 CLK I Shift register clock input

10 DATA I Serial data input

11 LE I Load enable signal input

12 EN I Power-down control

13 ZC I Forced high-impedance control for the charge pump

14 FOLD O Multiplexed CMOS level output (see Functional Description section for programming infor-

mation) 15 φP O Phase comparator N-channel open drain output for an external charge pump 16 φR O Phase comparator CMOS inverter output for an external charge pump PFD LD MUX FIN DA TA CLK LE CONTROL LOGIC SHIFT REGISTER FOLD DO LOCK DETECTOR EN N-LATCH N-COUNTER R-COUNTER CHARGE PUMP OSC N-PRESCALER XOUT XIN R-LATCH XFIN φR φP ZC

VSS = 0 V Recommended Operating Conditions VSS = 0 V Parameter Symbol Rating Unit Supply voltage range VCC VSS – 0.3 to VSS + 4.0 V VP VCC to 6.0 V Input voltage range VFIN VSS – 0.5 to VDD + 0.5 V Output voltage range VO VSS to VCC V VDO VSS to VP V Storage temperature range TSTG –55 to 125 °C Soldering temperature range TSLD 260 °C Soldering time range tSLD 4s ESD rating (human body mode) 3500 eV Parameter Symbol Value Unit min. typ. max. Supply voltage range VCC 2.4 3.0 3.6 V VP Vcc – 5.5 V Operating temperature TA –40 25 80 °C

Electrical Characteristics

(VCC = VP = 3.0 V, VSS = 0 V, TA = –40 to 85 °C unless otherwise noted) Parameter Symbol Condition Value Unit min. typ. max. GENERAL Power supply current consumption ICC,total fin = 2.5 GHz 4 mA Standby current consumption ICC,standby ZC = “H” or open 10 µA FIN operating frequency fFIN VFIN = 0.3 Vpk-pk sinusoid 50 2500 MHz XIN operating frequency fXIN 3 40 MHz Input sensitivity PFIN 50 Ω measurement system -15 +2 dBm XIN input voltage swing VXIN 0.5 VCC Vpk-pk CHARGE PUMP RF charge pump output current IDOsource VDO = VP/2, CS bit = “H” -6 mA IDOsink VDO = VP/2, CS bit = “H” 6m A IDOsource VDO = VP/2, CS bit = “L” -1.5 mA IDOsink VDO = VP/2, CS bit = “L” 1.5 mA DIGITAL INTERFACE (DATA, CLK, LE, PS, ZC) High-level input voltage VIH 0.8×VCC V Low-level input voltage VIL 0.2×VCC V High-level input current IIH VIH = VCC = 3.6V –1 1 µA Low-level input current IIL VIL = 0 V , VCC = 3.6V –1 1 µA XIN logic HIGH input current IIH,XIN VIH = VDD 100 µA XIN logic LOW input current IIL,XIN VIL = 0 V –100 µA φP logic LOW output voltage VOL Open drain output 0.4 V φP logic LOW output current IOL Open drain output 1 mA φR logic HIGH output voltage VOH VCC = VP = 3.0 V , IOH = –1 mA VCC – 0.4 V φR logic LOW output voltage VOL VCC = VP = 3.0 V , IOL = 1 mA 0.4 V φR logic HIGH output current IOH VCC = VP = 3.0 V –1 mA φR logic LOW output current IOL VCC = VP = 3.0 V 1m A

FOLD logic HIGH output voltage VOH VCC = VP = 3.0 V , IOH = –1 mA VCC – 0.4 V FOLD logic LOW output voltage VOL VCC = VP = 3.0 V , IOL = 1 mA 0.4 V FOLD logic HIGH output current VOH VCC = VP = 3.0 V –1 mA FOLD logic LOW output current VOL VCC = VP = 3.0 V 1m A MICROWIRE TIMING DATA to CLK setup time tSU1 10 ns DATA to CLK hold time tHOLD1 10 ns CLK to LE setup time tSU2 20 ns CLK to LE hold time tHOLD2 30 ns LE Pulse width tEW 50 ns (VCC = VP = 3.0 V, VSS = 0 V, TA = –40 to 85 °C unless otherwise noted) Parameter Symbol Condition Value Unit min. typ. max.

Programmable Input Frequency Divider The VCO output to the FIN pin is divided by the programmable divider and then inter- nally output to the phase/frequency detector (PFD) as fV. The programmable input fre- quency divider consists of a multi-modulus (selectable ÷ 32/33 or ÷ 64/65 (M/M+1)) prescaler and a 18-bit N-counter, which is further comprised of a 7-bit swallow A-counter, and a 11-bit main B-counter. The total divide ratio, N, is related to values for M, A, and B through the relation with The minimum programmable divi sor for continuous counting is given by , and is for the ÷ 32/33 prescaler mode, and is for the ÷ 64/65 mode. Hence, the valid total divide ratio range for the input divider is for the ÷ 32/33 mode and for the ÷ 64/65 mode. Programmable Reference Frequency Divider The crystal oscillator output is divided by the programmable reference divider and then internally output to the PFD as fR. The programmable reference frequency divider con- sists of a 14-bit reference R-counter. Becasue of its specific design, the minimum accept- able divisor for R is 3, and hence the total divide ratio, R, ranges from 3 to 16383. Shift Register Configuration The divide ratios for the input and reference dividers are input using a 19-bit serial inter- face consisting of separate clock (CLK), data (DATA), and load enable (LE) lines. The format of the serial data is shown in Table 1. The data on the DATA line is written to the shift register on the rising edge of the CLK signal and is input with MSB first, and the last bit is used as the latch select control bit. The data on the DATA line should be changed on the falling edge of CLK, and LE should be held LOW while data is being written to the shift register. Data is transferred from the shift register to one of the frequency divider latches when LE is set HIGH. When the latch select control bit is set LOW, data is loaded to the 18-bit N-counter latch, and when the latch select control bit is set HIGH, the 4 MSBs are recognized as CS, LDS, FC, SW, respectively, and the next 14 data bits are loaded to the 14-bit R-counter latch. The definition of the 4 MSBs will be described in Table 5 and 6. Note that LDS should be set LOW for normal operation. Also, serial input data timing waveforms are shown in Fig. 1. NM 1+() AM BA –()×+× MBA ,+×== BA .≥ 64 64 1–()× 4032= N 992 to 65631= N 4032 to 131135=

Fig. 1 – Serial data input waveforms tSU1 tSU2 tHOLD1 DATA CLK LE DATA CLK LE MSB 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654319 21 CONTROL Parameter Min. Typ. Max. Unit tSU1 10 – – ns tSU2 20 – – ns tHOLD1 10 – – ns BIT CB Control bit for selecting the 0:N or 1: R latch A1 to A7 Control bits for setting the divide ratio of the programmable swallow counter (0 to 127) N1 to N11 Control bits for setting the divide ratio of the programmable main counter (3 to 2047) R1 to R14 Control bits for setting th e divide ratio of the programmable reference counter (3 to 16383) SW Control bit for setting the divide ra tio of the prescaler (32/33 or 64/65) FC Control bit for setting the polarit y of the phase/frequency detector LDS Control bit for selecting the output for the FOLD pin CS Control bit for setting th e charge pump current level Table 1: Serial data input format 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 C B A A A A A A A N N N N N N N N N N N R R R R R R R R R R R R R R S W F C L D S C S MSBLSB

Table 2: Binary 7-bit data format for swallow counter Divide ratio (A) A A A A A A A 0 0000000 1 0000001 1 2 7 1111111 Table 3: Binary 11-bit data format for main counter Divide ratio (B) N N N N N N N N N N N 3 00000000011 4 00000000100 2047 1 1111111111 Table 4: Binary 14-bit data format for reference counter Divide ratio (R) R R R R R R R R R R R R R R 3 00000000000011 4 00000000000100 1 6 3 8 3 11111111111111 Table 5: Data format for 3 optional bits Bit H L Description SW 32/33 64/65 Prescaler dual-modulus ratio setting CS + 6 mA + 1.5 mA Charge pump current setting LDS FO signal LD signal FOLD output select setting

Phase/Frequency Detector (PFD) The PFD compares an internal i nput frequency divider output signal, fV, with an internal reference frequency divider output signal, fR, and generates an error signal, DO, which is proportional to the phase error between fV and fR. The DO output is intended for use with a passive filter as shown in Fig. 2 (a). The polarity of DO is selectable by setting the bit FC to high or low. The setting should depend on the frequency-voltage characteristic of exter- nal VCO as depicted in Fig. 2 (b). The input/output waveforms for the PFD are shown in Fig. 3. Fig. 2 – Low-pass filter and external VCO frequency-voltage characteristic Table 6: Data format for FC bit (LDS = HIGH) FC = HIGH FC = LOW DO φR φPF O L D D O φR φPF O L D fR > fV HLL FOLD = fR LH Za FOLD = fV fR < fV LHZ HLL fR = fV Z L ZZ L Z a. Z denotes high impedance state DO VCO (a) Passive low-pass filter (1) (2) fVCO VDO (b) VCO frequency-voltage characteristic Note: If VCO has a positive tuning curve similiar to trace (1), set FC = “H,” otherwise if the VCO has a negative tuning curve similar to trace (2), set FC = “L.”

Fig. 3 – Phase comparator output waveforms Charge Pump (CP) The phase error signal, DO, generated from the PFD will pump charge into an external loop filter, which then converts the charge to produce the VCO’s tuning voltage. With a constant pumping rate, the shift of the VCO’s tuning voltage will be directly proportional to the phase error signal DO. Two pumping rates, 1.5 mA and 6 mA, are provided by the chip and are selectable through the bit CS as defined previously in Table 5. Also, the charge pump characteristics corresponding to both modes are shown in the Typical Char- acteristics section. The internal charge pump may be turned off by the pin ZC. When ZC is set low, the internal charge pump will stay in its high-impedance state and will not pump any charge into the external LPF. In this case, the user is allowe d to utilize one’s own charge pump by two control pins φP and φR which are defined in Table 6. φP and φR are the error signals directly proportional to the positive/negative phase error when FC = “H.” When FC = “L,” the relation becomes negative/positive. Table 7: Setting for the pin ZC ZC Do Output H Normal output L High impedance fR fV DO LD [FC=”H”] DO [FC=”L”] 1. Pulses of finite width on DO output are genera ted during locked state to prevent dead zone. 2. A “locked” condition (LD is HIGH) is indicated when the phase error is less than t1 or t2 at least for 3 consecutive comparison cycles, otherwise an “unlocked” condition (LD is LOW) is indicated. 3. The values of t 1 and t2 depend on the XIN input frequency: t 1 > 2/fosc (e.g. t1 > 250 ns, if fXIN = 8 MHz) t 2 > 2/fosc (e.g. t2 > 250 ns, if fXIN = 8 MHz) 4. LD becomes HIGH during power-dow n mode (when EN is set LOW).

Multi-function Lock Detect Output (FOLD) A digital lock detect function is included with the phase detector through an internal digi- tal filter to produce a logic level output whic h is available on the FOLD output pin. The criterion of lock indication de pends on the period of the crysta l oscillator reference. The lock dectect output is HIGH whenever the phase error between pha se detector inputs is less than 2 times of the crystal period for mo re than three consecutive comparison cycles, otherwise is low. Note that LD become s HIGH during the power saving mode. The LD output is depicted in Fig. 3 as well. Power-down Control (EN) By setting the pin EN to LOW, the chip enters into power-down mode, reducing the cur- rent consumption. During the power-down mode, the phase detector output, DO, is set to its high impedance. Normal operation mode resumes when EN is switched to HIGH. To prove a smooth start-up condition, an intermittent control circ uit is activated when the device returns to normal operation. Due to the unknown relationship between fV and fR after returning from power-down, the PFD output is unpredicta ble and may give rise to a significant jump in the VCO’s frequency which will result in an increased lock-up time. To prevent this, the FS8170 employs an intermittent control circuit to limit the magnitude of the error signal generated by the phase detector when it returns to normal operation, thus ensuring a much quicker return to the fully phase-locked condition. Table 8: Setting for the pin EN EN Status H Normal operation mode L Power-down mode

The circuit shown in Fig. 4 is used for measuring the input sensitivity of the FIN input of the PLL. Fig. 4 – FIN input sensitivity test circuit 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 XINXOUTVPVCCDOVSSXFINFIN φPFOLDZCENLEDATACLK φR S.G . S.G. 1000pF 1000pF 50Ω 50Ω 1000pF 0.1µF From Controller Vcc To Counter

Fig. 5 – Input sensitivity vs. frequency -50 -45 -40 -35 -30 -25 -20 -15 -10 SPEC FIN Input Sensitivity (Prescaler: 64/65) Sensitivity (dBm) FIN (GHz) Vcc=2.4V Vcc=3.0V Vcc=3.6V -50 -45 -40 -35 -30 -25 -20 -15 -10 Vcc=2.4V Vcc=3.0V Vcc=3.6V SPEC FIN Input Sensitivity (Prescaler: 32/33) Sensitivity (dBm) FIN (GHz)

Fig. 6 – XIN input sensitivity vs. frequency 0 50 100 150 200 250 -35 -30 -25 -20 -15 -10 SPEC XIN Input Sensitivity Sensitivity (dBm) XIN (MHz) Vcc=2.4V Vcc=3.0V Vcc=3.6V

Charge Pump Characteristic Fig. 7 – Charge pump current vs. VDO Sink State : FR>FV , FC Negative Source State : FR>FV, FC Positive High Current Mode (Ido=6mA) Ido (mA) Vdo (V) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Sink State : FR>FV , FC Negative Source State : FR>FV, FC Positive Low Current Mode (Ido=1.5mA) Ido (mA) Vdo (V)

Supply Voltage Dependence of Charge Pump Current Fig. 8 – Charge pump current vs. supply voltage at VDO = VP/2 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Sink Current Source Current Low Current Mode (1.5mA mode) VDO = 1/2 VP IDO (mA) VP (V) 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 7.2 High Current Mode (6.0mA mode) VDO = 1/2 VP IDO (mA) VP (V) Sink Current Source Current

φR φP FOLD ZC EN LE DATA CLK M C U HiMARK FS8170 1000pF 12K 33pF 33pF 1µF VCC VCO Lock Detect VP VP 12K 10K 10K XIN 1000pF 0.1µF