FS8107E PTC | Alldatasheet
Document overview
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Technical content
Features
High maximum input operating frequency — 100 MHz at V DD1 = 1.0 V Up to 22 MHz internal crystal oscillator reference frequency at VDD1 = 1.0 V Extremely low current consumption (IDD,total typically 0.4 mA at fFIN = 90 MHz) 16-bit programmable input frequency divider (including a ÷ 32/33 prescaler) with divide ratio range from 992 to 65535 13-bit programmable reference frequency divider (including a ÷ 8 prescaler) with divide ratio range from 40 to 65528 Optional lock detector output Charge pump output for passive low-pass filter Quick-lock signal output for faster locking Separate pin for stand-by control TSSOP 16L package (0.65mm pitch)
Applications
Pager Wireless communication system
Package and Pin Assignment: 16L, TSSOP Note: Tolerance + 0.1mm unless otherwise specified Symbols Dimensions in mm Dimensions in inch XIN XOUT VDD2 DB DO VSS FIN VDD1 TEST NC OPR LE DATA CLK LD NC HiMARK FS8107E
Number Name I/O Description 1X I N I Reference crystal oscillator or external clock input with internally biased amplifier (any external input to XIN must be ac-coupled)
2 XOUT O Reference crystal oscill ator or external clock output
3 VDD2 POWER Nominal 3.0 V supply voltage
4 DB O Single-ended quick-lock ou tput for faster locking
5 DO O Single-ended charge pump ou tput for passive low pass filter
6 VSS GND Ground
7F I N I VCO frequency input with internally biased input amplifier (any external input to FIN must be ac-coupled) 8 VDD1 POWER Nominal 1.0 V supply voltage
9 NC NC No connection
10 LD O Lock detector output (high when PLL is locked)
11 CLK I Shift register clock input
12 DATA I Serial data input
13 LE I Latch enable input
14 OPR I Battery-save control input; normal oper ation when high, stand-by mode when low
15 NC NC No connection
16 TEST I Test mode control input wi th internal pull-down resistor
÷ 8 ÷ 32/33 LD DO XOUT LOCK DETECTOR QUICK- DB WINDOW GENERATOR OPR LOCK
VSS = 0 V Recommended Operating Conditions VSS = 0 V Parameter Symbol Rating Unit Supply voltage VDD1 VSS – 0.3 to VSS + 2.0 V VDD2 VSS – 0.3 to VSS + 7.0 V Input voltage range VFIN VSS – 0.3 to VDD + 0.3 V Operating temperature range TOPR –10 to 60 oC Storage temperature range TSTG –40 to 125 oC Soldering temperature range TSLD 255 oC Soldering time range tSLD 10 s Parameter Symbol Value Unit min. typ. max. Supply voltage range VDD1 0.95 1.0 2.0 V VDD2 2.0 3.0 3.3 V Operating temperature TA –10 25 60 oC
Electrical Characteristics
(VDD1 = 0.95 to 2.0 V, VDD2 = 2.7 to 3.3 V, VSS = 0 V, TA = 0 to 60°C unless otherwise noted) Parameter Symbol Condition Value Unit min. typ. max. Current consumption IDD,total VDD1 = 1.0 V , OPR=”H”, VFIN = 0.3 Vpk-pk sinusoid, fFIN = 100 MHz, VXIN = 0.3 Vpk-pk sinusoid, fXIN = 12.8 MHz 0.40 1.10 mA Standby current consumption (IDD2)I DD,standby VDD1 = 0 V , OPR=”L” 10 µA FIN max. operating frequency fFIN,max VFIN = 0.3 Vpk-pk sinusoid 100 MHz FIN min. operating frequency fFIN,min VFIN = 0.3 Vpk-pk sinusoid 40 MHz XIN max. operating frequency fXIN,max VXIN = 0.3 Vpk-pk sinusoid 22 MHz XIN min. operating frequency fXIN,min VXIN = 0.3 Vpk-pk sinusoid 7 MHz FIN input voltage swing VFIN 0.3 Vpk-pk XIN input voltage swing VXIN 0.3 Vpk-pk CLK, DATA, LE logic LOW input voltage VIL 0.3 V CLK, DATA, LE logic HIGH input voltage VIH 1.5 V XIN logic LOW input current IIL,XIN VIL = 0 V 10 µA XIN logic HIGH input current IIH,XIN VIH = VDD1 10 µA FIN logic LOW input current IIL,FIN VIL = 0 V 60 µA FIN logic HIGH input current IIH,FIN VIH = VDD1 60 µA DO logic LOW output current IOL,DOP VOL = 0.4 V 1.0 mA DO logic HIGH output current IOH,DOP VOH = VDD2 – 0.4 V 1.0 mA LD, FV , FR logic LOW output current IOL VOL = 0.4 V 0.1 mA LD, FV , FR logic HIGH output current IOH VOH = VDD2 – 0.4 V 0.1 mA DATA to CLK setup time tSU1 2 µs CLK to LE setup time tSU2 2 µs Hold time tHOLD 2 µs
Programmable Input Frequency Divider The VCO input to the FIN pin is divided by the programmable divider and then internally output to the phase/frequency detector (PFD) as fV. The programmable input frequency divider consists of a ÷ 32/33 (P/P+1) dual-modulus prescaler and a 16-bit (N) counter, which is further comprised of a 5-bit swallow (A) counter, and a 11-bit main (B) counter. The total divide ratio, M, is related to values for P, A, and B through the relation with The minimum programmable diviso r for continuous counting is given by and the valid total divide ratio range for the input divider is Programmable Reference Frequency Divider The crystal oscillator output is divided by the programmable divider and then internally output to the PFD as fR. The programmable reference frequency divider consists of a fixed ÷ 8 (S) prescaler and a 13-bit reference (R) counter. The total divide ratio, T, is related to values for S and R through the relation The usable divisor range of reference counter is and therefore, the valid total divide ratio range for the reference divider is (in steps of 8.) Serial Input Data Format The divide ratios for the input and reference dividers are input using a 17-bit serial inter- face consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The format of the serial data is shown in Fig. 1. The data on the DATA line is written to the shift register on the rising edge of the CLK signal and is input with MSB first, and the last (17th) bit is used as the latch select control bit. The data on the DATA line should be changed on the falling edge of CLK, and LE should be held low while data is being writ- ten to the shift register. Data is transferred from the shift register to one of the frequency divider latches when LE being set high. When the 17th bit is set low, data is loaded to the 16-bit N-counter latch, and when the 17th bit is set high, the 13 MSBs are loaded to the MP 1+() AP BA –()×+× PBA ,+×== BA .≥ M 992 to 65535.= TS R × 8 R.×== R 5 to 8191,= T 40 to 65528=
13-bit R-counter latch and the remaining 3 LSBs are used to control testing modes and should be set as follows for normal operation: R14 = high, R15 = low, R16 = low. To dis- able LD output (i.e. set LD low), R14 should be set low. Serial input data timing waveforms are shown in Fig. 2. Fig. 1 – Serial input data format Fig. 2 – Serial input data timing waveforms CONTROL BIT LSB MSB 16-bit data for N-counter 13-bit data for R-counter R15 R16 R14 tSU1 tSU2 tHOLD DATA CLK LE DATA CLK LE MSB 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 71 LSB CONTROL BIT
Phase/Frequency Detector (PFD) The PFD compares an internal input frequency divider output signal, fV, with an internal reference frequency divider output signal, fR, and generates an error signal, DO, which is proportional to the phase error between fV and fR. The DO output is intended for use with a passive filter as shown in Fig. 3. The input/output waveforms for the PFD are shown in Fig. 4. Fig. 3 – Passive low-pass filter circuit Fig. 4 – PFD input/output waveforms DO to VCO C high-Z high-Z high-Z fR fV DO LD
Quick-lock Signal (DB) The quick-lock output signal, DB, is provided so that the PLL may achieve higher speed locking. When connected, the DB output effectively doubles the charge pump current out- put to the loop filter during the initial start-up of the PLL (when OPR first goes high). Once the PLL phase error is within a specific tolerance, the quick-lock circuitry sets the DB output to a high impedance state and the PLL continues toward lock with its normal charge pump current. Stand-by Mode The stand-by mode for the PLL is entered by setting the OPR pin low and VDD1 to 0 V while the circuit is in operation. In the stand-by mode, the XIN and FIN amplifiers, N- counter, and R-counter are stopped, the N- and R-counters are also reset, and the DO and DB outputs are set to the high impedance state. As long as voltage is supplied to VDD2, data loaded to the latches is kept. To exit from stand-by mode to normal operation, the OPR pin must be set high and voltage must again be supplied to VDD1.
multiplier (×2,3) 2nd LO 1st LO HiMARK FS8107E