FS6407 NXP
Document overview
- Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
- PDF pages: 111
Technical content
Features
- Highly flexible SMPS pre-regulator, allowing two topologies: non-inverting buck-boost and standard buck
- Switching mode power supply (SMPS) dedicated to MCU core supply, from 1.2 V to 3.3 V delivering up to 1.5 A
- Multiple wake-up sources in low-power mode: CAN and/or IOs
- Six configurable I/Os
- Linear voltage regulator dedicated to aux iliary functions, or to a sensor supply (VCCA tracker or independent), 5.0 V or 3.3 V
- Linear voltage regulator dedicated to MCU A/D reference voltage or I/Os supply (VCCA), 5.0 V or 3.3 V
Figure 1. FS6407/FS6408 simplified application diagram - buck boost configuration
Applications
- Automation (PLC, robotics)
- Building control (lift)
- Transportation (mobile machine, military)
- Medical (Infusion pump, stairs) VAUX_E VAUX_B VAUX CAN-5V MOSI MISO SCLK NCS RXDTXD CANH CANL SELECT INTB RSTB FS0B DEBUG IO_0 IO_1 IO_2 IO_3 IO_4 IO_5 GND_COM VDDIO CAN BUS VDDIO Vpre DEBUG mode GNDA DGND Vcore or Vcca VSUP1 SW_PRE2 VPRE SW_CORE FB_CORE VCCA_E VCCA_B VCCA VSENSE COMP_CORE VSUP2 BOOTS_PRE BOOTS_CORE GATE_LS SW_PRE1 VCORE_SNS VSUP3 Input supply VDDIO MUX_OUT Vaux Vcca MCU SPI VDD ADC Input AD ref. voltage NMI Reset FCCU 34FS6407 34FS6408 CAN Ignition VDD
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Figure 2. Simplified application diagram - buck configuration, VAUX not used, VCCA = 100 mA
1 Orderable parts
Table 1. Orderable part variations
- To order parts in Tape & Reel, add the R2 suffix to the part number.
2 Internal block diagram
Figure 3. FS6407/FS6408 simplified internal block diagram
3 Pin connections
3.1 Pinout diagram for FS6407/FS6408
Figure 4. FS6407/FS6408 pinout
3.2 Pin definitions
A functional description of each pin can be found in the functional pin description section beginning on page 22. Table 2. FS6407/FS6408 pin definition and VSUP2 must be connected together externally. 3 VSENSE A_IN Sensing of the battery voltage. Must be c onnected prior to the reverse battery protection diode. diode used for VSUP1. Must be connected between the reverse protection diode and the input PI filter. 5, 22, 23 NC N/A Not connected. Pins must be left open.
6 GND_COM GND Dedicated ground for CAN
7 CAN_5V A_OUT Output voltage for the embedded CAN interface
8 CANH A_IN/OUT HSCAN output High
9 CANL A_IN/OUT HSCAN output Low
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11 IO_4:5 D_IN
Output gate driver: Can drive a logic level low-side NMOS transistor. Controlled by the SPI.
13 IO_0:1 A_IN
connected on VCORE (in parallel to the one used to set the Vcore voltage). detected. Open drain structure.
15 DEBUG D_IN Debug mode entry input
16 AGND GROUND Analog ground connection
19 IO_2:3 D_IN
Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition. 20 TXD D_IN Transceiver input from the MCU which controls the state of the HSCAN bus. Internal pull-up to VDDIO.
21 RXD D_OUT Receiver output which reports the state of the HSCAN bus to the MCU
24 RSTB D_OUT
This output is asserted low when the safety block reports a failure. The main function is to reset the MCU.
28 NCS D_IN No Chip Select (Active low)
29 INTB D_OUT This output pin generates a low pulse when an Interrupt condition occurs. Pulse duration is configurable. 30 VDDIO A_IN Input voltage for MISO output buffer. Allows voltage compatibility with MCU I/Os.
31 SELECT D_IN Hardware selection pin for VAUX and VCCA output voltages
32 FB_CORE A_IN VCORE voltage feedback. Input of the error amplifier. 33 COMP_CORE A_IN Compensation network. Output of the error amplifier.
34 VCORE_SNS A_IN VCORE output voltage sense
35 SW_CORE A_IN VCORE switching point
36 BOOT_CORE A_IN/OUT Bootstrap capacitor for VCORE internal NMOS gate drive
37 VPRE A_OUT VPRE output voltage
Table 2. FS6407/FS6408 pin definition (continued)
44 GATE_LS A_OUT Low-side MOSFET gate drive fo r “Non-inverting Buck-boost” configuration
45 DGND GROUND Digital ground connection
46 BOOT_PRE A_IN/OUT Bootstrap capacitor for the VPRE internal NMOS gate drive
47 SW_PRE2 A_IN Second pre-regulator switching point
48 SW_PRE1 A_IN First pre-regulator switching point
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4 General product characteristics
4.1 Maximum ratings
Table 3. Maximum ratings
- All V SUPS (VSUP1/2/3) must be connected to the same supply (Figure 49)
- All pins (ESD Class 2)
- VSUP1,VSUP2, VSUP3, VSENSE, VAUX, IO_0:1, IO_4:5,FS0B, DEBUG (ESD Class 3A)
- CANH, CANL (ESD Class 3A) Charge Device Model (JESD22/C101):
- All Pins (ESD Class 2)
- Corner Pins (ESD Class 2) System level ESD (Gun Test)
- VSUP1, VSUP2, VSUP3, VSENSE, VAUX, IO_0:1, IO_4:5, FS0B 330 Ω / 150 pF Unpowered According to IEC61000-4-2: 330 Ω / 150 pF Unpowered According to OEM CAN, FLexray Conformance 2.0 kΩ / 150 pF Unpowered According to ISO10605.2008 2.0 kΩ / 330 pF Powered According to ISO10605.2008
- CANH, CANL 330 Ω / 150 pF Unpowered According to IEC61000-4-2: 330 Ω / 150 pF Unpowered According to OEM CAN, FLexray Conformance 2.0 kΩ / 150 pF Unpowered According to ISO10605.2008 2.0 kΩ / 330 pF Powered According to ISO10605.2008 ±2.0 ±4.0 ±6.0 ±500 ±750 ±8.0 ±8.0 ±8.0 ±8.0 ±15.0 ±12.0 ±15.0 ±15.0 kV kV kV V V kV kV kV kV kV kV kV kV (3) Thermal ratings TA Ambient Temperature -40 to 125 °C TJ Junction Temperature -40 to 150 °C TSTG Storage Temperature -55 to 150 °C Thermal resistance RθJA Thermal Resistance Junction to Ambient 30 °C/W (4) RθJCTOP Thermal Resistance Junction to Case Top 24.2 °C/W (5) RθJCBOTTOM Thermal Resistance Junction to Case Bottom 0.9 °C/W (6) Notes 3. Compared to AGND. 4. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012.1). 6. Thermal resistance between the die and the solder par on the bottom of the packaged based on simulation without any interface resistance.
Table 3. Maximum ratings (continued)
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4.2 Static electrical characteristics
Table 4. Operating range
- Buck mode (VSUP > VSUP_UV_7)
- Buck mode (VSUP_UV_7 ≥ VSUP ≥ 4.6 V)
- Boost mode (VSUP ≥ 2.7 V) 6.25 VPRE_UV_4 6.0 VSUP - RDSON_PR E * IPRE 6.75 7.0 V IPRE VPRE Maximum Output Current Capability
- Buck or Boost with VSUP > VSUP_UV_7
- Buck with VSUP_UV_7 ≥ VSUP ≥ 4.6 V
- Boost with VSUP_UV_7 ≥ VSUP ≥ 6.0 V
- Boost with 6.0 V ≥ VSUP ≥ 4.0 V
- Boost with 4.0 V ≥ VSUP ≥ 2.7 V 0.5 1.0 0.3 1.7 1.7 1.7 A (8) IPRE_LPOFF VPRE Maximum Output Current Capability in LPOFF at low VSUP voltage
- Buck with VSUP_UV_7 ≥ VSUP ≥ 4.6 V
- Boost with VSUP_UV_7 ≥ VSUP ≥ 6.0 V
- Boost with 6.0 V ≥ VSUP ≥ 4.0 V
- Boost with 4.0 V ≥ VSUP ≥ 2.7 V 0.05 1.7 1.0 0.3 A (8) IPRE_LIM VPRE Output Current Limitation 3.5 – – A IPRE_OC VPRE Overcurrent Detection Threshold (in buck mode only) 5.0 – – A VPRE_UV VPRE Undervoltage Detection Threshold (Falling) 5.5 – 6.0 V Notes 7. V SUP_UV_L_B = VPRE_UV_4P3 + RDSON_PRE * IPRE 8. Guaranteed by design
- I PRE from 50 mA to 2.0 A - Buck mode –1 0 0–m V (9) LORVPRE_BOOST VPRE Load Regulation for COUT = 57 µF
- I PRE from 50 mA to 2.0 A - Boost mode –5 0 0–m V (9) VPRE_LL_H VPRE_LL_L VPRE Pulse Skipping Thresholds – 200 180 – mV TWARN_PRE VPRE Thermal Warning Threshold – 105 – °C TSD_PRE VPRE Thermal Shutdown Threshold 160 – – °C TSD_PRE_HYST VPRE Thermal Shutdown Hysteresis – 10 – °C (9) VG_LS_OH LS Gate Driver High Output Voltage (IOUT = 50 mA) V PRE-1 – V PRE V VG_LS_OL LS Gate driver Low Level (IOUT = 50 mA) – – 0.5 V Vcore voltage regulator VCORE_FB VCORE Feedback Input Voltage 0.784 0.8 0.816 V ICORE VCORE Output Current Capability in Normal Mode
- FS6407N
- FS6408N 0.8 1.5 A ICORE_LIM VCORE Output Current Limitation
- FS6407N
- FS6408N 1.8 3.5 A RDSON_CORE VCORE Pass Transistor On Resistance – – 200 m Ω LORVCORE_1.2 VCORE Transient Load regulation - 1.2 V range -60 – 60 mV (9), (10) LORVCORE_3.3 VCORE Transient Load regulation - 3.3 V range -100 – 100 mV (9), (10) VCORE_LL_H VCORE_LL_L VCORE Pulse Skipping Thresholds – 180 160 – mV TWARN_CORE VCORE Thermal Warning Threshold – 105 – °C TSD_CORE VCORE Thermal Shutdown Threshold 160 – – °C TSD_CORE_HYST VCORE Thermal Shutdown Hysteresis – 10 – °C (9) Notes 9. Guaranteed by design 10. C OUT = 40 µF, ICORE = 10 mA to 1.5 A, dICORE/dt ≤ 2.0 A/µs
Table 4. Operating range (continued)
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- 5 . 0 V config. with Internal ballast at 100 mA
- 5 . 0 V config with external ballast at 200 mA
- 5 . 0 V config with external ballast at 300 mA
- 3 . 3 V config with Internal ballast at 100 mA
- 3 . 3 V config with external ballast at 200 mA
- 3 . 3 V config with external ballast at 300 mA 4.95 4.9 4.85 3.2505 3.234 3.201 5.0 5.0 5.0 3.3 3.3 3.3 5.05 5.1 5.15 3.3495 3.366 3.399 V (11) ICCA_IN VCCA Output Current (int. MOSFET) – – 100 mA ICCA_OUT VCCA Output Current (external PNP) – – 300 mA ICCA_LIM_INT VCCA Output Current Limitation (int. MOSFET) 100 – 675 mA ICCA_LIM_OUT VCCA Output Current Limitation (external PNP) 300 – 675 mA ICCA_LIM_FB VCCA Output Current Limitation Foldback 80 – 200 mA VCCA_LIM_FB VCCA Output Voltage Foldback Threshold 0.5 – 1.1 V VCCA_LIM_HYST VCCA Output Voltage Foldback Hysteresis 0.03 – 0.3 V ICCA_BASE_SC ICCA_BASE_SK VCCA Base Current Capability – – mA TWARN_CCA VCCA Thermal Warning Threshold (int. MOSFET only) – 105 – °C TSDCCA VCCA Thermal Shutdown Threshold (int. MOSFET only) 160 – – °C TSDCCA_HYST VCCA Thermal Shutdown Hysteresis – 10 – °C (12) LORTVCCA VCCA Transient Load Regulation
- I CCA = 10 mA to 100 mA (internal MOSFET)
- I CCA = 10 mA to 300 mA (external ballast) –– 1 . 0 % (12) Notes 11. External PNP gain within 150 to 450 12. Guaranteed by design.
- I AUX_OUT = 10 mA to 300 mA –– 1 . 0 % (13) CAN_5V voltage regulator VCAN VCAN Output Voltage VSUP > 6.0 V in Buck mode VSUP > VSUP_UV_L in Boost mode 4.8 5.0 5.2 V ICAN_OUT VCAN Output Current – – 100 mA ICAN_LIM VCAN Output Current Limitation 100 – 250 mA TSDCAN VCAN Thermal Shutdown Threshold 160 – – °C TSDCAN_HYST VCAN Thermal Shutdown Hysteresis – 10 – °C (13) VCAN_UV VCAN Undervoltage Detection Threshold 4.25 – 4.8 V VCAN_UV_HYST VCAN Undervoltage Hysteresis 0.07 – 0.22 V VCAN_OV VCAN Overvoltage Detection Threshold 5.2 – 5.55 V VCAN_OV_HYST VCAN Overvoltage Hysteresis 0.07 – 0.22 V LORVCAN VCAN Load Regulation (from 0 to 50 mA) – 100 – mV (13) Notes 13. Guaranteed by design.
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- Min Limit = 2.7 V at VSUP = 40 V 2.6 – – V VIO23_IH Digital High Input voltage level (IO_2, IO_3) 2.0 – – V VIO_IL Digital Low Input voltage Level (IO_0:1; IO_4:5) – – 2.1 V VIO_HYST Input Voltage Hysteresis (IO_0:1, IO_4:5) 50 120 500 mV (16) VIO23_IL Digital Low Input voltage Level (IO_2, IO_3) – – 0.9 V VIO23_HYST Input Voltage Hysteresis (IO_2, IO_3) 200 450 700 mV (16) IIO_IN_0:1 Input Current for IO_0:1 -5.0 – 100 µA IIO_IN_1 Input Current for IO_1 when used for FB_Core monitoring -1.0 – 1.0 µA IIO_IN_2:5 Input Current for IO_2:5 -5.0 – 5.0 µA IIO_IN_LPOFF Input Current for IO_0:5 in LPOFF -1.0 – 1.0 µA Output gate driver VIO_OH High Output Level at IIO_OUT = -2.5 mA V PRE - 1.5 – V PRE V VIO_OL Low Output Level at IIO_OUT = +2.5 mA 0.0 – 1.0 V VIO_OUT_SK VIO_OUT_SC Output Current Capability 2.5 -2.5 mA Analog multiplexer VAMUX_REF1 Internal Voltage Reference with 6.0 V < VSUP < 19 V 2.475 2.5 2.525 V VAMUX_REF2 Internal Voltage Reference with VSUP ≤ 6.0 V or VSUP ≥ 19 V 2.468 2.5 2.532 V VAMUX_TP_CO Internal Temperature sensor coefficient – 9.9 – mV/°C (16) VAMUX_TP Temperature Sensor MUX_OUT output voltage (at TJ=165°C) 2.08 2.15 2.22 V Notes 15. For V SUP < 2.0 V, all supplies are already off and external pull-up on RSTB (e.g VCORE or VCCA) pulls the line down. 16. Guaranteed by design.
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- TX dominant state
- TX recessive state 2.75 2.0 2.5 4.5 3.0 V VCANL CANL Output Voltage (45 Ω < RBUS < 65 Ω)
- TX dominant state
- TX recessive state 0.5 2.0 2.5 2.25 3.0 V VCAN_SYM CAN dominant voltage symmetry (VCANL + VCANH) 4.5 5 5.5 V VOH-VOL Differential Output Voltage
- TX dominant state (45 Ω < RBUS < 65 Ω)
- TX recessive state 1.5 -50 2.0 0.0 3.0 V mV ICANL-SK CANL Sink Current Under Short-circuit Condition (VCANL ≤ 12 V, CANL driver ON, TXD low) 40 – 100 mA ICANH-SC CANH Source Current Under Short-circuit Condition (VCANH = -2.0 V, CANH driver ON, TXD low) -100 – -40 mA RINSLEEP CANH, CANL Input Resistance Device Supplied and in CAN Sleep Mode 5.0 – 50 k Ω
- V SUP and VCAN connected to GND
- V SUP and VCAN connected to GND via 47k resistor -10 -10 µA µA (17) TOT Overtemperature Detection 160 – – °C THYST Overtemperature Hysteresis – – 20 °C Digital interface MISOH High Output Level on MISO (IMISO = 1.5 mA) V DDIO - 0.4 – – V MISOL Low Output Level on MISO (IMISO = 2.0 mA) – – 0.4 V IMISO Tri-state Leakage Current (VDDIO = 5.0 V) -5.0 – 5.0 µA VDDIO Supply Voltage for MISO Output Buffer 3.0 – 5.5 V IVDDIO Current consumption on VDDIO – 1.0 3.0 mA SPILK SCLK, NCS, MOSI Input Current -1.0 – 1.0 µA VSPI_IH SCLK, NCS, MOSI High Input Threshold 2.0 – – V RSPI NCS, MOSI Internal Pull-up (pull-up to VDDIO) 200 400 800 K Ω VSPI_IL SCLK, NCS, MOSI Low Input Threshold – – 0.8 V Debug VDEBUG_IL Low Input Voltage Threshold 2.1 2.35 2.6 V VDEBUG_IH High Input Voltage Threshold 4.35 4.6 4.97 V IDEBUG_LK Input Leakage Current -10 – 10 µA Notes 17. Guaranteed by design and characterization.
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4.3 Dynamic electrical characteristics
Table 5. Dynamic electrical characteristics
- V DDIO = 5.0 V, CLOAD = 50 pF
- V DDIO = 5.0 V, CLOAD = 150 pF 5.0 5.0 ns tCLH Minimum Time SCLK = HIGH 62 – – ns tCLL Minimum Time SCLK = LOW 62 – – ns tPCLD Propagation Delay (SCLK to data at 10% of MISO rising edge) – – 30 ns tCSDV NCS = LOW to Data at MISO Active – – 75 ns tSCLCH SCLK Low Before NCS Low (setup time SCLK to NCS change H/L) 75 – – ns tHCLCL SCLK Change L/H after NCS = low 75 – – ns tSCLD SDI Input Setup Time (SCLK change H/L after MOSI data valid) 40 – – ns tHCLD SDI Input Hold Time (MOSI data hold after SCLK change H/L) 40 – – ns tSCLCL SCLK Low Before NCS High 100 – – ns tHCLCH SCLK High After NCS High 100 – – ns tPCHD NCS L/H to MISO at High-impedance – – 75 ns tONNCS NCS Min. High Time 500 – – ns tNCS_MIN NCS Filter Time 10 – 40 ns
Figure 5. SPI timing diagram Figure 6. Register access restriction
- R LOAD = 120 Ω, C between CANH and CANL = 100 pF, C at RxD < 15 pF – – 255 ns t1PWU Single Pulse Wake-up Time 0.5 – 5.0 µs t3PWU Multiple Pulse Wake-up Time 0.5 – 1.0 µs t3PTO1 Multiple Pulse Wake-up Timeout (120 µs bit selection) 100 120 – µs t3PTO2 Multiple Pulse Wake-up Timeout (360 µs bit selection) 330 360 – µs tCAN_READY Delay to Enable CAN by SPI Command (NCS rising edge) to CAN to Transmit (device in normal mode and CAN interface in TX/RX mode) – – 100 µs (18) Fail-safe state machine OSCFSSM Oscillator 405 – 495 kHz CLKFS_MIN Fail-safe Oscillator Monitoring 150 – – kHz tIC_ERR IO_0:5 Filter Time 4.0 – 20 µs tACK_FS Acknowledgement Counter (used for IC error handling IO_1 and IO_5) 7.0 – 9.7 ms t_DFS_RECOVERY IO_0 Filter Time to Recover from Deep Reset and Fail State 0.8 – 1.3 ms tIO1_DRIFT_MON IO_1 filter time 1.0 – 2.0 ms Fail-safe output tRSTB_FB RSTB Feedback Filter Time 8.0 – 15 µs tFSOB_FB FS0B Feedback Filter Time 8.0 – 15 µs tRSTB_BLK RSTB Feedback Blanking Time 180 – 320 µs tFSOB_BLK FS0B Feedback Blanking Time 180 – 320 µs tRSTB_POR Reset Delay Time (after a Power On Reset or from LPOFF) 12 15.9 23.6 ms (19) tRSTB_LG Reset Duration (long pulse) 8.0 – 10 ms tRSTB_ST Reset duration (short pulse) 1.0 – 1.3 ms tRSTB_IN External Reset Delay time 8.0 – 15 µs tDIAG_SC Fail-safe Output Diagnostic Counter (FS0B) 550 – 800 µs VSUP voltage supply CSUP Minimum capacitor on Vsup 44 – – µF Notes 18. For proper CAN operation, TXD must be set to high level be fore CAN enable by SPI, and must remain high for at least TCAN_READY. 19. This timing is not guaranteed in case of fault duri ng startup phase (after Power On Reset of from LPOFF)
Table 5. Dynamic electrical characteristics (continued)
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- Guaranteed by characterization.
- V DDIO = 5.0 V, CMUX_OUT = 1.0 nF –– 1 0 µs Interrupt tINTB_LG INTB Pulse Duration (long) 90 100 – µs tINTB_ST INTB Pulse Duration (short) 20 25 – µs Functional sate machine tWU_GEN General Wake-up Signal Deglitch Time (for any wu signal on IOs) 60 70 80 µs Notes 21. Guaranteed by characterization.
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5 Functional pin description
5.1 Introduction
The FS6407/FS6408 is the third generation of the System Basis Chip, combining:
- High efficiency switching voltage regulator for MCU, and linear voltage regulators for integrated CAN interface, external ICs such as sensors, and accurate reference voltage for A to D converters.
- Built-in enhanced high-speed CAN interface (ISO11898-2 and -5), wi th local and bus failure diagnostic, protection, and Fail-safe operation mode.
- Low-power mode, with ultra low-current consumption.
- Various wake-up capabilities.
- Enhanced safety features with multiple fail-safe outputs and scheme to support SIL applications.
5.2 Power supplies (VSUP1, VSUP2, VSUP3)
VSUP1 and VSUP2 are the inputs pins for internal supply dedicated to SMPS regulators. VSUP3 is the input pin for internal voltage reference. VSUP1, 2, and 3 are robust against ISO7637 pulses. VSUP1,2, and 3 must be connected to the same supply (Figure 49).
5.3 VSENSE input (VSENSE)
This pin must be connected to the battery line (before the reverse battery protection diode), via a serial resistor. It incorporates a threshold detector to sense the battery voltage, and provide a battery early warning. It also includes a resistor divider to measure the VSENSE voltage via the MUX-OUT pin. VSENSE pin is robust against ISO7637 pulses.
5.4 Pre-regulator (VPRE)
A highly flexible SMPS pre-regulator is implemented in the FS6407/FS6408. It can be configured as a “non-inverting buck-boost converter” (Figure 24) or “standard buck converter” (Figure 23), depending on the external configuration (connection of pin GATE_LS). The configuration is detected automatically during start-up sequence. The SMPS pre-regulator is working in current mode control and the compensation network is fully integrated in the device. The high-side switching MOSFET is also integrated to make the current control easier. The pre-regulator delivers a typical output voltage of 6.5 V, which is used internally. Current limitation, overcurrent, overvoltage, and undervoltage detectors are provided. VPRE is enabled by default. 5.5 VCORE output (from 1.2 V to 3.3 V range) The VCORE block is an SMPS regulator. The voltage regulator is a step down DC-DC converter operating in voltage control mode. The output voltage is configurable from 1.2 V to 3.3 V range thanks to an external resistor divider connected between VCORE and the feedback pin (FB_CORE) (as example in Figure 1, Figure 2, and Figure 49). The stability of the converter is done externally, by using the COMP_CORE pin. Current limitation, overvoltage, and undervoltage detectors are provided. VCORE can be turned ON or OFF via a SPI command, however it is not recommended to turn OFF VCORE by SPI when VCORE is configured safety critical (both overvoltage and undervoltage have an impact on RSTB and FS0B). VCORE overvoltage information disables VCORE. Diagnostics are reported in the dedicated register and generate an Interrupt. VCORE is enabled by default.
impact on RSTB and FS0B). VCCA overcurrent (with the use of external PNP only) and overvoltage information disables VCCA. Diagnostics are reported in the dedicated register and generate an Interrupt. VCCA is enabled by default. generates an Interrupt. VAUX is enabled by default.
5.8 SELECT input (VCCA, VAUX voltage configuration)
VCCA and VAUX output voltage configurations are set by connecting an external resistor between the SELECT pin and Ground. the dedicated register via the SPI. Table 6. VCCA/VAUX voltage selection (Figure 50) Table 7. VCCA voltage selection (VAUX not used, Figure 51, Figure 52)
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5.9 CAN_5V voltage regulator
The CAN_5V voltage regulator is a linear regulator dedicated to the internal HSCAN interface. An external capacitor is required. Current limitation, overvoltage, and undervoltage detectors are provided. If the internal CAN transceiver is not used, the CAN_5V regulator can supply an external load (CAN_5V voltage regulator). CAN_5V is enabled by default.
5.10 Interrupt (INTB)
The INTB output pin generates a low pulse when an Interrupt condition occurs. The INTB behavior as well as the pulse duration are set through the SPI during INIT phase. INTB has an internal pull-up resistor connected to VDDIO.
5.11 CANH, CANL, TXD, RXD
These are the pins of the high speed CAN physical interface. The CAN transceivers provides the physical interface between the CAN protocol controller of an MCU and the physical dual wires CAN bus. The CAN interface is connected to the MCU via the RXD and TXD pins.
5.11.1 TXD
TXD is the device input pin to control the CAN bus level. TXD is a digital input with an internal pull-up resistor connected to VDDIO. In the application, this pin is connected to the microcontroller transmit pin. In Normal mode, when TXD is high or floating, the CANH and CANL drivers are OFF, setting the bus in a recessive state. When TXD is low, the CANH and CANL drivers are activated and the bus is set to a dominant state. TXD has a built-in timing protection that disables the bus when TXD is dominant for more than TDOUT. In LPOFF mode, VDDIO is OFF, pulling down this pin to GND.
5.11.2 RXD
RXD is the bus output level report pin. In the application, this pin is connected to the microcontroller receive pin. In Normal mode, RXD is a push-pull structure. When the bus is in a recessive state, RXD is high. When the bus is dominant, RXD is low. In LPOFF mode, this pin is in high-impedance state.
5.11.3 CANH and CANL
These are the CAN bus pins. CANL is a low-side driver to GND, and CANH is a high-side driver to CAN_5V. In Normal mode and TXD high, the CANH and CANL drivers are OFF, and the voltage at CANH and CANL is approximately 2.5 V, provided by the internal bus biasing circuitry. When TXD is low, CANL is pulled to GND and CANH to CAN_5V, creating a differential voltage on the CAN bus. In LPOFF mode, the CANH and CANL drivers are OFF, and these pins are pulled down to GND via the device RIN_CHCL resistors. CANH and CANL have integrated ESD protection and extremely high robustness versus external disturbance, such as EMC and electrical transients. These pins have current limitation and thermal protection.
5.12 Multiplexer output MUX_OUT
The MUX_OUT pin (Figure 7) delivers analog voltage to the MCU ADC input. The voltage to be delivered to MUX_OUT is selected via the SPI, from one of the following parameters:
- Internal 2.5 V reference
- Die temperature sensor T(°C) = (V AMUX - VAMUX_TP) / VAMUX_TP_CO + 165 Voltage range at MUX_OUT is from GND to VDDIO (3.3 V or 5.0 V)
Figure 7. Simplified analog multiplexer block diagram
5.13 I/O pins (I/O_0:I/O_5)
The FS6407/FS6408 includes six multi-purpose I/Os (I/O_0 to I/O_5). I/O_0, I/O_1, I/O_4, and I/O_5 are robust against ISO7637 pulses. An external serial resistor must be connected to those pins to limit the current during ISO pulses.
- IO_0:1 are selectable as follows: Analog input (load dump proof) sent to the MCU through the MUX_OUT pin. Wake-up input on the rising or falling edge or based on the previous state. Digital input (logic level) sent to the MCU through the SPI. Safety purpose: Digital input (logic level) to perform an IC error monitoring (both IO_0 AND IO_1 are used if configured as safety inputs, see Figure 9).
- IO_1 is also selectable as follow: Safety purpose: FB_Core using a second resistor bridge (R3/R4 duplicated) connected to IO_1, to detect external resistor drift and trigger when FB_Core - IO_1 > ±150 mV max.
- IO_2:3 are selectable as follows: Digital input (logic level) sent to the MCU through the SPI. Wake-up input (logic level) on the rising or falling edge or based on the previous state. Safety purpose: Digital input (logic level) to monitor MCU error signals (both IO_2 AND IO_3 are used if configured as safety inputs). Only bi-stable protocol is available. When IO_2:3 are used as safety inputs to monitor FCCU error outputs from the NXP MCU, the monitoring is active only when the Fail-safe sate machine is in “normal WD running” state (Figure 11) and all the phases except the “Normal Phase” are considered as an Error.
Table 8. I/Os configuration
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Figure 8. IO_2:3 MCU error monitoring: bi-stable protocol
- IO_4:5 are selectable as follows: Digital input (logic level) sent to the MCU through the SPI. Wake-up input (load dump proof) on rising or falling edge or based on previous state. Output gate driver (from VPRE) for low-side logic level MOSFET. Safety purpose: Digital input (logic level) to perform an IC error monitoring (both IO_4 AND IO_5 are used if configured as safety inputs, see Figure 9).
Figure 9. External error signal handling
5.14 SAFE output pi ns (FS0B, RSTB)
FS0B pin, when the application is ready to start. An external pull-up circuitry is mandatory connected to VDDIO or VSUP3.
- If the pull-up is connected to VDDIO, the value recommended is 5.0 kΩ. There is no current in LPOFF since VDDIO is OFF in the LPOFF mode.
- If the pull-up is connected to VSUP3, the value must be above 10 kΩ. There is a current in the pull-up resistor to consider at the application level in LPOFF mode. FCCU_eout[0] FCCU_eout[1] Reset Phase Normal Phase Error Phase Config Phase FS6407/FS6408 Internal IO_4 signal latched Error signal (IO_4 input) Acknowledgment counter Acknowledgement signal from MCU (IO_5 input) Filter time Reset counter Restart Acknowledgment counter FS0b RSTb The error is acknowledged by the MCU then, internal IO_4 signal is released The error is NOT acknowledged by the MCU So, FS0b is activated at the end of the counter
The RSTB pin must be connected to the MCU and is active low. An external pull-up resistor must be connected to VDDIO. In default configuration, the RST delay time has three possible values depending on the mode and product configuration:
- The longest one is used automatically following a Power On Reset or when resulting from LPOFF mode (Low Power Off).
- The two reset durations are then available in the INIT_FSSM1 register, which are 1.0 ms and 10 ms. The configured duration is used in the normal operation when a fault occurs leading to a reset activation. The INIT_FSSM1 register is available (writing) in the INIT FS phase.
5.15 DEBUG input (entering in debug mode)
The DEBUG pin allows the product to enter Debug mode. To activate Debug mode, the voltage applied to the DEBUG pin must be within the VDEBUG_IL and VDEBUG_IH range at start-up. If the voltage applied to DEBUG pin is out of these limits before VCORE ramp-up, the device settles into Normal mode. When Debug mode is activated, the FS0B output is asserted low at start-up. As soon as the FS0B is released to “high” via SPI (Good WD answer and FS_OUT writing), this pin is never activated, whatever the fault is reported. In Debug mode, any errors from the watchdog are ignored (No reset and No fail-safe), even if the whole functionality of the watchdog is kept ON (Seed, LFSR, Wd_refresh counter, WD error counter). This allows an easy debug of the hardware and software routines (i.e. SPI commands). When Debug mode is activated, the CAN transceiver is set to Normal operation mode. This allows communication with the MCU, in case SPI communication is not available (case of MCU not programmed). To exit Debug mode, the pin must be tied to ground through an external pull-down resistor or to VPRE through an external pull-up resistor and a Power On Reset occurs.
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6 Functional device operation
6.1 Mode and state description of main state machine
The device has several operation modes. The transition and conditions to enter or leave each mode are illustrated in the functional state diagram (Figure 10). Two state machines are working in parallel. The Main state machine is in charge of the power management (VPRE,
6.1.1 Buck or buck boost configuration
An external low-side logic level MOSFET (N-type) is required to operate in non-inverting buck-boost converter. The connection of the external MOSFET is detected automatically during the start-up phase (after a Power On Reset or From LPOFF).
- If the external low-side MOSFET is NOT connected (GATE_LS pin connected to PGND), the product is configured as a standard buck converter.
- If the external low-side MOSFET is connected (GATE_LS pin con nected to external MOSFET gate), the product is configured as a non-inverting buck-boost converter. The automatic detection is accomplished by pushing a 300 μA current on Gate_LS pin and monitoring the corresponding voltage generated. If a voltage >120 mV is detected before the 120 μs timeout, the non-inverting buck-boost configuration is locked. Otherwise, the standard buck configuration is locked. The boost driver has a current capability of ±300 mA.
6.1.2 VPRE on
Pre-regulator is an SMPS regulator. In this phase, the pre-regulator is switched ON and a softstart with a specified duration tPRE_SOFT is started to control the VPRE output capacitor charge.
6.1.3 Select pin configuration
This phase is detecting the required voltage level on VAUX and VCCA, according to resistor value connected between the SELECT pin and ground. If the SELECT pin is connected to VPRE via the resistor, it disables the VAUX regulator at start-up.
6.1.4 VCORE/VAUX/VCCA on
In this stage, the three regulators VCORE, VAUX, and VCCA are switched ON at the same time with a specified soft start duration. The CAN_5V is also started at that time.
6.1.5 INIT main
This mode is automatically entered after the device is “Powered ON”. When RSTB is released, initialization phase starts where the device can be configured via the SPI. During INIT phase, some registers can only be configured in this mode (refer to Table 14 and Table 15). Other registers can be written in this mode, and also in Normal mode. Once the INIT registers configurations are complete, a last register called “INIT INT” must be configured to switch to Normal mode. Writing data in this register (even same default values), automatically locks the INIT registers, and the product switches automatically to Normal mode in the Main state machine.
6.1.6 Normal
In this mode, all device functions are available. This mode is entered by a SPI command from the INIT phase by writing in the INIT INT register. While in Normal mode, the device can be set to Low Power mode (LPOFF) using secured SPI command.
6.1.7 Low-power mode off
The Main State Machine has 3 LPOFF modes with different conditions to enter and exit each LPOFF mode as described here after. After wake up from LPOFF, all the regulators are enabled by default. In LPOFF, all the regulators are switched OFF. The register configuration, the VPRE behavior and the ISO pulse requirement are valid for the 3 LPOFF modes.
6.1.7.1 LPOFF - sleep
Entering in Low Power mode LPOFF - SLEEP is only available if the product is in Normal mode by sending a secured SPI command. In this mode, all the regulators are turned OFF and the MCU connected to the VCORE regulator is unsupplied. Before entering in LPOFF Power mode OFF-sleep, the Reset Error Counter must go back to value “0” (“N” consecutive good watchdog refreshes decrease the reset error counter to 0). “N” = RSTb_err_2:0 x (WD_refresh_2:0 + 1). Once the FS6407/FS6408 is in LPOFF - SLEEP, the device monitors external events to wake-up and leave the Low Power mode. The wake-up events can occur and depending of the device configuration from:
- C A N
- I/O inputs When a wake-up event is detected, the device starts the main state machine again by detecting the VPRE configuration (BUCK or BUCK- BOOST), the wake-up source is reported to the dedicated SPI register, and the Fail-safe state machine is also restarted.
6.1.7.2 LPOFF - V PRE_UV
LPOFF- VPRE_UV is entered when the device is in the INIT or Normal mode, and if the VPRE voltage level is passing the VPRE_UV_L_4P3 threshold (typ 4.3 V). After 1.0 ms the device attempts to recover by switching ON the VPRE again.
6.1.7.3 LPOFF - deep FS
LPOFF - DEEP FS is entered when the device is in Deep Fail-safe and if the Key is OFF (IO_0 is low). To exit this mode, a transition to high level on IO_0 is required. IO_0 is usually connected to key ON key OFF signal.
6.1.7.4 Register configuration in LPOFF
In LPOFF, the register settings of the main state machine are kept because the internal 2.5 V main digital regulator is available for wake- up operation. However, the register settings of the fail-safe state machine are erased, because the 2.5 V fail safe digital regulator is not available in LPOFF. As a consequence, after a wake-up event, the configuration of the fail-safe registers must be done again during initialization phase (256 ms open window).
6.1.7.5 V PRE behavior in LPOFF
When device is in LPOFF Sleep mode, and if the VSUP < VSUP_UV_7, VPRE is switched on to maintain internal biasing and wake-up capabilities on IOs or CAN.
- I f VPRE is configured as a non-inverting buck-boost converter, VPRE is switched ON in SMPS mode with boost functionality.
- I f VPRE is configured as a standard buck converter, VPRE is switched ON in Linear mode following VSUP.
6.2 Mode and state description of fail-safe state machine
6.2.1 LBIST
Included in the fail-safe machine, the Logic Built-in Self Test (LBIST) verifies the correct functionality of the FSSM at start-up. The fail-safe state machine is fully checked and if an issue is reported, the RSTB stays low and after 8 s, the device enters in DEEP Fail-safe. LBIST is run at start-up and after each wake-up event when the device is in LPOFF mode.
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6.2.2 Select pin configuration
VAUX for the voltage supervision.
6.2.3 ABIST
the overvoltage and undervoltage detections of the voltage supervisor and the RTSTB and FS0B fail-safe outputs feedback (Table 9). The ABIST is run at start-up and after each wake-up event when the device is in LPOFF mode.
6.2.4 Release RSTB
In this state, the device releases the RSTB pin.
6.2.5 INIT FS
is requested). Faults leading to an “Activate RST” are described in Reset error counter. leaves this mode and goes into Normal WD mode.
6.2.6 Normal WD is running
In this mode, the device waits for a periodic watchdog refresh coming from the MCU, within a specific configured window timing. bad watchdog refreshes, if there is an external reset request, or if a fault occurs leading to an RSTB activation.
6.2.7 RST delay
time is configurable via the SPI in the INIT_ FSSM1 register, which is accessible for writing only in the INIT FS phase. Table 9. Regulators and fail-safe pins checked during ABIST
6.3 Deep fail-safe state
The Fail-safe state machine monitors the RSTB pin of the device and count the number of reset(s) happening in case of fault detection (see Reset error counter). As soon as either the reset error counter reach its final value or the RESET pin remains asserted low for more than 8.0 s, the device moves to Deep Fail-safe state, identified by the “Wait Deep Fail-safe” state in the functional state diagram (Figure 10). When the device is in Deep Fail-safe state, all the regulators are OFF. To exit this state, a Key OFF / Key ON action is needed. IO_0 is usually connected to key signal. Key OFF (IO_0 low) moves the device to LPOFF-Deep FS, and Key ON (IO_0 high) wakes up the device. The final value of the reset error counter can be configured to 2 or 6 in the register INIT FSSM 2. During power up phase, the 8.0 s timer starts when the Fail-safe state machine enters in the “Select pin config detection” state and stop when the RSTB pin is released. During “INIT FS” state, the 8.0 s timer can be disabled in the register INIT SUPERVISOR 2. During “Normal WD running” state, the 8.0 s timer is activated at each RSTB pin assertion.
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6.4 Functional state diagram
Figure 10. Simplified state diagram
6.5 Fail-safe machine
electrically independent from the rest of the circuitry, to avoid common cause failure. bonding wire per pin is used). Additionally, the ground connection is redundant as well to avoid any loss of ground. handling and controls the fail-safe outputs. handle the different kinds of failures, and to give a chance for the system to come back to a normal state.
6.5.1 Fail-safe machine state diagram
Figure 11. Detailed fail-safe state diagram
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6.5.2 Watchdog operation
the right voltage on the DEBUG pin at start-up. The watchdog can also be inhibited through the SPI register to allow “reprogramming” (ie.at vehicle level through CAN). window is considered a wrong WD refresh.
6.5.2.1 Normal operati on (first watchdog refresh)
a simple calculation based on this formula. As an example, the result of this calculation based on LFSR default value (0xB2) is 0x4D. Figure 12. Watchdog answer calculation Table 73. If the watchdog refresh is wrong or if the watchdog is not refreshed during this 256 ms open window (INIT FS phase), the device asserts the reset low and the RSTB error counter is incremented by “1”.
6.5.2.2 Normal watchdog refresh
restarts the window. This ensures the synchronization between MCU and FS6407/FS6408.
- The new WD window duration (except after disable) is taken into account when a write in the WD_answer register occurs (good or bad WD answer) or when the previous WD window is finished without any writing (WD timeout)
- The new WD window duration after disable is taken into account when SPI command is validated The duty cycle of the window is set to 50% and is not modifiable.
Figure 13. Windowed watchdog
6.5.2.3 Watchdog in debug mode
counter, and reset counter. This allows the user to debug their software and ensure a good watchdog strategy in the application.
6.5.2.4 Wrong watchdog refresh handling
On Reset or a transition on IO_O helps the system to recover.
6.5.2.5 Watchdog error counter
value of this counter is configurable in the INIT_WD register, but only when device is in INIT FS mode. Figure 14. Watchdog error counter configuration (INIT_WD register, bits WD_CNT_error_1:0)
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6.5.2.6 Watchdog refresh counter
error counter is decremented by “1” (case with WD_CNT_refresh_1:0 configured at 6). register, but only when device is in INIT FS mode. Figure 15. Watchdog refresh counter configuration (INIT_WD register, WD_CNT_refresh_1:0) meaning no WD refresh during closed or open windows, is considered as a wrong WD refresh. Table 10. Watchdog error table
1 WD Refresh NOK /
6.5.3 Reset error counter
The reset error counter manages the reset events and counts the number of resets occurring in the application. This counter is incremented not only for the reset linked to consecutive wrong refresh watchdogs, but also for other sources of reset (undervoltage, overvoltage, external reset). The RST error counter is incremented by 1, each time a reset is generated. The reset error counter has two output values (intermediate and final). The intermediate output value is used to handle the transition from reset (RSTB is asserted low) to reset and fail where RSTB and FS0B are activated. The final value is used to handle the transition from reset and fail to deep reset and fail (Deep Fail-safe mode), where regulators are off, RSTB and FS0B are activated, and a power on reset or a transition on IO_0 is needed to recover. The intermediate value of the reset error counter is configurable to “1” or “3” using the RSTB_err_FS bit in the INIT FSSM2 register (Table 70). If RSTB_err_FS is set to “0”, it means the device activates FS0B when the reset error counter reaches level “3”. If RSTB_err_FS is set to “1”, it means the device activates FS0B when the reset error counter reaches level “1”. This configuration must be done during INIT FS phase. The final value of the reset error counter is based on the intermediate configuration.
- RSTB_err_FS = 0 / Intermediate = 3; Final = 6 (Figure 16). When reset error counter reaches 6, the device goes into deep reset and fails.
- RSTB_err_FS = 1 / Intermediate = 1; Final = 2 (Figure 17). When reset error counter reaches 2, the device goes into deep reset and fails. In any condition, if the RSTB is asserted LOW for a duration longer than eight seconds, the device goes into deep reset and fails. Conditions leading to an increment of the RSTB error counter, and according to the product configuration are:
- Watchdog error counter = 6
- Watchdog refresh NOK during INIT phase or Watchdog timeout
- IO_23 error detection (FCCU)
- Undervoltage
- Overvoltage
- IO_1 FB_Core Delta
- FS0B shorted to VDD
- S P I D E D
- Reset request by the SPI
- External reset Conditions leading to a transition go to FS, according to the product configuration are:
- IO_01/IO_23/IO_45 error detection
- Undervoltage
- Overvoltage
- IO_1 FB_Core Delta
- Analog BIST fail
- S P I D E D
- RSTB shorted to high
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Figure 16. RSTB error counter (RSTB_err_FS = 0) Figure 17. RSTB error counter(RSTB_err_FS = 1)
6.5.3.1 RST error counter at st art-up or resuming from LPOFF mode
counter down to 0) and a right command is sent to FS_OUT register (Figure 20). Figure 18. Example of WD operation generating a reset (WD_error_cnt = 6) Figure 19. Example of WD operation leading a decrement of the reset error counter (WD_resfresh_cnt = 6)
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Figure 20. Reset error counter and FS0B deactivation sequence (RSTB_err_FS = 0 & WD_CNT_error1:0 = 6)
6.5.4 Fail-safe output (FS0B) deactivation
- Fault is removed
- Reset error counter must be at “0”
- FS_OUT register must be filled with the right value.
6.5.4.1 Faults triggering FS0B activation
- IO_01/IO_23/IO_45 error detection
- Undervoltage
- O v e r v o l t a g e
- IO_1 FB_Core Delta
- Analog BIST fail (not configurable)
- SPI DED (not configurable)
- RSTB shorted to high (not configurable)
- RSTB error counter level
6.5.5 SPI DED
Event Upset). Only fail-safe registers are concerned. During INIT FS mode, access to fail-safe registers for product configuration is open. Then once the INIT FS phase is over, the Hamming circuitry is activated to protect registers content. code but detected errors cannot be corrected. The flag is sent, RSTB and FS0B are activated.
6.5.6 FS_OUT register
value is dependant on the current WD_LFSR. LSB and MSB must be swapped and negative operation per bit must be applied. Figure 21. FS_OUT register based on LFSR value
6.6 Input voltage range
can still be covered using only the Buck configuration. Figure 22. Input voltage range
- Thermal dissipation must be checked based on application use case to maintain junction temperature (T J) <150 °C
- Buck only, V SUP < VSUP_UV_7: CAN communication is guaranteed for VSUP > 6.0 V. For VCCA and VAUX 5.0 V configuration, undervoltage triggers at low VSUP (refer to VCCA_UV_5 and VAUX_UV_5).
6.7 Power management operation
when the junction temperature of the pass transistor decrease below the TSD threshold.
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6.7.1 VPRE voltage pre-regulator
automatically during the start-up phase. regulated between 6.0 V and 7.0 V. fulfill application needs while the current load remains below the maximum current capability in all conditions. Figure 23. Pre-regulator: buck configuration Figure 24. Pre-regulator: buck boost configuration by the device at VSUP_UV_7 threshold. Transition between buck mode and boost mode is based on hysteresis (Figure 25).
- When VSUP > V SUP_UV_7, the converter works in Buck mode and the VPRE output is regulated at 6.5 V typical
- When VSUP < V SUP_UV_7, the converter works in Boost mode and the VPRE output is regulated at 6.3 V typical SW_pre2 VPRE Boots_pre Gate_LS SW_pre1 L_VPRE Cboot_pre Csnub_Vpre Rsunb_Vpre PGND PGND PGND D_Vpre PGND PGND PGND ESR cap. <100 mΩ ESR cap. <10 mΩ PGND Cout_Vpre1 Cout_Vpre2 Cout_Vpre3 Cout_Vpre4 SW_pre2 VPRE Boots_pre Gate_LS SW_pre1 L_Vpre Cboot_pre Csnub_Vpre Rsunb_Vpre PGND PGND PGND Optional D_Vpre LS_BB D_BB PGND PGND PGND ESR cap. <100 mΩ ESR cap. <10 mΩ PGND Cout_Vpre1 Cout_Vpre2 Cout_Vpre3 Cout_Vpre4
Figure 25. Transition between buck and boost
6.7.1.1 Power up and power down sequence
Figure 26. Buck configuration power up and power down
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Figure 27. Buck boost configuration power-up and power-down
6.7.1.2 Low VSUP management
current guaranteed on VPRE.. Figure 28. Behavior at low VSUP (buck configuration)
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Figure 29. Behavior at low VSUP (buck boost configuration)
6.7.1.3 Light load condition
Pulse Skipping mode during light load condition. Figure 30. Description of light load condition
6.7.1.4 Overcurrent detecti on and current limitation
6.7.1.4.1 Overcurrent protection:
blanked when the pass transistor is switched ON during TPRE_OC to avoid parasitic switch OFF of the high-side gate driver.
6.7.1.4.2 Current limitation:
the next rising edge of the switching clock. limitation does not switch OFF the regulator. The current limitation protects the regulator when VPRE pin is shorted to GND. Figure 31. Overcurrent and current limitation scheme
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6.7.1.5 VPRE voltage monitoring
reporting an undervoltage. Diagnostic is reported in the dedicated register and generate an Interrupt. configuration (registers INIT SUPERVISOR 1, 2, 3).
6.7.1.6 V PRE efficiency
to be verified by measurement at application level. Figure 32. VPRE efficiency
6.7.2 VCORE voltage regulator
to use 1.0% accuracy resistors and set R4 = 8.06 kΩ and adjust R3 to obtain the final VCORE voltage needed for the MCU core supply.
Figure 33. VCORE buck regulator
6.7.2.1 Light load condition
6.7.2.2 Current limitation
again before the next rising edge of the switching clock. undervoltage condition and bring the device into the Fail-safe state. The current limitation does not switch OFF the regulator.
6.7.2.3 Voltage monitoring
(registers INIT SUPERVISOR 1, 2, 3).
6.7.2.4 V CORE efficiency
the recirculation phase. Lower the diode forward voltage (VF) is, the better the efficiency.
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Figure 34. VCORE efficiency
6.7.3 Charge pump and bootstrap
6.7.4 VCCA voltage regulator
configuration and ±1.5% for 3.3 V configuration with an output current capability at 100 mA. configured as a tracking regulator.
6.7.4.1 Current limitation
the current limitation threshold is selected based on the auto detection of the external PNP during start up phase.
- When the internal MOSFET transistor is used, the current is limited to I CCA_LIM_INT and the regulator is kept ON
- When the external PNP transistor is used, the current is limited to ICCA_LIM_OUT and the regulator is switch OFF after a dedicated duration TCCA_LIM_OFF under current limitation. A SPI command is needed to restart the regulator. In case of external PNP configuration only, the lowest current limitation threshold can be selected by SPI in the register INIT VREG 2 instead of the highest one. In order to limit the power dissipation in the external PNP transistor in case of short circuit to GND of VCCA pin, a current limitation foldback scheme is implemented to reduce the current limitation to ICCA_LIM_FB when VCCA is below VCCA_LIM_FB.
6.7.4.2 Voltage monitoring
configuration (registers INIT SUPERVISOR 1, 2, 3).
6.7.5 VAUX voltage regulator
VAUX_E and SELECT pins must be connected to VPRE to not populate the external PNP, as described in Figure 51. the INIT phase and secured (bit VAUX_TRK_EN in the register INIT VREG2). The tracking accuracy is ±15 mV. Figure 35. Example of VAUX used in tracker mode
6.7.5.1 Current limitation
foldback scheme is implemented to reduce the current limitation to IAUX_LIM_FB when VAUX is below VAUX_LIM_FB.
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Figure 36. VAUX current limitation scheme with foldback mechanism
6.7.5.2 Voltage monitoring
configuration (registers INIT SUPERVISOR 1, 2, 3).
6.7.6 CAN_5V voltage regulator
never asserts RSTB or the FS0B Fail-safe pins. must be put in Sleep mode without wake-up capability.
6.7.7 Power dissipation
- V PRE (6. 5V) up to 2.0 A
- V CORE (from 1.2 V to 3.3 V range) up to 0.8 A (FS6407) or up to 1.5 A (FS6408)
- V CCA (3.3 V or 5.0 V) up to 100 mA (with internal MOS) or up to 300 mA (with external PNP)
- V AUX (3.3 V or 5.0 V) up to 300 mA (with external PNP)
- V CAN (5.0 V) up to 100 mA A thermal dissipation analysis has to be performed based on application use case to ensure the maximum silicon junction temperature does not exceed 150 °C. Two use cases covering the two main VCORE voltage configurations are provided in Figure 37.
- use case 1: V CORE = 3.3 V, ICORE = 0.7 A, VCCA with int. MOS
- use case 2: V CORE = 1.2 V, ICORE = 1.4 A, VCCA with ext. PNP Both use cases have a total internal power dissipation below 0.9 W. A junction to ambient thermal resistivity of 30 °C/W allows the application to work up to 125 °C ambient temperature. A good soldering of the package expose pad is highly recommended to achieve such thermal performance. Iaux_LIMIaux_LIM_FB IAUX VAUX Vaux (3.3Vor 5V) Vaux_LIM_FB
Figure 37. Power dissipation use case 1) CAN transceiver dissipation includes CAN_5V regulator dissipation. 2) 25% CAN traffic means the CAN bus is dominant for 25% of time and recessive for the remaining 75%.
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Figure 38. Power dissipation versus ICORE, ICCA, or IPRE
6.7.8 Start-up sequence
different voltage rails automatically start, as described in Figure 39. Figure 39. Start-up scheme monitoring the RSTB pin low, finally sends the device in Deep Fail-safe mode after 8.0 s.
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6.8 CAN transceiver
Figure 40. CAN simplified block diagram
6.8.1 Operating modes
6.8.1.1 Normal mode
internal pull-up resistor TXDPULL-UP connected to VDDIO.
Figure 41. CAN timing diagram
6.8.1.2 Sleep mode
and RXD pins are pulled down to GND, both driver and receiver are OFF. device enters is LPOFF. After LPOFF, the initial CAN mode prior to enter LPOFF is restored (Figure 42). Figure 42. CAN transition when device goes to LPOFF
6.8.2 Fault detection
6.8.2.1 TXD permanent dominant (timeout)
operating when the CAN transceiver is in Normal mode and Listen Only mode.
0 Sleep, no wake-up capab ility 0 Sl eep, no wake-up capability 0 Sleep, no wake-up capability
1 Listen Only 1 Listen Only
10 Sleep, wake-up capability 10 Sleep, wake-up capab ility
11 Normal 11 Normal
10 Sleep, wake-up capability
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Figure 43. TXD dominant timeout detection
6.8.2.2 RXD permanent recessive
level, and seen from a CAN controller as a bus idle state.
6.8.2.3 CAN bus short-circuits
receiver are not be disabled. The CANH and CANL failure detection is operating when the CAN transceiver is in Normal mode. is operating when the CAN transceiver is in Normal mode and Listen Only mode.
6.8.2.4 CAN current limitation
6.8.2.5 CAN overtemperature
receiver continues to operate. The CAN_mode MSB bit is set to 0 and the flag CAN_OT is reported in the Diag CAN register. detection after setting the CAN_mode to Normal operation and when a high level is detected on TXD.
Figure 44. Overtemperature behavior
6.8.2.6 Distinguish CAN diagnostics and CAN errors
CAN Error bits are provided in Table 11.
6.8.3 Wake-up mechanism
the t3PTOX timeout. t3PTOX = t3PTO1 or t3PTO2, depending on the SPI selection. Table 11. CAN diagnostic and CAN error bits Event 1: over temperature detection. CAN driver disable. Event 2: temperature falls below “overtemp. threshold minus hysteresis” => CAN driver remains disable. Event 3: temperature below “overtemp. threshold minus hysteresis” and TxD high to low transition => CAN driver enable. Event 4: temperature above “overtemp. threshold minus hysteresis” and TxD high to low transition => CAN driver remains disable.
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6.8.3.1 Single pulse detection
Figure 45. Single pulse wake-up pattern illustration
6.8.3.2 Multiple pulse detection
- event 3: a dominant level (event 3) longer than t3PWU.
would prevent system to enter in low-power mode. Figure 46. Multiple pulse wake-up pattern illustration
7 Serial peripheral interface
7.1 High level overview
7.1.1 SPI
- Bit 15 read/write
- Bit 14 Main or fail -safe register target
- bit 13 to 9 (A4 to A0) to select the register address. Bit 8 is a parity bit in write mode, Next bit (=0) in read mode.
- bit7 to 0 (D7 to D0): control bits MISO, Master IN Slave Out bits:
- bits 15 to 8 (S15 to S8) are device status bits
- bits 7 to 0(Do7 to Do0) are either extended device status bi ts, device internal control register content or device flags. Figure 47 is an overview of the SPI implementation.
7.1.2 Parity bit 8 calculation
15-9, 7-0 sequence (this is the whole 16-bits of the write command except bit 8). Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1 if the number of 1 is even.
7.1.3 Device status on MISO
Figure 47. SPI overview and sampled at falling edge. Msb first. for write commands, MOSI bits [15] = [1].
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read back to ensure its content (default setting or value previously written) are correct.
7.1.4 Register description
accesses is 3.5 µs, some SPI accesses to the main registers can be done in between (Figure 48).
7.2 Detail operation
Figure 48. MOSI / MISO SPI command organization Table 12. MOSI bits description
0 READ
0 Number of “1” (bit15:9 and bit 7:0) is odd
1 Number of “1” (bit15:9) and bit 7:0) is even
Table 13. MISO bits description
0 No WU event
1 WU event
0 No event
1 CAN event
0 No IO transition
1 IO transition
1 Event occurred
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7.2.1 Register address table
Table 14 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for main logic. Table 14. Register mapping of main logic Write description Table ref. Table 15. Register mapping of fail-safe logic Write description Table ref.
7.2.2 Secured SPI command
- Secure 3 = NOT(Bit5)
- Secure 2 = NOT(Bit4)
- Secure 1 = Bit7
- Secure 0 = Bit6 I N I T F S S M # 2 1 00101 #37(25h) Write during INIT phase then Read only Table 69 W D _ W i n d o w 1 00110 #38(26h) Write (No restriction) and Read Table 71 W D _ L F S R 1 00111 #39(27h) Write (No restriction) and Read Table 73 WD_answer 1 01000 #40(28h) Write (No restriction) and Read Table 75 F S _ O U T 1 01001 #41(29h) Write (No restriction) Table 77 RSTb request 1 01010 #42(2Ah) Write (No restriction) Table 79 I N I T W D 1 01011 #43(2Bh) Write during INIT phase then Read only Table 81 D i a g F S 1 1 01100 #44(2Ch) Read only Table 83 WD_Counter 1 01101 #45(2Dh) Read only Table 85 Diag_FS2 1 01110 #46(2Eh) Read only Table 87
Table 16. Secured SPI Table 15. Register mapping of fail-safe logic (continued) Write description Table ref.
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7.3 Detail of register mapping
7.3.1 Init VREG 1
7.3.2 Init Vreg 2
Table 17. INIT VREG1 register configuration Table 18. Description and configuration of the bits (default value in bold)
0 No Monitoring (IO_1 is used as analog & digital input)
1 Monitoring enabled (IO_1 can NOT be used for analog /digital input neither for WU from LPOFF)
Table 19. INIT VREG2 register configuration
7.3.3 Init CAN
Table 20. INIT VREG2. Description and configuration of the bits (default value in bold)
1 Tracking enabled
Table 21. INIT CAN register description
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7.3.4 INIT IO_WU1
Table 22. INIT CAN. Description and configuration of the bits (default value in bold)
1 Single dominant pulse
Table 23. INIT IO_WU1 register description Table 24. INIT IO_WU1. Description and configuration of the bits (default value in bold)
00 NO wake-up capability
01 Wake-up on rising edge only
10 Wake-up on falling edge only
11 Wake-up on any edge
7.3.5 INIT IO_WU2
0 INT NOT masked
Table 25. INIT IO_WU2 register description Table 26. INIT IO_WU2. Description and configuration of the bits (default value in bold) Table 24. INIT IO_WU1. Description and configuration of the bits (default value in bold) (continued)
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7.3.6 INIT INT
1 INT masked
Table 27. INIT INT register description Table 26. INIT IO_WU2. Description and configuration of the bits (default value in bold) (continued)
7.3.7 HW config
Table 28. INIT INT. Description and configuration of the bits (default value in bold)
0 All INT sources
1 All INT INHIBITED
1 CAN error bits changed INHIBITED
Table 29. HW config. register description
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7.3.8 WU source
Table 30. HW config. description and configuration of the bits (default value in bold)
0 Buck-Boost
1 Buck only
0 External PNP connected
1 Internal MOSFET
0 Normal operation
1 DEBUG mode selected
Table 31. WU source register description
7.3.9 IO input
Table 32. WU source. Description and configuration of the bits (default value in bold)
0 No Wake-up
1 WU event detected
Table 33. IO input register description
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7.3.10 Status VREG1
Table 34. IO input. Description and configuration of the bits
0 Low
Table 35. STATUS VREG1 register description
7.3.11 Status VREG2
Table 36. Status VREG1. Description and configuration of the bits (default value in bold)
0 No current limitation (I PRE_PK < IPRE_LIM)
1 Current limitation (I PRE_PK > IPRE_LIM)
0 No thermal warning (T J < TWARN_PRE)
1 Thermal warning (T J > TWARN_PRE)
Table 37. STATUS VREG2 register description Table 38. Status VREG2. Description and configuration of the bits (default value in bold)
0 No current limitation (I CORE_PK < ICORE_LIM)
1 Current limitation (I CORE_PK > ICORE_LIM)
0 No thermal warning (T J < TWARN_CORE)
1 Thermal warning (T J > TWARN_CORE)
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7.3.12 Diag VREG1
0 No thermal warning (T J < TWARN_CCA)
1 Thermal warning (T J > TWARN_CCA)
0 No current limitation (I CCA < ICCA_LIM)
1 Current limitation (I CCA > ICCA_LIM)
0 No current limitation (I AUX < IAUX_LIM)
1 Current limitation (I AUX > IAUX_LIM)
0 No current limitation (I CAN < ICAN_LIM)
1 Current limitation (I CAN > ICAN _LIM)
Table 39. DIAG VREG1 register description Table 40. Diag VREG1. Description and configuration of the bits (default value in bold)
1 TSD occurred (T J > TSD_PRE)
Table 38. Status VREG2. Description and configuration of the bits (default value in bold)(continued)
7.3.13 Diag VREG2
0 No overvoltage (V PRE < VPRE_OV)
1 Overvoltage detected (V PRE > VPRE_OV)
0 No undervoltage (VPRE > VPRE_UV)
1 Undervoltage detected (V PRE < VPRE_UV)
1 TSD occurred (T J > TSD_CORE)
0 No overvoltage (V CORE_FB < VCORE_FB_OV)
1 Overvoltage detected (V CORE_FB > VCORE_FB_OV)
0 No undervoltage (V CORE_FB > VCORE_FB_UV)
1 Undervoltage (V CORE_FB < VCORE_FB_UV)
Table 41. DIAG VREG2 register description Table 42. Diag VREG2. Description and configuration of the bits (default value in bold)
1 TSD occurred (T J > TSD_CAN)
0 No Overvoltage (V CAN < VCAN_OV)
1 Overvoltage detected (V CAN > VCAN_OV)
Table 40. Diag VREG1. Description and configuration of the bits (default value in bold) (continued)
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7.3.14 Diag VREG3
0 No undervoltage (V CAN > VCAN_UV)
1 Undervoltage detected (V CAN < VCAN_UV)
0 No TSD (T J < TSD_AUX)
1 TSD occurred (T J > TSD_AUX)
0 No overvoltage (V AUX < VAUX_OV)
1 Overvoltage detected (V AUX > VAUX_OV)
0 No undervoltage (V AUX > VAUX_UV)
1 Undervoltage detected (V AUX < VAUX_UV)
Table 43. DIAG VREG3 register description Table 44. Diag VREG3. Description and configuration of the bits (default value in bold)
1 TSD occurred (T J > TSD_CCA)
Table 42. Diag VREG2. Description and configuration of the bits (default value in bold) (continued)
7.3.15 Diag CAN1
0 No overvoltage (V CCA < VCCA_OV)
1 Overvoltage detected (V CCA > VCCA_OV)
0 No undervoltage (V CCA > VCCA_UV)
1 Undervoltage detected (V CCA < VCCA_UV)
Table 45. DIAG CAN1 register description Table 46. Diag CAN1. Description and configuration of the bits (default value in bold)
0 No failure
1 Failure detected
Table 44. Diag VREG3. Description and configuration of the bits (default value in bold) (continued)
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7.3.16 Diag CAN
7.3.17 Diag SPI
Table 47. DIAG CAN register description Table 48. Diag CAN. Description and configuration of the bits (default value in bold) Table 49. DIAG SPI register description Table 46. Diag CAN1. Description and configuration of the bits (default value in bold) (continued)
7.3.18 Mode
Table 50. Diag SPI. Description and configuration of the bits (default value in blue)
0 No error
1 Error detected in the secured bits
1 Wrong number of clock cycles (<16 or > 16)
1 SPI violation
0 Parity bit OK
1 Parity bit error
Table 51. MODE register description
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7.3.19 Vreg mode
Table 52. MODE. Description and configuration of the bits (default value in bold)
0 Not in INIT mode
1 INIT MODE
0 Not in Normal mode
1 Normal mode
0 No Request
1 Request for an INT pulse
Table 53. VREG MODE register description
7.3.20 IO_OUT-AMUX
Table 54. VREG MODE. Description and configuration of the bits (default value in bold)
0 DISABLED
1 ENABLED
Table 55. IO_OUT-AMUX register description
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7.3.21 CAN mode
Table 56. IO_OUT-AMUX. Description and configuration of the bits (default value in bold)
0 High-impedance (IO_4 configured as input)
1 ENABLED (IO_4 configured as output gate driver)
0 High-impedance (IO_5 configured as input)
1 ENABLED (IO_5 configured as output gate driver)
000 Vref
111 Die Temperature Sensor
Table 57. CAN MODE register description
7.3.22 Can_Mode_2
Table 58. CAN MODE. Description and configuration of the bits (default value in bold)
00 Sleep / NO wake-up capability
01 LISTEN ONLY
10 Sleep / Wake-up capability
11 Normal operation mode
0 NO auto disable
1 Reset CAN_mode from “11” to “01” on CAN over temp or TXD dominant or RXD recessive event
1 Wake-up detected
- CAN mode is automatically configured to “sleep + wake-up c apability[10]” if CAN mode was different than “sleep + no wake-up capability [00]”
before the device enters in LPOFF. After LPOFF, the initial CAN mode prior to enter LPOFF is restored. Table 59. CAN_MODE_2 register description
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7.3.23 INIT SUPERVISOR1
Table 60. CAN_MODE_2. Description and configuration of the bits (default value in bold) 1O N . V CAN OV flag is under monitoring. In case of OV the VCAN regulator is switched OFF. Table 61. INIT SUPERVISOR1 register description Table 62. INIT SUPERVISOR1. Description and configuration of the bits (default value in bold) Description V CORE safety input.
00 No effect of V CORE_FB_OV and VCORE_FB_UV on RSTb and FSxx
11 Both V CORE_FB_OV and VCORE_FB_UV DO HAVE an impact on RSTb and FSxx
Description V CCA safety input.
00 No effect of V CCA_OV and VCCA_UV on RSTb and FSxx
11 Both V CCA_OV and VCCA_UV DO HAVE an impact on RSTb and FSxx
7.3.24 INIT SUPERVISOR2
1 Wrong number of clock cycles (<16 or >16)
Table 63. INIT SUPERVISOR2 register description Table 62. INIT SUPERVISOR1. Description and configuration of the bits (default value in bold) (continued)
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Table 64. INIT SUPERVISOR2. Description and configuration of the bits (default value in bold) Description V AUX safety input.
00 No effect of V AUX_OV and VAUX_UV on RSTb and FSxx
11 Both V AUX_OV and VAUX_UV DO HAVE an impact on RSTb and FSxx
0 ENABLED
1 DISABLED
Description Secured SPI communication c heck, concerns fail-safe logic only.
7.3.25 INIT SUPERVISOR3
Table 65. INIT SUPERVISOR3 register description Table 66. INIT SUPERVISOR3. Description and configuration of the bits (default value in bold)
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7.3.26 Init FSSM1
Table 67. INIT FSSM1 register description Table 68. INIT FSSM1. Description and configuration of the bits (default value in bold)
1 SAFETY CRITICAL
1 SAFETY CRITICAL (External resi stor bridge monitoring active)
Table 66. INIT SUPERVISOR3. Description and configuration of the bits (default value in bold) (continued)
Table 68. INIT FSSM1. Description and configuration of the bits (default value in bold) (continued)
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7.3.27 Init FSSM2
Table 69. INIT FSSM2 register description Table 70. INIT FSSM2. Description and configuration of the bits (default value in bold)
0 NOT SAFETY
0 Fccu_eaout_1:0 active HIGH
1 Fccu_eaout_1:0 active LOW
7.3.28 WD window
Table 71. WD WINDOW register description Table 70. INIT FSSM2. Description and configuration of the bits (default value in bold) (continued)
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Table 72. WD Window. Description and configuration of the bits (default value in bold)
0000 DISABLE
main and fail-safe logics. Other errors flagged by the SPI_CLK bit.
7.3.29 WD_LFSR
7.3.30 WD answer
Table 73. WD LFSR register description Table 74. WD LFSR. Description and configuration of the bits (default value in bold)
- Value Bit7:Bit0: 1111 1111 is prohibited.
- During a write command, MISO reports the previous register content.
Table 75. WD answer register description
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report the latest information. Table 76. WD answer. Description and configuration of the bits (default value in bold)
0 No Reset
1 Reset occurred
1 Fail safe event occurred / Also default state at power-up after LPOFF as FS0b is asserted low
0 WD refresh OK
1 WRONG WD refresh
1 Error detected
1 ECC done
7.3.31 Fail-safe out (FS_out)
7.3.32 RSTB request
Table 77. Fail-safe out register description Table 78. Fail-safe out. Description and configuration of the bits (default value in bold) Table 79. RSTB request register description Table 80. RSTB request. Description and configuration of the bits (Default value in bold)
1 Request a RSTb low pulse
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7.3.33 INIT_WD
Table 81. INIT WD register description Table 82. INIT WD. Description and configuration of the bits (default value in bold)
7.3.34 Diag FS1
main and fail-safe logics. Other errors flagged by the SPI_CLK bit. Table 83. DIAG FS1 register description Table 84. Diag FS1. Description and configuration of the bits (default value in bold)
1 Short-circuit HIGH
0 No external RSTb
1 External RSTb
00 No Failure
01 Short-circuit LOW / open load
Table 82. INIT WD. Description and configuration of the bits (default value in bold) (continued)
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7.3.35 WD counter
7.3.36 Diag FS2
Table 85. WD counter register description Table 86. WD counter. Description and configuration of the bits (default value in bold) Table 87. DIAG FS2 register description Table 88. Diag FS2. Description and configuration of the bits (default value in bold)
Table 88. Diag FS2. Description and configuration of the bits (default value in bold) (continued)
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8 List of interruptions and description
through the SPI during INIT phase. It is possible to mask some Interruption source (see Detail of register mapping). Table 89. Interruptions list ILIM_CCA_OFF Current limitation maximum duration expiration. Only used when external PNP connected. ILIM_AUX_OFF Current limitation maximum duration expiration. Only used when external PNP connected. TSDCAN Temperature shutdown on the pass transistor. Auto restart when TJ < (TSDCAN - TSDCAN_HYST).
Table 89. Interruptions list (continued)
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9 Typical applications
Figure 49. FS6407/FS6408 simplified application schematic with non-inverting buck-boost configuration Figure 50. VAUX/VCCA connection
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10 Packaging
10.1 Package mechanical dimensions
perform a keyword search for the drawing’s document number. Table 90. Package mechanical dimensions
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11 References
The following are URLs where you can obtain information on related NXP products and application solutions Support pages Description URL AN4766 MC33907_08 System Basis Chip: Recommendations for PCB layout and external components https://www.nxp.com/webapp/Download?colCode=AN4766 AN4661 Designing the VCORE Compensation Network For The MC33907/MC33908 System Basis Chips http://www.nxp.com/files/analog/doc/app_note/AN4661.pdf AN4442 Integrating the MPC5643L and MC33907/08 for Safety Applications http://www.nxp.com/files/analog/doc/app_note/AN4442.pdf AN4388 Quad Flat Package (QFP) http://www.nxp.com/files/analog/doc/app_note/AN4388.pdf AN4843 Low-power Wireless Charging Using the NXP WCT1001A Controller http://www.nxp.com/files/microcontrollers/doc/app_note/AN4843.pdf AN5099 Integrating the MPC5744P and MC33907/08 for Safety Applications http://www.nxp.com/files/microcontrollers/doc/app_note/AN5099.pdf MC33907- MC33908PDTCALC MC33907_8 Power Dissipation Tool http://www.nxp.com/files/software_development_tools/calculators/ MC33907-MC33908-PDT-CALC.xlsx V CORE Compensation Network Simulation Tool Upon demand MC33907_8SMUG MC33907_8NAE, MC33907/8NAE Safety Manual https://www.nxp.com/webapp/Download?colCode=MC33907NL- 33908NLSMUG FMEDA MC33907_8 FMEDA Upon demand KIT34FS6407EVB Evaluation Board http://www.nxp.com/products/analog-power-management/transceivers/can- physical-interfaces/evaluation-board-mc34fs6407-safe-dc-dc-up-to-800- ma:KIT34FS6407EVB KIT34FS6408EVB Evaluation Board http://www.nxp.com/products/analog-power-management/transceivers/can- physical-interfaces/evaluation-board-mc34fs6407-safe-dc-dc-up-to-800- ma:KIT34FS6408EVB KIT33908MBEVBE Evaluation Mother Board (EVM) http://www.nxp.com/webapp/sps/site/ prod_summary.jsp?code=KIT33908MBEVBE KITMPC5643DBEVM Evaluation Daught er Board (Qorivva MPC5643L) http://www.nxp.com/webapp/sps/site/ prod_summary.jsp?code=KITMPC5643DBEVM KITMPC5744DBEVM Evaluation daughter board - MPC5744P, 32-bit Microcontroller http://www.nxp.com/products/power-architecture-processors/mpc5xxx- 5xxx-32-bit-mcus/mpc57xx-mcus/evaluation-daughter-board- NXP- mpc5744p-32-bit-microcontroller:KITMPC5744DBEVM MC34FS6407 Product Summary Page http://www.nxp.com/products/analog-power-management/transceivers/can- physical-interfaces/safe-sbc-with-buck-and-boost-dc-dc-up-to-800-ma-on- vcore:MC34FS6407 MC34FS6408 Product Summary Page http://www.nxp.com/products/analog-power-management/transceivers/can- physical-interfaces/safe-sbc-with-buck-and-boost-dc-dc-up-to-800-ma-on- vcore:MC34FS6408 Analog Home Page http://www.nxp.com/analog
110 NXP Semiconductors
Revision Date Description of changes 1.0 10/2014 • Initial release 2.0 3/2015 • Overall description improvement 3.0
- Changed PC parts to MC in the Orderable Part Variations table
- Changed document classification to Advance Information
- Changed max. ambient temperature to 125 °C
- Updated the min. value for t 3PTO1 in Table 5
- Updated the min. value for t 3PTO2 in Table 5
- Updated the min. and typ. value for f SW_PRE in Table 5
- Updated the max. value for t PRE_UV_4p3 in Table 5
- Updated the min. and max. value for t PRE_TSD in Table 5
- Updated the values for f SW_CORE in Table 5
- Updated the min. and max. value for t CORE_TSD in Table 5
- Updated the min. and max. value for t CCA_TSD in Table 5
- Updated the min. and max. value for t AUX_TSD in Table 5
- Updated the max. value for t CAN_TSD in Table 5
- Updated links in References table 9/2015 • Updated Table 56 7/2016 • Updated to NXP document form and style
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