FS6377-01G-XTD

FS6377 ONSEMI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 24

Technical content

©2008 SCILLC. All rights reserved. Publication Order Number: May 2008 – Rev. 4 FS6377/D FS6377 Programmable 3-PLL Clock Generator IC

1.0 Key Features

• Three on-chip PLLs with programmable reference and feedback dividers
• Four independently programmable muxes and post dividers
• I 2C™-bus serial interface
• Programmable power-down of all PLLs and output clock drivers
• One PLL and two mux/post-divider combinations can be modified by SEL_CD input
• Tristate outputs for board testing
• 5V to 3.3V operation
• Accepts 5MHz to 27MHz crystal resonators
• Commercial and industrial temperature ranges offered

2.0 General Description

The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three I2C-programmable phase locked loops (PLLs) feeding four programmable muxes and post dividers provide a high degree of flexibility. Figure 1: Pin Configuration

Figure 2: Block Diagram Table 1: Pin Descriptions Pin Type Name Description 1 DI U O SDA Serial interface data input/output 2 DI U SEL_CD Selects one of two PLL C, mux D/C and post divider C/D combinations 3 DI U PD Power-down input

4 P VSS Ground

5 AI XIN Crystal oscillator input

6 AO XOUT Crystal oscillator output

U OE Output enable input 8 P VDD Power supply (5V to 3.3V) 9 DI U ADDR Address select

10 DO CLK_D D clock output

11 P VSS Ground

12 DO CLK_C C clock output

13 DO CLK_B B clock output

14 P VDD Power supply (5V to 3.3V)

15 DO CLK_A A clock output

U SCL Serial interface clock output Key: AI: Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-up; DID = Input with Internal Pull-down; DIO = Digital Input/Output; DI-3 = Three-level Digital Input; DO = Digital Output; P = Power/Ground; # = Active Low Pin Rev. 4 | Page 2 of 24 | www.onsemi.com

3.0 Functional Block Description

3.1 Phase Locked Loops (PLLs)

Each of the three on-chip PLLs is a st andard phase- and frequency-locked loop archit ecture that multiplies a reference frequenc y to a desired frequency by a ratio of integers. This frequency multiplication is exact. As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), and a feedback divider. During operation, the reference frequency (f REF), generated by the on-board crystal oscillator, is first reduced by the reference divider. The divider value is called the "modulus," and is denoted as NR for the reference divider. The divided reference is then fed into the PFD. The PFD controls the frequency of the VCO (f VCO) through the charge pump and loop filter. T he VCO provides a high speed, low noise, continuously variable frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback div ider (the modulus is denoted by NF) to close the loop. The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearin g at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is: Figure 3: PLL Diagram 3.1.1. Reference Divider The reference divider is designed for low phase jitter. The divi der accepts the output of the re ference oscillator and provides a divided- down frequency to the PFD. The reference divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h. 3.1.2. Feedback Divider The feedback divider is based on a dual-modulus prescaler techni que. The technique allows the same granularity as a fully programmable feedback divider, while still allowing the programmabl e portion to operate at low speed. A high-speed pre-divider (also called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overal l power consumption of the divider. Rev. 4 | Page 3 of 24 | www.onsemi.com

For example, a fixed divide-by-eight could be used in the feed back divider. Unfortunately, a divide-by-eight would limit the ef fective modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to achieve a desired input- frequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large. A large feedback modulus means that the divided VCO frequency is relatively low, requiring a wide loop bandwidth to permit the low frequencies. A narrow loop bandwidth tuned to high frequencies is essential to minimizing jitter; therefore, divider moduli sho uld always be as small as possible. To understand the operation, refer to Figure 4. The M-counter (with a modulus always equal to M) is cascaded with the dual-modulus prescaler. The A-counter controls the modul us of the prescaler. If the value programm ed into the A-counter is A, the prescaler will be set to divide by N+1 for A prescaler outputs. Thereafter, the pres caler divides by N until the M-counter output resets the A-co unter, and the cycle begins again. Note that N=8 and A and M are binary numbers. Suppose that the A-counter is programmed to zero. The modulus of the prescaler will al ways be fixed at N; and the entire modulu s of the feedback divider becomes MxN. Next, suppose that the A-counter is programmed to a one. This causes the prescaler to switch to a divide-by-N+1 for its first d ivide cycle and then revert to a divide-by-N. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycl e of the feedback divider. The overall modulus is now seen to be equal to MxN+1. This example can be extended to show that the feedback divider modulus is equal to MxN+A, where A<M. Figure 4: Feedback Divider 3.1.3. Feedback Divider Programming For proper operation of the feedback divider , the A-counter must be programmed only for values that are less than or equal to t he M- counter. Therefore, not all divider moduli below 56 are available for use. The selection of divider values is listed in Table 2. Above a modulus of 56, the feedback divider can be programmed to any value up to 2047. Table 2: Feedback Divider Modulus Under 56 M-Counter: FBKDIV[10:3] A-Counter: FBKDIV[2:0] 000 001 010 011 100 101 110 111 00000001 8 9 00000010 16 17 18 00000011 24 25 26 27 00000100 32 33 34 35 36 00000101 40 41 42 43 44 45 00000110 48 49 50 51 52 53 54 00000111 56 57 58 59 60 61 62 63 Feedback Divider Modulus Rev. 4 | Page 4 of 24 | www.onsemi.com

3.2 Post Divider Muxes

As shown in Figure 2, an input mux in front of each post divider stage can select from any one of the PLL frequencies or the reference frequency. The frequency selection is done via the I2C-bus. The input frequency on two of the four muxes (mux C and D in Figure 2) can be changed without reprogramming by a logic-level input on the SEL_CD pin.

3.3 Post Dividers

The post divider performs several useful functions. First, it allo ws the VCO to be operated in a narrower range of speeds compa red to the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to where NF, NR and NP are the feedback, reference and post divider moduli respectively, and f CLK and fREF are the output and reference oscillator frequencies. The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly. The modulus on two of the four post dividers muxes (post dividers C and D in Figure 2) can be altered without reprogramming by a logic level on the SEL_CD pin.

4.0 Device Operation

The FS6377 powers up with all internal registers cleared to zero, delivering the crystal frequency to all outputs. For operation to occur, the registers must be loaded in a most sign ificant-bit (MSB) to least-significant-bit (LSB) order. The register mapping of the FS6377 is shown in Table 3, and I 2C-bus programming information is detailed in Section 5.0. Control of the reference, feedback and post dividers is detailed in Table 5. Selection of these dividers directly controls how fast the VCO will run. The maximum VCO speed is noted in Table 13.

4.1 SEL_CD Input

The SEL_CD pin provides a way to alter the operation of PLL C, muxes C and D and post dividers C and D without having to reprogram the device. A logic-low on the SEL_CD pin sele cts the control bits with a "C1" or "D1" notation, per Table 3. A logic-high on t he SEL_CD pin selects the control bits with "C2" or "D2" notation, per Table 3. Note that changing between two running frequencies using the SEL_CD pin may produce glitches in the output, especially if the p ost- divider(s) is/are altered.

4.2 Power-Down and Output Enable

A logic-high on the PD pin powers down only those portions of the FS6377 which have their respective power-down control bits enabled. Note that the PD pin has an internal pull-up. When a post divider is powered down, the associated output driver is forced low. When all PLLs and post dividers are powered do wn the crystal oscillator is also powered down. The XIN pin is forced low, and the XOUT pin is pulled high. A logic-low on the OE pin tristates all output clocks. Note that this pin has an internal pull-up. Rev. 4 | Page 5 of 24 | www.onsemi.com

4.3 Oscillator Overdrive

For applications where an external reference clock is provided ( and the crystal oscillator is not required), the reference clock should be connected to XOUT and XIN should be left unconnected (float). For best results, make sure the reference clock signal is as jitter-free as possible, can drive a 40pF load with fast rise and fall times and can swing rail-to-rail. If the reference clock is not a rail-to-rail signal, the reference must be AC coupled to XOUT through a 0.01µF or 0.1µF capacit or. A minimum 1V peak-to-peak signal is required to drive the internal differential oscillator buffer.

5.0 I2C-bus Control Interface

This device is a read/write slav e device meeting all Philips I 2C-bus specifications except a "general call." The bus has to be controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while t he device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. I 2C-bus logic levels noted herein are based on a percentage of the power supply (V DD). A logic-one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS).

5.1 Bus Conditions

Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition. The following bus conditions are defined by the I2C-bus protocol. 5.1.1. Not Busy Both the data (SDA) and clock (SLC) lines remain high to indicate the bus is not busy. 5.1.2. START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device mu st be preceded by a START condition. 5.1.3. STOP Data Transfer A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition. 5.1.4. Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pul se per data bit. Each data transfer is initiated by a START condition and termi nated with a STOP condition. T he number of data bytes transferred between START and STOP conditions is determined by the master de vice, and can continue indefinitely. However, data that is overwritten to the device after the first sixteen bytes will overfl ow into the first register, th en the second, and so on, in a first-in, first- overwritten fashion. Rev. 4 | Page 6 of 24 | www.onsemi.com

5.1.5. Acknowledge When addressed, the receiving device is required to generate an a cknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. The master must signal an end of data to the slave by not generat ing an acknowledge bit on the last byte that has been read (cl ocked) out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.

5.2 I2C-bus Operation

All programmable registers can be accessed randomly or sequentia lly via this bi-directional two wire digital interface. The dev ice accepts the following I2C-bus commands. 5.2.1. Slave Address After generating a START condition, the bus ma ster broadcasts a seven-bit slave address followed by a R/W bit. The address of t he device is: A6 A5 A4 A3 A2 A1 A0 1 0 1 1 X 0 0 where X is controlled by the logic level at the ADDR pin. The variable ADDR bit allows two different devices to exist on the same bus. Note that every device on an I 2C-bus must have a unique address to avoid bus conflicts. The default address sets A2 to one via the pull-up on the ADDR pin. 5.2.2. Random Register Write Procedure Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register ad dress is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored. 5.2.3. Random Register Read Procedure Random read operations allow the master to directly read from any register. To per form a read procedure, the R/W bit that is transmitted after the seven-bit address is a l ogic-low, as in the register write procedur e. This indicates to the addressed sla ve device that a register address will follow after the slave device acknowledges its device address. The register address is then writte n into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. T he slave will acknowledge the device address, and then transmits the eight-bit word. The master does not acknowledge the transfer but does generate a STOP condition. 5.2.4. Sequential Register Write Procedure Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremen ted after each write. This procedure is more efficient than the random register write if several registers must be written. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicate s to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address Rev. 4 | Page 7 of 24 | www.onsemi.com

is written into the slave's address pointer. Following an acknowled ge by the slave, the master is allowed to write up to sixtee n bytes of data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur. Registers are therefore updated at different times during a sequential register write. 5.2.5. Sequential Register Read Procedure Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure is more efficient than the random register read if several registers must be read. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave devic e that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. T he slave will acknowledge the device address, and then transmits all 16 bytes of data starting with the initia l addressed register. The register address pointe r will overflow if the initial register addres s is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition. Rev. 4 | Page 8 of 24 | www.onsemi.com

6.0 Programming Information

Table 3: Register Map Address BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Byte 15 MUX_D2[1:0] (selected via SEL_CD = 1 MUX_C2[1:0] (selected via SEL_CD = 1) PDPOST_D PDPOST_C PDPOST_B PDPOST_A Byte 14 POST_D2[3:0] (selected via SEL_CD = 1) POST_C2[3:0] (selected via SEL_CD = 1) Byte 13 POST_D1[3:0] (selected via SEL_CD = 0) POST_C1[3:0] (selected via SEL_CD = 0) Byte 12 POST_B[3:0] POST_A[3:0] Byte 11 MUX_D1[1:0] (selected via SEL_CD = 0) Reserved (0) LFTC_C2 (SEL_CD = 1) CP_C2 (SEL_CD = 1) FBKDIV_D2[10:8] M-Counter (selected via SEL_CD pin = 1) Byte 10 FBKDIV_C2[7:3] M-Counter (selected via SEL_CD pin = 1) FBKDIV_C2[2:0] A-Counter (selected via SEL_CD pin = 1) Byte 9 REFDIV_C2[7:0] (selected via SEL_CD pin = 1) Byte 8 MUX_C1[1:0] (selected via SEL_CD = 0) PDPLL_C LFTC_C1 (SEL_CD = 0) CP_C1 (SEL_CD = 0) FBKDIV_c1[10:8] M-Counter (selected via SEL_CD = 0) Byte 7 FBKDIV_C1[7:3] M-Counter (selected via SEL_CD = 0) FBKDIV_C1[2:0] A-Counter (selected via SEL_CD = 1) Byte 6 REFDIV_C1[7:0] (selected via SEL_CD = 0) Byte 5 MUX_B[1:0] PDPLL_B LFTC_B CP_B FBKDIV_B[10:8] M-Counter Byte 4 FBKDIV_B[7:3] M-Counter FBKDIV_B[2:0] A-Counter Byte 3 REFDIV_B[7:0] Byte 2 MUX_A[1:0] PDPLL_A LFTC_A CP_A FBKDIV_A[10:8] M-Counter Byte 1 FBKDIV_A[7:3] M-Counter FBKDIV_A[2:0] A-Counter Byte 0 REFDIV_A[7:0] Note: All register bits are cleared to zero on power-up.

6.1 Control Bit Assignment

If any PLL control bit is altered during device operation, incl uding those bits controlling the reference and feedback dividers, the output frequency will slew smoothly (in a glitch-free manner) to the new frequency. The slew rate is related to the programmed loop fi lter time constant. However, any programming changes to any mux or post divider control bits will cause a glitch on an operating clock output. Rev. 4 | Page 10 of 24 | www.onsemi.com

6.2 Power-Down

All power-down functions are controlled by enable bits. The bits select which portions of the device to power-down when the PD input is asserted. Table 4: Power-Down Bits Name Description Power-Down PLL A PDPLL_A (Bit 21) Bit = 0 Bit = 1 Power on Power off Power-Down PLL B PDLL_B (Bit 45) Bit = 0 Bit = 1 Power on Power off Power-Down PLL C PDLL_C (Bit 69) Bit = 0 Bit = 1 Power on Power off Reserved (0) (Bit 69) Set these reserved bits to zero (0) Power-Down POST Divider A PDPOSTA (Bit 120) Bit = 0 Bit = 1 Power on Power off Power-Down POST Divider B PDPOSTB (Bit 121) Bit = 0 Bit = 1 Power on Power off Power-Down POST Divider C PDPOSTC (Bit 122) Bit = 0 Bit = 1 Power on Power off Power-Down POST Divider D PDPOSTD (Bit 123) Bit = 0 Bit = 1 Power on Power off Table 5: Divider Control Bits Name Description REFDIV_A[7:0] (Bits 7-0) Reference Divider A (NR) REFDIV_B[7:0] (Bits 31-24) Reference Divider B (NR) REFDIV_C1[7:0] (Bits 55-48) Reference Divider C1 (NR) selected when the SEL_CD pin = 0 REFDIV_C2[7:0] (Bits 79-72) Reference Divider C2 (NR) selected when the SEL_CD pin = 1 Feedback Divider A (NF) FBKDIV_A[10:0] (Bits 18-8) FBKDIV_A[2:0] FBKDIV_A[10:3] A-Counter value M-Counter value Feedback Divider B (NF) FBKDIV_B[10:0] (Bits 42-32) FBKDIV_B[2:0] FBKDIV_B[10:3] A-Counter value M-Counter value Feedback Divider C1 (NF) selected when the SEL_CD pin = 0 FBKDIV_C1[10:0] (Bits 66-56) FBKDIV_C1[2:0] FBKDIV_C1[10:3] A-Counter value M-Counter value Feedback Divider C2 (NF) selected when the SEL_CD pin = 1 FBKDIV_C2[10:0] (Bits 90-80) FBKDIV_C2[2:0] FBKDIV_C2[10:3] A-Counter value M-Counter value Rev. 4 | Page 11 of 24 | www.onsemi.com

Table 6: Divider Control Bits Name Description POST_A[3:0] (Bits 99-96) POST divider A (see Table 7) POST_B[3:0] (Bits 103-100) POST divider B (see Table 7) POST_C1[3:0] (Bits 107-104) POST divider C1 (see Table 7) selected when the SEL_CD pin = 0 POST_C2[3:0] (Bits 115-112) POST divider C2 (see Table 7) selected when the SEL_CD pin = 1 POST_D1[3:0] (Bits 111-108) POST divider D1 (see Table 7) selected when the SEL_CD pin = 0 POST_D2[3:0] (Bits 119-116) POST divider D2 (see Table 7) selected when the SEL_CD pin = 1 Table 7: Post Divider Modulus BIT [3] BIT [2] BIT [1] BIT [0] Divide By 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 8 0 1 1 1 9 1 0 0 0 10 1 0 0 1 12 1 0 1 0 15 1 0 1 1 16 1 1 0 0 18 1 1 0 1 20 1 1 1 0 25 1 1 1 1 50 Rev. 4 | Page 12 of 24 | www.onsemi.com

Table 8: PLL Tuning Bits Name Description Loop Filter Time Constant A LFTC_A (Bit 20) Bit = 0 Bit = 1 Short time constant: 7µs Long time constant: 20µs Loop Filter Time Constant B selected when the SEL_CD pin = 0 LFTC_B (Bit 44) Bit = 0 Bit = 1 Short time constant: 7µs Long time constant: 20µs Loop Filter Time Constant C1 selected when the SEL_CD pin = 1 LFTC_C1 (Bit 68) Bit = 0 Bit = 1 Short time constant: 7µs Long time constant: 20µs Loop Filter Time Constant C2 LFTC_C2 (Bit 92) Bit = 0 Bit = 1 Short time constant: 7µs Long time constant: 20µs Charge Pump A CP_A (Bit 19) Bit = 0 Bit = 1 Current = 2µA Current = 10µA Charge Pump B CP_B (Bit 43) Bit = 0 Bit = 1 Current = 2µA Current = 10µA Charge Pump C1 selected when the SEL_CD pin = 0 CP_C1 (Bit 67) Bit = 0 Bit = 1 Current = 2µA Current = 10µA Charge Pump C2 selected when the SEL_CD pin = 1 CP_C2 (Bit 91) Bit = 0 Bit = 1 Current = 2µA Current = 10µA Rev. 4 | Page 13 of 24 | www.onsemi.com

Table 9: Mux Select Bits Name Description Mux A Frequency Select Bit 23 Bit 22 0 0 Reference frequency 0 1 PLL A frequency 1 0 PLL B frequency MUX_A[1:0] (Bits 23-22) 1 1 PLL C frequency Mux B Frequency Select Bit 47 Bit 46 0 0 Reference frequency 0 1 PLL A frequency 1 0 PLL B frequency MUX_B[1:0] (Bits 47-46) 1 1 PLL C frequency Mux C1 Frequency Select selected when the SEL_CD pin = 0 Bit 71 Bit 70 0 0 Reference frequency 0 1 PLL A frequency 1 0 PLL B frequency MUX_C1[1:0] (Bits 71-70) 1 1 PLL C frequency Mux C2 Frequency Select selected when the SEL_CD pin = 1 Bit 125 Bit 124 0 0 Reference frequency 0 1 PLL A frequency 1 0 PLL B frequency MUX_C2[1:0] (Bits 125- 124) 1 1 PLL C frequency Mux D1 Frequency Select selected when the SEL_CD pin = 0 Bit 95 Bit 94 0 0 Reference frequency 0 1 PLL A frequency 1 0 PLL B frequency MUX_D1[1:0] (Bits 95-94) 1 1 PLL C frequency Mux D2 Frequency Select selected when the SEL_CD pin = 1 Bit 127 Bit 126 0 0 Reference frequency 0 1 PLL A frequency 1 0 PLL B frequency MUX_D2[1:0] (Bits 127- 126) 1 1 PLL C frequency Rev. 4 | Page 14 of 24 | www.onsemi.com

7.0 Electrical Specifications

Table 10: Absolute Maximum Ratings Parameter Symbol Min. Max. Units Supply voltage, dc (VSS = ground) VDD V SS – 0.5 7 V Input voltage, dc V1 VSS – 0.5 VDD + 0.5 V Output voltage, dc VO V SS – 0.5 VDD + 0.5 V Input clamp current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output clamp current, dc (VI < 0 or VI > VDD) I OK -50 50 mA Storage temperature range (non-condensing) TS -65 150 °C Ambient temperature range, under bias TA -55 125 °C Junction temperature TJ 150 °C Re-flow solder profile Per IPC/JEDEC J-STD-020B Input static discharge voltage protection (MIL-STD 883E, Method 3015.7) 2 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the devic e. These conditions represent a stress rating only, and functional operation of the device of these or any other conditions above the operational limits not ed in this specification is not implie d. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability. CAUTION: ELETROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 11: Operating Conditions Parameter Symbol Conditions/Descriptions Min. Typ. Max. Units Supply voltage VDD 5V ± 10% 3.3V ± 10% 4.5 3.3 5.5 3.6 V Ambient operating temperature range TA Commercial Industrial -40 85 °C Crystal resonator frequency fXIN 5 27 MHz Crystal resonator load capacitance CXL Parallel resonant, AT cut 18 pF Serial data transfer rate Standard mode 10 100 kb/s Output driver load capacitance CL 15 pF Table 12: DC Electrical Specifications Parameter Symbol Conditions/Descriptions Min. Typ. Max. Units Overall Supply current, dynamic, with load outputs IDD VDD = 5.5V, f CLK = 50MHz, C L = 15pF See Figure 10 for more information 43 mA Supply current, static IDDL VDD = 5.5V, device powered down 0.3 mA Power-Down, Output Enable Pins (PD, OE) High-level input voltage VIH VDD = 5.5V VDD = 3.6V 3.85 2.52 V DD +0.3 VDD +0.3 V Low-level input voltage VIL VDD = 5.5V VDD = 3.6V VSS - 0.3 VSS - 0.3 1.65 1.08 V Hysteresis voltage Vhys VDD = 5.5V VDD = 3.6V 2.20 1.44 V High-level input current IIH -1 1 µA Low-level input current (pull-up) IIL V IL = 0V -20 -36 -80 µA Serial Interface I/O (SCL, SDA) High-level input voltage VIH VDD = 5.5V VDD = 3.6V 3.85 2.52 V DD +0.3 VDD +0.3 V Low-level input voltage VIL VDD = 5.5V VDD = 3.6V VSS - 0.3 VSS - 0.3 1.65 1.08 V Hysteresis voltage Vhys VDD = 5.5V VDD = 3.6V 2.20 1.44 V High-level input current IIH -1 1 µA Low-level input current (pull-up) IIL V IL = 0V -20 -36 -80 µA Low-level output sink current (SDA) IOL VOL = 0.4V, VDD = 5.5V 26 mA Rev. 4 | Page 15 of 24 | www.onsemi.com

Table 12: DC Electrical Specifications (continued) Mode and Frequency Select Inputs (ADDR, SEL_CD) High-level input voltage VIH VDD = 5.5V VDD = 3.6V 2.4 2.0 V DD +0.3 VDD +0.3 V Low-level input voltage VIL VDD = 5.5V VDD = 3.6V VSS - 0.3 VSS - 0.3 0.8 0.8 V High-level input current IIH -1 1 µA Low-level input current (pull-up) IIL -20 -36 -80 µA Crystal Oscillator Feedback (XIN) Threshold bias voltage VTH VDD = 5.5V VDD = 3.6V 2.9 1.7 V High-level input current IIH VDD = 5.5V VDD = 5.5V, oscillator powered down µA mA Low-level input current IIL V DD = 5.5V -25 -54 -75 µA Crystal loading capacitance* CL(xtal) As seen by an external crystal connected to XIN and XOUT 18 pF Input loading capacitance* CL(XIN) As seen by an external clock driver on XOUT; XIN unconnected 36 pF Crystal Oscillator Driver (XOUT) High-level output source current IOH V DD = V(XIN) = 5.5V, VO = 0V 10 21 30 mA Low-level output sink current IOL VDD = 5.5V, V(XIN) = 0V, VO = 5.5V -10 -21 -30 mA Clock Outputs (CLK_A, CLK_B, CLK_C, CLK_D) High-level output source current IOH V O = 2.4V -125 mA Low-level output sink current IOL VO = 0.4V 23 mA Output impedance ZOH ZOL VO = 0.5VDD; output driving high VO = 0.5VDD; output driving low Ω Tristate output current IZ -10 10 µA Short circuit source current* ISCH VDD = 5.5V, V O = 0V; shorted for 30s, max. -150 mA Short circuit sink current* ISCL VDD = VO = 5.5V; shorted for 30s, max. 123 mA Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not currently production tested on any specific limits. Min. and max. characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device. Low Drive Current (mA) High Drive Current (mA) Voltage (V) Min. Typ. Max. Voltage (V) Min. Typ. Max. 0 0 0 0 0 -87 -112 -150 0.2 9 11 12 0.5 -85 -110 -147 0.5 22 25 29 1 -83 -108 -144 0.7 29 34 40 1.5 -80 -104 -139 1 39 46 55 2 -74 -97 -131 1.2 44 52 64 2.5 -65 -88 -121 1.5 51 61 76 2.7 -61 -84 -116 1.7 55 66 83 3 -53 -77 -108 2 60 73 92 3.2 -48 -71 -102 2.2 62 77 97 3.5 -39 -62 -92 2.5 65 81 104 3.7 -32 -55 -85 2.7 65 83 108 4 -21 -44 -74 3 66 85 112 4.2 -13 -36 -65 3.5 67 87 117 4.5 0 -24 -52 4 68 88 119 4.7 -15 -43 4.5 69 89 120 5 0 -28 5 91 121 5.2 -11 5.5 123 5.5 0 Figure 9: CLK_A, CLK_B, CLK_C, CLK_D Clock Outputs The data in this table represents nominal characterization data only. Rev. 4 | Page 16 of 24 | www.onsemi.com

Figure 10: Dynamic Current vs. Output Frequency Rev. 4 | Page 17 of 24 | www.onsemi.com

Table 13: AC Timing Specifications Parameter Symbol Conditions/Descriptions Clock (MHz) Min. Typ. Max. Units Overall Output frequency* fO VDD = 5.5V VDD = 3.6V 0.8 0.8 150

100 MHz

VCO frequency* fVCO VDD = 5.5V VDD = 3.6V 230

170 MHz

VCO gain* AVCO 400 MHz/V Loop filter time constant* LFTC bit = 0 LFTC bit = 1 µs Rise time* tr V O = 0.5V to 4.5V; CL = 15pF VO = 0.3V to 3.0V; CL = 15pF 1.9 1.6 ns Fall time* tr VO = 4.5V to 0.5V; CL = 15pF VO = 3.0V to 0.3V; CL = 15pF 1.8 1.5 ns Tristate enable delay* tPZL, tPZH 1 8 ns Tristate disable delay* tPZL, tPZH 1 8 ns Clock stabilization time* tSTB Output active from power-up, via PD pin After last register is written 100 µs ms Divider Modulus Feedback divider NF See Table 2 8 2047 Reference divider NR 1 255 Post divider NP See Table 8 1 50 Clock Outputs (PLL A clock via CLK_A pin) Approximate Duty cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 100 45 55 % Jitter, long term (σy(τ))* tj(LT) On rising edges 500µs apart at 2.5V relative to an ideal clock, C L = 15pF, f XIN = 14.318MHz, N F= 220, NR = 63, NPX = 50, no other PLLs active On rising edges 500µs apart at 2.5V relative to an ideal clock, C L = 15pF, f XIN = 14.318MHz, N F= 220, NR = 63, NPX = 50, all other PLLs active (B = 60MHz, C = 40MHz, D = 14.318MHz) 100 165 ps Jitter, period (peak-peak)* tj(ΔP) From rising edge to the next rising edge at 2.5V, CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63, NPX = 50, no other PLLs active From rising edge to the next rising edge at 2.5V, C L = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63, NPX = 50, all other PLLs active (B = 60MHz, C = 40MHz, D = 14.318MHz) 100 110 390 ps Clock Outputs (PLL B clock via CLK_B pin) Approximate Duty cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 100 45 55 % Jitter, long term (σy(τ))* tj(LT) On rising edges 500µs apart at 2.5V relative to an ideal clock, C L = 15pF, f XIN = 14.318MHz, N F= 220, NR = 63, NPX = 50, no other PLLs active On rising edges 500µs apart at 2.5V relative to an ideal clock, C L = 15pF, f XIN = 14.318MHz, N F= 220, NR = 63, NPX = 50, all other PLLs active (A = 50MHz, C = 40MHz, D = 14.318MHz) 100 ps Jitter, period (peak-peak)* tj(ΔP) From rising edge to the next rising edge at 2.5V, C L = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63, NPX = 50, no other PLLs active From rising edge to the next rising edge at 2.5V, C L = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63, NPX = 50, all other PLLs active (A = 50MHz, C = 40MHz, D = 14.318MHz) 100 120 400 ps Rev. 4 | Page 18 of 24 | www.onsemi.com

Table 13: AC Timing Specifications continued Clock Outputs (PLL_C clock via CLK_C pin) Approximate Duty cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 100 45 55 % Jitter, long term (σy(τ))* tj(LT) On rising edges 500µs apart at 2.5V relative to an ideal clock, C L = 15pF, f XIN = 14.318MHz, N F= 220, NR = 63, NPX = 50, no other PLLs active On rising edges 500µs apart at 2.5V relative to an ideal clock, C L = 15pF, f XIN = 14.318MHz, N F= 220, NR = 63, NPX = 50, all other PLLs active (A = 50MHz, B = 60MHz, D = 14.318MHz) 100 105 ps Jitter, period (peak-peak)* tj(ΔP) From rising edge to the next rising edge at 2.5V, CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63, NPX = 50, no other PLLs active From rising edge to the next rising edge at 2.5V, C L = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63, NPX = 50, all other PLLs active (A = 50MHz, B = 60MHz, D = 14.318MHz) 100 120 440 ps Clock Outputs (Crystal Oscillator via CLK_D pin) Approximate Duty cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 14.318 45 55 % Jitter, long term (σy(τ))* tj(LT) On rising edges 500µs apart at 2.5V relative to an ideal clock, C L = 15pF, f XIN = 14.318MHz, no other PLLs active From rising edges to the next at 2.5V, CL = 15pF, fXIN = 14.318MHz, all other P LLs active (A = 50MHz, B = 60MHz, C = 40MHz) 14.318 14.318 ps Jitter, period (peak-peak)* tj(ΔP) From rising edge to the next rising edge at 2.5V, CL = 15pF, fXIN = 14.318MHz, no other PLLs active From rising edge to the next rising edge at 2.5V, CL = 15pF, fXIN = 14.318MHz, all other PLLs active (A = 50MHz, B = 60MHz, C = 40MHz) 14.318 14.318 450 ps Unless otherwise stated, V DD = 5.0V ± 10%, no load on any output, and ambient temperature range T A = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3σ from typical. Table 14: Serial Interface Timing Specifications Parameter Symbol Conditions/Description Standard Mode Units Min. Max. Clock frequency fSCL SCL 0 100 kHz Bus free time between STOP and START tBUF 4.7 µs Set-up time, START (repeated) tsu:STA 4.7 µs Hold time, START tnd:STA 4.0 µs Set-up time, data input tsu:DAT SDA 250 ns Hold time, data input thd:DAT SDA 0 µs Output data valid from clock tAA Minimum delay to bridge undefined region of the falling edge of SCL to avoid unintended START or STOP 3.5 µs Rise time, data and clock tR SDA, SCL 1000 ns Fall time, data and clock tF SDA, SCL 300 ns High time, clock tHI SCL 4.0 µs Low time, clock tLO SCL 4.7 µs Set-up time, STOP Tsu:STO 4.0 µs Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T A = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3σ from typical. Rev. 4 | Page 19 of 24 | www.onsemi.com

Figure 11: Bus Timing Data Figure 12: Data Transfer Sequence

8.0 Package Information – For Both ‘Green’ and ‘No-Green’

Table 15: 16-pin SOIC (0.150") Package Dimensions Dimensions Inches Millimeters Min. Max. Min. Max. A 0.061 0.068 1.55 1.73 A1 0.004 0.0098 0.102 0.249 A2 0.055 0.061 1.40 1.55 B 0.013 0.019 0.33 0.49 C 0.0075 0.0098 0.191 0.249 D 0.386 0.393 9.80 9.98 E 0.150 0.157 3.81 3.99 e 0.050 BSC 1.27 BSC H 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 Θ 0° 8° 0° 8° Rev. 4 | Page 20 of 24 | www.onsemi.com

Table 16: 16-pin SOIC (0.150") Package Characteristics Parameter Symbol Conditions/Description Typ. Units Thermal impedance, junction to free- air16-pin 0.150” SOIC ΘJA Air flow = 0m/s 110 °C/W Lead inductance, self L11 Corner lead Center lead 4.0 3.0 nH Lead inductance, mutual L12 Any lead to any adjacent lead 0.4 nH Lead capacitance, bulk C11 Any lead to VSS 0.5 pF

9.0 Ordering Information

Part Number Package Shipping Configuration Temperature Range FS6377-01G-XTD 16-pin (0.150”) SOIC (small outline package) ‘Green’ or lead-free packaging Tube/Tray 0°C to 70°C (commercial) FS6377-01G-XTP 16-pin (0.150”) SOIC (small outline package) ‘Green’ or lead-free packaging Tape & Reel 0°C to 70°C (commercial) FS6377-01iG-XTD 16-pin (0.150”) SOIC (small outline package) ‘Green’ or lead-free packaging Tube/Tray -40°C to 85°C (industrial) FS6377-01iG-XTP 16-pin (0.150”) SOIC (small outline package) ‘Green’ or lead-free packaging Tape & Reel -40°C to 85°C (industrial)

10.0 Demonstration Software

Windows XP- (and earlier) based software is available from ON Semiconductor that illustrates the capabilities of the FS6377 and aids in application development. Contact your local sales representative for more information.

10.1 Software Requirements

• PC running MS Windows 95/98, 98 SE, ME, NT4, 2000, XP Home Edition, or XP Professional Edition
• 1.8MB available space on hard drive C
• Internet access to operate program found at www.amis.com/products/clocks/FS6377.html

10.2 Demo Program Operation

Launch the demo program from the website. Note that the parallel port cannot be accessed if your machine is not connected to th e demo board. A warning message will appear as shown in Figure 13. Clicking “Ignore” starts the program for calculation only. The FS6377 demo hardware is available on a limited basis for demonstration by an ON SEMICONDUCTOR field applications engineer, but is no longer available for purchase. The opening screen is shown in Figure 14. Rev. 4 | Page 21 of 24 | www.onsemi.com

setting of the SEL_CD pin for as long as mux B is the PLL C output. screen. A typical menu is shown in Figure 16. The range of possible post divider values is also given in Table 7. Figure 17. Individual bits can be poked, or the entire register value can be changed.

11.0 Revision History

3 October 2007 Update content to new AMIS template

4 May 2008 Update to ON Semiconductor template

Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.