FRX130R4

FRX130D INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• 6A, 100V, rDS(ON) =0.180Ω
• Second Generation Rad Hard MOSFET Results From New Design Concepts
• Gamma - Meets Pre-RAD Specifications to 100K RAD (Si) - Defined End-Point Specs at 300K RAD (Si) and 1000K RAD (Si) - Performance Permits Limited Use to 3000K RAD (Si)
• Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM
• Photo Current - 1.50nA Per-RAD (Si)/s Typically
• Neutron - Maintain Pre-RAD Specifications for 3E13 Neutrons/cm2 - Usable to 3E14 Neutrons/cm2

Description

The Intersil has designed a series of SECOND GENERA- TION hardened power MOSFETs of both N-Channel and P-Channel enhancement types with ratings from 100V to 500V, 1A to 60A, and on resistance as low as 25mΩ . Total dose hardness is offered at 100K RAD (Si) and 1000K RAD (Si) with neutron hardness ranging from 1E13n/cm 2 for 500V product to 1E14n/cm2 for 100V product. Dose rate hardness (GAMMA DOT) exists for rates to 1E9 without current limiting and 2E12 with current limiting. This MOSFET is an enhancement-mode silicon-gate power field effect transistor of the vertical DMOS (VDMOS) struc- ture. It is specially designed and processed to exhibit mini- mal characteristic changes to total dose (GAMMA) and neutron (n o) exposures. Design and processing efforts are also directed to enhance survival to heavy ion (SEU) and/or dose rate (GAMMA DOT) exposure. This part may be supplied as a die or in various packages other than shown above. Reliability screening is available as either non TX (commercial), TX equivalent of MIL-S- 19500, TXV equivalent of MIL-S-19500, or space equiva- lent of MIL-S-19500. Contact the Intersil High-Reliability Marketing group for any desired deviations from the data sheet. Symbol Package

18 LEAD CLCC

Ordering Information

FRX130D1 18 Ld CLCC FRX130D1 FRX130D3 18 Ld CLCC FRX130D3 FRX130R1 18 Ld CLCC FRX130R1 FRX130R3 18 Ld CLCC FRX130R3 FRX130R4 18 Ld CLCC FRX130R4 FRX130H4 18 Ld CLCC FRX130H4 D G S File Number 3144.3CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified FRX130D, R, H UNITS (Distance >0.063in (1.6mm) from Case, 10s Max) 300 oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 1mA, VGS = 0V 100 - - V Gate Threshold Voltage V GS(TH) ID = 1mA, VDS = VGS 2.0 4.0 V Gate-Body Leakage Forward I GSSF VGS = +20V - 100 nA Gate-Body Leakage Reverse I GSSR VGS = -20V - 100 nA Zero Gate Voltage Drain Current I DSS1 IDSS2 IDSS3 VDS = 100V, VGS = 0 VDS = 80V, VGS = 0 VDS = 80V, VGS = 0, TC = 125oC 0.025 0.25 µA Rated Avalanche Current I AR Time = 20µs- - 1 8 A Drain to Source On-State Volts V DS(ON) VGS = 10V, ID = 6A - - 1.130 V Drain to Source On Resistance r DS(ON) VGS = 10V, ID = 4A - - 0.180 Ω Turn-On Delay Time t d(ON) VDD = 50V, ID = 6A - - 30 ns Rise Time t r Pulse Width = 3µs - - 100 Turn-Off Delay Time t d(OFF) Period = 300µs, Rg = 25Ω - - 200 Fall Time t f 0 ≤ VGS ≤ 10 (See Test Circuit) - - 100 Gate-Charge Threshold Q g(TH) VDD = 50V, ID = 6A IGS1 = IGS2 0 ≤ VGS ≤ 20 1-4 ncGate-Charge On State Q g(ON) 1 7-7 0 Gate-Charge Total Q gM 32 - 128 Plateau Voltage V GP 3 - 12 V Gate-Charge Source Q gS 3- 1 4 nc Gate-Charge Drain Q gD 8- 3 2 Diode Forward Voltage V SD ID = 6A, VGD = 0 0.6 - 1.8 V Reverse Recovery Time t rr I = 6A; di/dt = 100A/µs - - 400 ns Junction To Case R θJC -- 1 1 oC/W Junction To Ambient R θJA Free Air Operation - - 250 FRX130D, FRX130R, FRX130H

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli- able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com FRX130D, FRX130R, FRX130H

18 Pin CLCC

18 PIN CERAMIC LEADLESS CHIP CARRIER

ELEMENT PAD PINS CONNECTED GATE A 5 DRAIN B 1, 2, 3, 4, 16, 17, 18 SOURCE C 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 E D R 1 R A D 2 D 1 e b L SEATING PLANE SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A 0.092 0.112 2.34 2.84 - b 0.020 0.030 0.51 0.76 - D 0.275 0.295 6.99 7.49 - D 1 0.175 0.215 4.45 5.46 - D 2 0.070 0.080 1.78 2.03 - E 0.340 0.360 8.64 9.14 - E1 0.240 0.280 6.10 7.11 - E2 0.095 0.105 2.42 2.66 - e 0.050 BSC 1.27 BSC - L 0.085 0.115 2.16 2.92 - L 1 0.035 0.055 0.89 1.39 - R 0.007 0.017 0.18 0.43 4 R 1 0.003 0.013 0.08 0.33 4 NOTES: 1. No current JEDEC outline for this package. 2. All exposed metallized areas shall be plated with a minimum of 50 microinches of gold over nickel unless otherwise stated. 3. Metallized castellations shall be connected to the seating plane and extend upward toward top of package. 4. Corner shape (notch, radius, square, etc.) may vary at the manu- facturer's option. 5. Unless otherwise specified, a minimum clearance of 0.010 inches (0.25mm) shall be maintained between all metallized areas. 6. Controlling dimension: Inch. 7. Revision 1 dated 6-93.