FR65E

FR65E FUJITSU | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 87

Technical content

DS07-16309-3EFUJITSU SEMICONDUCTOR DATA SHEET 32-Bit Microcontroller CMOS FR65E Series MB91307B n DESCRIPTION The FUJITSU FR family of single-chip microcontrollers using a 32-bit high-performance RISC CPU, with a variety of built-in I/O resources and bus control mechanisms for built-in control applications requiring high-capability, high-speed CPU processing. External bus access is assumed in order to support the expanded address space accessible by the 32-bit CPU, and a 1 KB cache memory plus large 128 KB RAM are provided for high-speed execution of CPU instructions. This microcontroller is ideal for built-in applications such as DVD players, navigation systems, high-capability FAX and printer control that demand high-capability CPU processing power. The MB91307B is a FR65E series product based on the FR30/40 series CPU with enhanced bus access for higher speed operation. n FEATURES FR CPU

• 32-bit RISC, load/store architecture, 5-stage pipeline
• Operating frequency 66MHz [with PLL: base frequency 16.5 MHz]
• 16-bit fixed length instructions (basic instructions), 1 instruction per cycle (Continued) n PACKAGE 120-pin, plastic LQFP (FPT-120P-M21) Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.

• Instructions for built-in applications: memory-to-memory transfer, bit processing, barrel shift etc.
• Instructions adapted for high-level languages: function input/output instructions, register contents multi-load/ store instructions
• Easier assembler notation: register interlock function
• Built-in multiplier/instruction level support Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles
• Interrupt (PC, PS removal): 6 cycles, 16 priority levels
• Harvard architecture for simultaneous execution of program access and data access
• CPU hold 4-word queue allows advanced instruction fetch function
• 4 GB expanded memory space enables linear access
• Instruction compatible with FR30/40 family Bus Interface
• Operating frequency: Max 33 MHz
• 8- or 16-bit data output
• Built-in pre-fetch buffer
• Unused data/address pins can be used as general-0purpose input/output ports
• Fully independent 8-area chip select outputs, can be set in minimum 64 KB units
• Interface support for many memory types SRAM, ROM/Flash Page mode flash ROM, page mode ROM interface Burst mode flash ROM (select burst length 1, 2, 4, 8)
• Basic bus cycle: 2 cycles
• Programmable by area with automatic wait cycle generation to enable wait insert
• RDY input for external wait cycles
• DMA supports fly-by transfer with independent I/O wait control Built-in RAM
• 128 KB built-in RAM capacity
• Accepts writing of data and instruction codes, enabling use as instruction RAM Instruction cache
• 1 K B c a p a c i t y
• 2-way set associative
• 4-words (16 bytes) per set
• Lock function enables permanent program storage
• Areas not used for instruction cache can be used for RAM DMAC (DMA controller)
• 5-channel (3-channel external-to-external)
• 3 transfer sources (external pin, internal peripheral, software)
• Addressing mode with 32-bit full address indication (increment, decrement, fixed)
• T ransfer mode (demand transfer / burst transfer / step transfer / block transfer)
• Fly-by transfer support (3 channels between external I/O and external memory)
• T ransfer data size selection 8/16/32-bit Bit search module (using REALOS)
• Searches words from MSB for first bit position of a 1/0 change Reload timer (includes 1 channel for REALOS)
• 16-bit timer: 3 channels
• Internal clock multiplier choice of x2, x8, x32 (Continued)

(Continued) UART

• Full duplex double buffer
• 3-channel
• Parity/no parity selection
• Asynchronous (start-stop synchronized), CLK-synchronized communications selection
• Built-in exclusive baud rate timer
• External clock can be used as transfer clock
• Variety of error detection functions (parity, frame, overrun) I 2C interface Interrupt controller
• T otal of 9 external interrupts: 1 non-maskable interrupt pin (NMI) and 8 normal interrupt pins INT7-INT0
• Interrupt from internal peripheral devices
• Programmable priority settings (16 levels) enabled, except for non-maskable interrupt
• Can be used for wake-up from stop mode A/D converter
• 10-bit resolution, 4-channel
• Sequential comparator type, conversion time approx. 5.4 ms
• Conversion modes: single conversion mode, continuous conversion mode
• Startup source: software / external trigger / timer output signal Other interval timers
• 16-bit timer with 3 channels (U-timer)
• Watchdog timer I/O port
• Maximum 69 ports Other features
• Built-in oscillator circuit for clock source, PLL multiplier selection enabled
• I N I T reset pin
• Also included: watchdog timer reset, software reset
• Power-saving modes: stop mode, sleep mode supported
• Gear functions
• Built-in time base timer
• Packages: LQFP-120 (FPT -120P-M21) : MB91307B : MB91V307R(Evaluation product)
• CMOS technology : 0.25 mm
• Supply voltage : 3.3 V – 0.3 V (built-in regulator 3.3 V fi 2.5 V)
• Master/slave sending and receiving • Arbitration function
• Clock synchronization function • Slave address/general call address detection function
• T ransfer direction detection function • Start condition repeat generator and detection function
• Bus error detection function • 10-bit/7-bit slave address
• Operates in standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps)

(TOP VIEW) (FPT-120P-M21) * : “L” level output after initialization and reset PA3/CS3 PA4/CS4 PA5/CS5 C PA6/CS6 PA7/CS7 P80/RDY P81/BGRNT P82/BRQ RD UUB/WR0 P85/ULB/WR1 NMI HST V SS INIT P90/SYSCLK P91 P92/MCLK P93 P94/LBA/AS P95/BAA P96 P97/WE P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 PI5/SC1 PI4/SO1 PI3/SI1 PI2/SC0 PI1/SO0 PI0/SI0 V CC PJ7/INT7/ATG PJ6/INT6/TIN2 PJ5/INT5/TIN1 PJ4/INT4/TIN0 PJ3/INT3 PJ2/INT2 PJ1/INT1 PJ0/INT0 AN3 AN2 AN1 AN0 AV SS /AVRL AVRH AV CC A24/P70 A23/P67 A22/P66 A21/P65 A20/P64 A19/P63 A18/P62 A17/P61 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 P26/D22 P27/D23 D24 D25 D26 D27 D28 D29 D30 D31 V SS A00 A01 A02 A03 A04 A05 A06 A07 V CC A08 A09 A10 A11 A12 A13 A14 A15 V SS P60/A16 PA2/CS2 PA1/CS1 PA0/CS0 PB7/IORD PB6/IOWR V CC V SS PB5/DEOP1/DSTP1 PB4/DACK1 PB3/DREQ1 PB2/DEOP0/DSTP0 PB1/DACK0 PB0/DREQ0 MD2 MD1 MD0 PG2/DEOP2/DSTP2 PG1/DACK2 PG0/DREQ2 PH7/SCL PH6/SDA PH5/TOT2 PH4/TOT1 PH3/TOT0 * VSS PH2/SC2 PH1/SO2 PH0/SI2

(Continued) Pin no. Pin name I/O circuit type Description 85 to 92 D16 to D23 C External data bus bits 16-23 Valid only in external bus 16-bit mode. P20 to P27 These pins can be used as ports in external bus 8-bit mode 93 to 100 D24 to D31 C External data bus bits 24-31 102 to 109 A00 to A07 F External address output bits 0-7 111 to 118 A08 to A15 F External address output bits 8-15 120, 1 to 7 A16 to A23 F External address output bits 16-23 P60 to P67 These pins can be used as ports according to setting

8 A24 F External data bus output bit 24

P70 This pin can be used as a port according to setting 9A V CC ¾ Power supply pin. Analog power supply for A/D converter

10 AVRH ¾ A/D converter reference voltage supply

11 AV SS /AVRL ¾ Power supply pin. Analog power supply for A/D converter 12 to 15 AN0 to AN3 D A/D converter reference voltage supply. Analog input pin. 16 to 19 INT0 to INT3 I INT0-INT3: External interrupt input. When the corresponding external interrupt is enabled, this input is in use at all times, so that output from other functions must be stopped unless used intentionally PJ0 to PJ3 PJ0-PJ3: General purpose input/output port 20 to 22 TIN0 to TIN2 I TIN0-TIN2: Reload timer input. When the corresponding timer input is enabled, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. INT4 to INT6 INT4-INT6: External interrupt input. When the corresponding external interrupt is enabled, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. PJ4 to PJ6 PJ4-PJ6: General purpose input/output port ATG I AT G: A/D converter external trigger input. When selected as an A/D start source, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. INT7 INT7: External interrupt input. When the corresponding external interrupt is enabled, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. PJ7 PJ7: General purpose input/output port

25 SI0 F

SI0: UART0 data input. When the UART0 channel is in input operation, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. PI0 PI0: General purpose input/output port. SO0 F SO0: UART0 data output. This function is valid when the UART0 data output function setting is disabled. PI1 PI1: General purpose input/output port. This function is valid when the UART0 data output function setting is disabled.

(Continued) Pin no. Pin name I/O circuit type Description SC0 F SC0: UART0 clock output. The clock output is valid when the UART0 clock output function setting is enabled. PI2 PI2: General purpose input/output port. This function is valid when the UART0 clock output function is disabled. SI1 F SI1: UART1 data input. When UART1 is set for input operation, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. PI3 PI3: General purpose input/output port. SO1 F SO1: UART1 data output. This function is enabled when the UART1 data output function setting is enabled. PI4 PI4: General purpose input/output port. This function is valid when the UART1 data output function setting is disabled. SC1 F SC1: UART1 clock input/output. The clock output is enabled when the UART1 clock output function setting is enabled. PI5 PI5: General purpose input/output port. This function is valid when the UART1 clock output function setting is disabled. SI2 F SI2: UART2 data input. When UART2 is set for input operation, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. PH0 PH0: General purpose input/output port. SO2 F SO2: UART2 data output. This function is enabled when the UART2 data output function setting is enabled. PH1 PH1: General purpose input/output port This function is enabled when the UART2 data output function setting is disabled. SC2 F SC2: UART2 clock input/output. The clock output is enabled when the UART2 clock output function setting is enabled. PH2 PH2: General purpose input/output port This function is enabled when the UART2 clock output function is disabled. TOT0 C TOT0: Timer output port. This function is valid when the timer output setting is enabled. PH3 PH3: General purpose input/output port.This pin outputs an L level signal at reset. TOT1 C TOT1: Timer output port. This function is valid when the timer output setting is enabled. PH4 PH4: General purpose input/output port.This pin outputs an L level signal at reset.

37 TOT2 C

TOT2: Timer output port. This function is valid when the timer output is enabled. PH5 PH5: General purpose input/output port.

(Continued) Pin no. Pin name I/O circuit type Description SDA Q SDA: I2C bus input/output port. This function is valid when I2C operation is enabled. When the I2C bus is in use, the port output must be set to Hi-Z level. When the I2C bus is in use, this is an open drain pin. PH6 PH6: General purpose input/output port. SCL Q SCL: I2C bus input/output port. This function is valid when I2C operation is enabled. When the I2C bus is in use, the port output must be set to Hi-Z level. When the I2C bus is in use, this is an open drain pin. PH7 PH7: General purpose input/output port.

40 DREQ2 F

DREQ2: DMA external transfer request input. When selected as a DMA startup source, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. PG0 PG0: General purpose input/output port. DACK2 F DACK2: DMA external transfer request acknowledge output. This function is valid when the DMA transfer request acknowledge output setting is enabled. PG1 PG1: General purpose input/output port. This function is valid when the DMA transfer request acknowledge output setting is enabled. DEOP2 F DEOP2: DMA external transfer end output. This function is valid when the DMA external transfer end output setting is enabled. DSTP2 DSTP2: DMA external transfer stop input. This function is valid when the DMA external transfer stop input setting is enabled. PG2 PG2: General purpose input/output port. This function is valid when the DMA external transfer end output selection and the DMA external transfer stop input selection are disabled. 43 to 45 MD2 to MD0 G Mode pins 2-0. The setting of these two pins determines the basic operating mode. They should be connected to V cc or Vss.

46 DREQ0 F

DREQ0: DMA external transfer request input. When selected as a DMA startup source, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. PB0 PB0: General purpose input/output port. DACK0 F DACK0: DMA external transfer request acknowledge output. This function is valid when the DMA transfer request acknowledge output setting is enabled. PB1 PB1: General purpose input/output port. This function is enabled when the DMA transfer request acknowledge output setting is disabled. DEOP0 F DEOP2: DMA external transfer end output. This function is valid when the DMA external transfer end output setting is enabled. DSTP0 DSTP0: DMA external transfer stop input. This function is valid when the DMA external transfer stop input setting is enabled. PB2 PB2: General purpose input/output port. This function is valid when the DMA external transfer end output selection and the DMA external transfer stop input selection are disabled.

(Continued) Pin no. Pin name I/O circuit type Description DREQ1 F DREQ1: DMA external transfer request input. When selected as a DMA startup source, this input is in use at all times, so that output from other functions must be stopped unless used intentionally. PB3 PB3: General purpose input/output port. DACK1 F DACK1: DMA external transfer request acknowledge output. This function is valid when the DMA transfer request acknowledge output setting is enabled. PB4 PB4: General purpose input/output port. This function is enabled when the DNA transfer request acknowledge output setting is disabled. DEOP1 F DEOP1: DMA external transfer end output. This function is valid when the DMA external transfer end output setting is enabled. DSTP1 DSTP1: DMA external transfer stop input. This function is valid when the DMA external transfer stop input setting is enabled. PB5 PB5: General purpose input/output port. This function is valid when the DMA external transfer end output selection and the DMA external transfer stop input selection are disabled.

53 X1 A Clock (oscillator) output

54 X0 Clock (oscillator) input

F IOWR : Write strobe output for DMA fly-by transfer. This function is valid when the DMA fly-by transfer write strobe output setting is enabled. PB6 PB6: General purpose input/output port. This function is valid when the DMA fly-by transfer write strobe output setting is disabled. IORD F IORD : Read strobe output for DMA fly-by transfer. This function is valid when the DMA fly-by transfer read strobe output setting is enabled. PB7 PB7: General purpose input/output port. This function is valid when the DMA fly-by transfer read strobe output setting is disabled. CS0 F CS0: Chip select output. This function is valid when the chip select 0 output setting is enabled. PA1 PA1: General purpose input/output port. This function is valid when the chip select 0 output setting is disabled. CS1 F CS1: Chip select output. This function is valid when the chip select 1 output setting is enabled. PA1 PA1: General purpose input/output port. This function is valid when the chip select 1 output setting is disabled. CS2 F CS2: Chip select output. This function is valid when the chip select 2 output setting is enabled. PA2 PA2: General purpose input/output port. This function is valid when the chip select 2 output setting is disabled. CS3 F CS3: Chip select output. This function is valid when the chip select 3 output setting is enabled. PA3 PA3: General purpose input/output port. This function is valid when the chip select 3 output setting is disabled.

(Continued) Pin no. Pin name I/O circuit type Description CS4 F CS4: Chip select output. This function is valid when the chip select 4 output setting is enabled. PA4 PA4: General purpose input/output port. This function is valid when the chip select 4 output setting is disabled. CS5 F CS5: Chip select output. This function is valid when the chip select 5 output setting is enabled. PA5 PA5: General purpose input/output port. This function is valid when the chip select 5 output setting is disabled. 64 C ¾ C: Bypass capacitor pin for internal capacitor. See “HANDLING DEVIC- ES” CS6 F CS6: Chip select output. This function is valid when the chip select 6 output setting is enabled. PA6 PA6: General purpose input/output port. This function is valid when the chip select 6 output setting is disabled. CS7 F CS7: Chip select output. This function is valid when the chip select 7 output setting is enabled. PA7 PA7: General purpose input/output port. This function is valid when the chip select 7 output setting is disabled. RDY C RDY: External ready signal input. This function is valid when the external ready input setting is enabled. P80 P80: General purpose input/output port. This function is valid when the external ready input setting is disabled. BGRNT F BGRNT : External bus open acknowledge output. This pin outputs an L level signal when the external bus is open. This function is valid when the output setting is enabled. P81 P81: General purpose input/output port. This function is valid when the output setting is disabled. BRQ P BRQ: External bus open request input. The input value is “1” when the external bus is open. This function is valid when the input setting is enabled. P82 P82: General purpose input/output port. This function is valid when the input setting is disabled. 70 RD M External bus read strobe output.

71 WR0

External bus write strobe output. UUB : Is the upper side of the 16-bit SRAM input/output mask enable signal. It is valid when the external bus is set to SRAM use. (WE/P97 function as the write strobe.) WR1 ULB F External bus write strobe output. ULB : Is the lower side of the 16-bit SRAM input/output mask enable signal. It is valid when the external bus is set to SRAM use. (WE/P97 function as the write strobe.) P85 P85: General purpose input/output port. This function is valid when the enable output setting is disabled.

(Continued) Pin no. Pin name I/O circuit type Description

73 NMI HN M I request input

74 HST H Hardware standby input

76 INIT B External reset input

F SYSCLK: System clock output. This function is valid when the system clock output setting is enabled. The clock signal output is at the same fre- quency as the external bus operating frequency. Clock output halts in the stop mode or the hardware standby mode. P90 P90: General purpose input/output port. This function is enabled when the system clock output setting is disabled. 78 P91 F P91: General purpose input/output port. This function is enabled when the SDRAM clock enable output setting is disabled. MCLK F MCLK: Memory clock output. Clock output halts in the sleep mode, the stop mode or the hardware standby mode. P92 P92: General purpose input/output port. This function is enabled when the clock output setting is disabled. 80 P93 F P93: General purpose input/output port. This function is enabled when the SDRAM clock re-input setting is disabled. AS F AS : Address strobe output. This function is valid when the address strobe output setting is disabled. LBA LBA : Burst flash ROM address load output. This function is valid when the address load output setting is enabled. P94 P94: General purpose input/output port. This function is valid when the address load output and address strobe output settings are disabled. BAA BAA : Burst flash ROM address advance output. This function is valid when the address advance output setting is enabled. P95 P95: General purpose input/output port. This function is valid when the address advance output and column address strobe output settings are disabled. 83 P96 F P96: General purpose input/output port. This function is enabled when the column address strobe output setting is disabled. WE WE : Write strobe output for 16-bit SRAM. This function is enabled when the write strobe output setting is enabled. P97 P97: General purpose input/output port. This function is enabled when the write strobe output setting is prohibited. 9A V CC ¾ A/D converter power supply

10 AVRH ¾ A/D converter power supply

11 AV SS /AVRL ¾ A/D converter power supply (GND)

24, 55,

110 VCC ¾ Power supply pins

34, 52, 75, 101 VSS ¾ Power supply pins (GND)

(Continued) Type Circuit Remarks A

• Oscillator feedback resistance approx. 1 MW B
• CMOS hysteresis input with pull-up resistance (25 kW ) C
• CMOS level input/output with standby control D
• Analog input with switch STANDBY CONTROL clock input digital input STANDBY CONTROL digital input digital output digital output CONTROL analog input

(Continued) Type Circuit Remarks F

• CMOS level output CMOS level hysteresis input with standby control G
• CMOS level input without standby control H
• CMOS level hysteresis input without standby control I
• CMOS level input
• CMOS level hysteresis input without standby control M
• CMOS level input STANDBY CONTROL digital output digital input digital output digital input digital input digital output digital input digital output digital output digital output

(Continued) Type Circuit Remarks P

• CMOS level input/output with standby control with pull-down resistance (25 kW ) Q
• Open drain output CMOS level hysteresis input with standby control STANDBY CONTROL CONTROL digital output digital input digital output STANDBY CONTROL digital input Open drain control digital output

• Preventing Latchup When CMOS integrated circuit devices are subjected to applied voltages higher than Vcc at input and output pins (other than medium- and high-withstand voltage pins), or to voltages lower than Vss, as well as when voltages in excess of rated levels are applied between Vcc and Vss, a phenomenon known as latchup can occur. When a latchup condition occurs, supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.
• T reatment of unused input pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistance.
• Power supply pins Devices are designed to prevent problems such as latchup when multiple Vcc and Vss supply pins are used, by providing internal connections between pins having the same potential. However, in order to reduce unwanted radiation, prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total output current ratings, all such pins should always be connected externally to power supplies and ground. Also, care must be given to connecting the V cc and Vss pins of this device to a current source with as little impedance as possible. In addition, it is recommended that a bypass capacitor of 1.0 mF be connected between Vcc and Vss as close to the pins as possible.
• Crystal oscillators Noise in proximity to the X0 and X1 pins can cause abnormal operation in this device. Printed circuit boards should be designed so that the X0 and X1 pins, and oscillators (or crystal oscillators), as well as bypass capacitors connected to ground, are placed as close together as possible. The use of printed circuit board architecture in which the X0 and X1 pins are surrounded by ground contributes to stable operation and is strongly recommended.
• T reatment of NC pins Any pins marked “NC” (not connected) must be left open.
• Mode pins (MD0-MD2) These pins should be used in direct connection to Vcc or Vss. T o prevent noise from causing the device to erroneously switch into test mode, the printed circuit board design should allow the shortest possible pattern length between mode pins and V cc or Vss, and the connection should have as little impedance as possible.
• Operation at startup Immediately after a power-on startup, always apply a reset initialization (INIT) at the INIT pin. Also, in order to assure a wait period for the oscillator circuits to stabilize immediately after startup, be sure that the “L” level input to the INIT pin continues for the required stabilization wait interval. (The INIT cycle for the INIT pin includes only the minimum setting for the stabilization wait period.)
• Base oscillator input at startup At power-on startup, always input a clock signal until the oscillator stabilization wait period is ended.

• Hardware standby at power-on startup If a power-on startup is followed immediately by a hardware standby request, the reset initialization of settings (INIT) from the INIT pin has priority. However in case of transition from the reset initialization (INIT) to hardware standby, the oscillator stabilization wait period is initialized to maximum duration, and after release of the hardware standby request the maximum setting is applied to the oscillator stabilization wait period.
• Caution on Operations during PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
• Remarks for the external clock operation When selecting the external clock, active X0 pin generally. Also simultaneously the opposite phase clock to X0 must be supplied to X1 pin. When using the clock along with STOP (oscillation stopped) mode, the X1 pin stops when “H” is input in STOP mode. T o prevent one output from competing against another, in this case, the stop mode must not be used. Refer to the Data Sheet for maximum input frequency.
• Built-in DC-DC regulator This device has a built-in regulator, requiring 3.3 V input to the Vcc pin and a bypass capacitor of approximately 0.1 mF connected to the C pin for the regulator. Note that the A/D converter requires a separate 3.3 V power supply. MB91307B Using external clock (normal) Note : Stop mode (oscillation stop mode) cannot be used. 3.3 V 0.1 mF CVCC AV CC AVRH AV SS /AVRL VSS GND

• Precautions for use of stop mode The built-in regulator in this device stops operating when the device is in stop mode. In such cases as when increased leak current (ICCH ) in stop mode, or abnormal operation or power fluctuation due to noise while in operating mode cause the regulator to stop, the internal 2.5 V power supply can ball below the voltage at which operation is assured. Therefore it is necessary when using the internal regulator and stop mode to assure that the external power supply does not fall below 3.3 V . And even if this should occur, the internal regulator can be set to restart when a reset is applied. (In this case the oscillator stabilization wait period should also be set to L level.) Sample use of Stop Mode with 3.3 V power supply
• Low-power consumption modes
• To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR, or time-base counter control register) and be sure to use the following sequence: (LDI #value_of_standby, R0) (LDI #_STCR, R12) STB R0, @R12 ; Write to standby control register (STCR) LDUB @R12, R0 ; Read STCR for synchronous standby LDUB @R12, R0 ; Read STCR again for dummy read NOP ; NOP x 5 for timing adjustment NOP NOP NOP NOP Set the I-flag and the ILM and ICR registers to branch to an interrupt handler when the interrupt handler triggers the microcontroller to return from the standby mode.
• If you use the monitor debugger, follow the precautions below: Do not set a breakpoint within the above array of instructions. Do not single-step the above array of instructions.
• Executing instructions on RAM If instruction codes are placed in RAM, they should not be placed in the last 8 address bytes 0005_FFFF8H to 0005_FFFF H . (Instruction code prohibited area) 0.1 mF C VCC 3.3 V 2.4 kW 7.6 kW GND VSS

• Notes on the PS register Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt handler to break or the PS flag to update its display setting when the debugger is being used. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case.
• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data event or emulator menu: (1) D0 and D1 flags are updated earlier. (2) The EIT handler (user interrupt/NMI or emulator) is executed. (3) Upon returning from the EIT , the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as those in (1) above.
• The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed to enable interruptions when a user interrupt or NMI trigger event has occurred. (1) The PS register is updated earlier. (2) The EIT handler (user interrupt/NMI or emulator) is executed. (3) Upon returning from the EIT , the above instructions are executed and the PS register is updated to the same value as that in (1) above.
• Notes on I-BUS Memory Do not access data in the instruction cache control register or the instruction cache RAM immediately before the RETI instruction. m Unique to the evaluation chip MB91V307R
• Simultaneous occurrences of a software break and a user interrupt/NMI When a software break and a user interrupt /NMI take place at the same time, the emulator debugger can cause the following phenomena:
• The debugger stops pointing to a location other than the programmed breakpoints.
• The halted program is not re-executed correctly. If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has been used, avoid setting any break at the relevant location.
• Single-stepping the RETI instruction If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.
• A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data event break to access to the area containing the address of a system stack pointer.

The FR series CPU is a high-performance core using RISC architecture with a high-capability instruction set intended for built-in applications. 1. Features

• Uses of RISC Architecture Basic instruction set: 1 instruction to 1 cycle.
• 32-bit architecture General-purpose registers: 32-bits · 16 registers
• 4 GB linear memory space
• Built-in multipliers 32-bit · 32-bit multiplication: 5 cycles 16-bit · 16-bit multiplication: 3 cycles
• Enhanced interrupt processing High-speed response (6 cycles) Multiple interrupt support Level masking functions (16 levels)
• Enhanced I/O operating instructions Memory-to-memory transfer instructions Bit processing instructions
• High code efficiency Basic instruction length: 16 bits
• Low power consumption Sleep mode, stop mode
• Gear function

1. Internal Architecture The FR series CPU uses a Harvard architecture with independent instruction bus and data bus. The instruction bus (I-BUS) is connected to an on-chip instruction cache. a 32-bit ‹fi 16-bit bus converter is connected to the bus (F-BUS) to provide an interface between the CPU and peripheral resources. The Harvard ‹fi Princeton bus converter is connected to the both the I-BUS and D-BUS as an interface between the CPU and bus controller. Internal Architecture FRex CPU D bus Instruction cache I address I data D address R-bus X-bus D data F address F data RAM 32 bit 16 bit Bus converter Princeton bus converter Harvard Bus controllerPeripherals resource I bus

1. Programming Model

• Basic Programming Model R12 R13 R14 R15 PC PS ¾ ILM ¾ SCR CCR TBR RP SSP USP MDH MDL AC FP SP XXXX XXXX H XXXX XXXX H 0000 0000H 32 bits [Default values] General-purpose register Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiplier result registers

1. Registers

• General Purpose Register Registers R 0 to R 15 are general-purpose registers. These registers can be used as accumulators for compu- tation operations, or as pointers for memory access. Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications. R13: Virtual accumulator R14: Frame pointer R15: Stack pointer Default values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
• PS (Program Status Register) This register holds the program status, and is divided into three parts, ILM, SCR, and CCR. All bits not defined in the diagram are reserved bits with read value “0” at all times. Write access to these bits is not enabled.
• CCR (Condition Code Register) S : Stack flag, cleared to “0” at reset. I : Interrupt flag, cleared to “0” at reset. N : Negative flag, default value at reset undefined. Z : Zero flag, default value at reset undefined. V : Overflow flag, default value at reset undefined. C : Carry flag, default value at reset undefined. R12 R13 R14 R15 AC FP SP XXXX XXXX H XXXX XXXX H 0000 0000H 32 bits [Default values] Bit positionfi PS Register 31 20 16 ILM SCR CCR 10 78 0 [Default value] - - 00XXXXB CCR Register 76543210 ¾¾ SIN Z V C

• SCR (System Condition code Register) Stepwise division flags These flags store interim data during execution of stepwise division. Step trace trap flag Indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs.
• ILM(Interrupt Level Mask Register) This register stores interrupt level mask values, for use in level masking. The register is initialized to value 15 (01111B) at reset.
• PC (Program Counte Registerr) The program counter indicates the address of the instruction that is executing. The default value at reset is undefined.
• TBR (Table Base Register) The table base register stores the starting address of the vector table used in EIT processing. The default value at reset is 000FFC00H . [Default value] XX0 B SCR Register 10 9 8 D1 D0 T [Default value] 01111B ILM Register 20 19 18 17 16 ILM4 ILM3 ILM2 ILM1 ILM0 [Default value] XXXXXXXX H PC Register 31 0 PC [Default value] 000FFC00 H TBR Register 31 0 TBR

• RP (Return Pointer) The return register stores the address for return from subroutines. During execution of a CALL instruction, the PC value is transferred to this RP register. During execution of a RET instruction, the contents of the RP register are transferred to this PC register. The default value at reset is undefined.
• SSP (System Stack Pointer) The SSP register is the system stack pointer. When the S flag is “0,” this register functions as the R15 register. The SSP register can also be explicitly specified. This register is also used as a stack pointer to indicate the stack to which the PS and PC are removed when an EIT occurs. The default value at reset is 00000000 H .
• USP (User Stack Pointer) The USP register is the user stack pointer. When the S flag is “1,” this register functions as the R15 register. The USP register can also be explicitly specified. The default value at reset is undefined. This register cannot be used with RETI instructions.
• Multiply & Divide registers The multiply and divide registers are each 32 bits in length. The default value at reset is undefined. [Default value] XXXXXXXX H RP Register 31 0 RP [Default value] 00000000H SSP Register 31 0 SSP [Default value] XXXXXXXX H USP Register 31 0 USP Multiply & Divide Registers 31 0 MDH MDL

In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating mode. 1. Mode Pins The three pins MD2, MD1, MD0 are used in mode vector fetch instructions, and also to make settings in test mode. 2. Mode Register (MODR) The mode data fetch instruction writes data to the address “0000_07FDH ” called the mode data. The area “0000_07FDH ” is the mode register (MODR). When a setting is made to this register, the device will operate the mode corresponding to that setting. The mode register can only be set by a reset source at the INIT level. It is not possible to write to this register from a user program. *No data exists at the FR family mode register address (0000_07FFH ). [bit7-3] Reserved bits These bits should always be set to “00000.” If set to any other value, stable operation is not assured. [bit2] ROMA (Internal RAM enable bit) This bit indicates whether internal RAM is enabled. [bit1, 0] WTH1, WTH0 (Bus width indicator bits) In external bus mode, these bits determine the bus width setting. In external bus mode, the value of these bits sets the BW1, 0 bits in the AMD0 register (CS0 area). Mode pin Mode name Reset vector access area Remarks MD2 MD1 MD0 0 0 1 External ROM mode vector Outside Bus width is set by mode register. ROMA Function Remarks 0 External ROM mode The built-in RAM area functions as external area. 1 Internal RAM mode The built-in RAM area is enabled. The 128 KB built-in RAM can be used. WTH1 WTH0 Bus width 0 0 8-bit 01 1 6 - b i t 1 0 Setting prohibited 1 1 Setting prohibited < Detailed register description > MODR Default Address 0000 07FDH XXXXXXXX 76543210 0 0 0 0 0 ROMA WTH1 WTH0 Operating mode setting bits

1. Memory Space The FR family has 4 GB (232 addresses) of logical address space with linear access from the CPU.

• Direct Addressing Areas The following areas of address space are used for I/O operations. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The direct areas differ according to the size of the data accessed, as follows. 2. Memory Map The following diagram illustrates memory space in the FR family. fi byte data access : 0-0FFH fi half word data access : 0-1FFH fi word data access : 0-3FFH 0000 0000H 0000 0400H 0001 0000H 0004 0000H 0006 0000H 0010 0000H FFFF FFFF H 0000 0000H 0000 0400H 0001 0000H 0004 0000H 0006 0000H 0010 0000H FFFF FFFF H I/O I/O I/O I/O I/O I/O : This model does not support single chip mode Direct addressing area See I/O map Access prohibited Internal RAM 128 KB Access prohibited External area Access prohibited External area Access prohibited Internal RAM 128 KB Access prohibited Access prohibited External area Internal ROM external bus mode External ROM external bus mode Single chip mode

• Use of Built-in RAM The MB91307B provides 128 KB of built-in RAM. T o enable use of this RAM, the mode register must be set to internal ROM external bus mode (ROMA=1). Precautions for use of this model
• The reset vector is fixed at 000F_FFFCH .
• For the MB91307B, the 128Kbyte RAM area is from 0004_0000H to 0005_FFFFH . The area from 0006_0000H to 000F_FFFFH is access prohibited.
• In order to use RAM the mode register must be set to internal ROM external bus mode.
• In internal ROM external bus mode the built-in RAM area can be used, but the vector area 000F_FFXX H is an internal area and cannot be accessed externally. Please refer to the following explanation.
• When placing instruction code in RAM, nothing should be placed in the last 8 bytes of the area 0005_FFFF8h to 0005_FFFFH . (This is an instruction code prohibited area.) 0000 0000H 0000 0400H 0001 0000H 0004 0000H 0006 0000H 0010 0000H FFFF FFFF H I/O I/O I/O I/O The shaded sections indicate internal areas Direct addressing area Refer to I/O map Access prohibited External area Access prohibited External area After reset release After mode setting Internal ROM external bus mode Internal RAM 128 KB Access prohibitedExternal area External area After mode register setting the vector area is an internal area. Therefore before writing to the mode register it is necessary to rewrite the TBR register so that the vector area is changed to an external area.

n USER PROGRAM INITIALIZATION The following sequence describes an example using built-in RAM. 1. Hardware Setting Conditions 2. Immediately After Reset Release 1) Assume that 1 MB of external ROM is placed beginning at 0010_0000H . Place the program at this location in the linker. (The following description can apply to other addresses than this one as well.) 2) Connect addresses A19 to A1 (1 MB) to ROM, other addresses will use CS0. 3) Set the mode pins (MD2, MD1, MD0) to external vectors. 4) Write the reset vector to 001F_FFFCH . Likewise write the mode vector to 001F_FFF8H . 1) After reset release, the CPU will attempt to load a mode vector from 000F_FFF8H , a reset vector from 000F_FFFC H , however because this will be an external vector, the CPU will have to go externally. However the CS0 default value causes 1 MB of external ROM to be repeated in external space, so that the mode vector and the reset vector itself will load the contents written at 001F_FFF8H and 001F_FFFCH in external ROM. 2) The branch destination is set in the linker to an address in the area 001X_XXXXH , so that subsequent pro- gram execution will be in this area. CS0 External ROM A19-1 Normal setting MB91307B CS0 External ROM External ROM 0000_0000H 0004_0000H FFFF_FFFF H MB91307B

1 MB of ROM can be

address map.

1. User Program Initialization Steps 1) Set the TBR register so that the interrupt table is 001F_FFXXH , then perform initialization. This process also includes a chip select setting, and at the same time the CS0 address is set to be valid at 001X_XXXXH . The CS0 decoding result is the same before and after the setting, so that the CPU can continue to run programs on external ROM. 2) If necessary, initialize the contents of RAM. 3) Now initialization is complete, and the application program can be executed. CS0 External ROM External ROM 0000_0000H 0004_0000H 0010_0000H 001F_FFFF H FFFF_FFFF H MB91307B

1 MB of ROM space

address map.

This map shows the correlation between areas of memory space and individual registers in peripheral resources. [How to read the map] Note: Default register bit values are indicated as follows: “1” : Default value “1” “0” : Default value “0” “X” : Default value “X” “-“ : No physical register at this location Address Register Block 000000H PDR0 [R/W] PDR1 [R/W] PDR2 [R/W] PDR3 [R/W] T-unit Port Data RegisterXXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Read/write attributes Register default value after reset Register name (1-column registers at address 4n, 2-column registers at address 4n + 2 … ) Left most register address (for word access, the first column of the register contains the MSB end of the data)

(Continued) Address Register Block 000000H ¾¾ PDR2 [R/W] T-unit Port Data Register XXXXXXXX 000004H ¾¾ PDR6 [R/W] PDR7 [R/W] 000008H PDR8 [R/W] PDR9 [R/W] PDRA [R/W] PDRB [R/W] --X--XXX XXXXXXX- XXXXXXXX XXXXXXXX 00000C H ¾ 000010H PDRG [R/W] PDRH [R/W] PDRI [R/W] PDRJ [R/W] R-bus Port Data Register -----XXX XXX00XXX ---XXXXX XXXXXXXX 000018H to 00001C H 000020H to 00003C H ¾ Reserved 000040H EIRR [R/W] ENIR [R/W] ELVR [R/W] Ext int 00000000 00000000 00000000 000044H DICR [R/W] HRCL [R/W] ¾ DLYI/I-unit 000048H TMRLR [W] TMR [R] Reload Timer 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00004C H ¾ TMCSR [R/W] ----0000 00000000 000050H TMRLR [W] TMR [R] Reload Timer 1XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000054H ¾ TMCSR [R/W] ----0000 00000000 000058H TMRLR [W] TMR [R] Reload Timer 2 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00005C H ¾ TMCSR [R/W] ----0000 00000000 000060H SSR [R/W] SIDR [R/W] SCR [R/W] SMR [R/W] UART000001-00 XXXXXXXX 00000100 00--0-0- 000064H UTIM [R] (UTIMR [W] ) DRCL [W] UTIMC [R/W] 000068H SSR [R/W] SIDR [R/W] SCR [R/W] SMR [R/W] UART1 00001-00 XXXXXXXX 00000100 00--0-0-

(Continued) Address Register 00006C H UTIM [R] (UTIMR [W] ) DRCL [W] UTIMC [R/W] U-TIMER 1 000070H SSR [R/W] SIDR [R/W] SCR [R/W] SMR [R/W] UART2 00001-00 XXXXXXXX 00000100 00--0-0- 000074H UTIM [R] (UTIMR [W] ) DRCL [W] UTIMC [R/W] U-TIMER 2 000078H ADCR [R] ADCS [R/W] A/D Converter 00007C H ¾ Reserved 000080H ¾ Reserved 000084H ¾ Reserved 000088H ¾ Reserved 00008C H ¾ Reserved 000090H ¾ Reserved 000094H IBCR [R/W] IBSR [R/W] ITBA [R/W] I2C interface 000098H ITMK [R/W] ISMK [R/W] ISBA [R/W] 00----11 11111111 01111111 00000000 00009C H ¾ IDAR [R/W] ICCR [R/W] IDBL [R/W] 0000A0H ¾ Reserved 0000A4H ¾ Reserved 0000A8H ¾ Reserved 0000AC H ¾ Reserved 0000B0H ¾ Reserved

(Continued) Address Register Block 000200H DMACA0 [R/W] DMAC 00000000 0000XXXX XXXXXXXX XXXXXXXX 000204H DMACB4 [R/W] 00000000 00000000 00000000 00000000 000208H DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00020C H DMACB4 [R/W] 00000000 00000000 00000000 00000000 000210H DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000214H DMACB4 [R/W] 00000000 00000000 00000000 00000000 000218H DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00021C H DMACB4 [R/W] 00000000 00000000 00000000 00000000 000220H DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000224H DMACB4 [R/W] 00000000 00000000 00000000 00000000 000228H ¾ 00022C H to 00023C H ¾ Reserved 000240H DMACR [R/W] DMAC 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX 000244H to 000274H ¾ Reserved 000278H ¾ Reserved 00027C H ¾ Reserved 000280H to 0002FC H ¾ Reserved

(Continued) Address Register Block 000300H ¾ Reserved 000304H ¾ ISIZE [R/W] 000308H to 0003E0H ¾ Reserved 0003E4H ¾ ICHRC [R/W] Instruction Cache0 - 000000 0003E8H to 0003EC H ¾ Reserved 0003F0H BSD0 [W] Bit Search Module XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FC H BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000400H DDRG [R/W] DDRH [R/W] DDRI [R/W] DDRJ [R/W] R-bus Port Direction Register ----000 00011000 --000000 00000000 000404H ¾ 000408H ¾ 00040C H ¾ 000410H PFRG [R/W] PFRH [R/W] PFRI [R/W] ¾ R-bus Port Function Register 000414H ¾ 000418H ¾ 00041C H ¾ 000420H to 00043C H ¾ Reserved

(Continued) *1: These registers have different default values at reset level. The value shown is the INIT level value. *2: These registers have different default values at reset level. The value shown is the INIT level value from the INIT pin. Address Register 000440H ICR00 [R/W] ICR01 [R/W] ICR02 [R/W] ICR03 [R/W] Interrupt Control unit 000444H ICR04 [R/W] ICR05 [R/W] ICR06 [R/W] ICR07 [R/W] 000448H ICR08 [R/W] ICR09 [R/W] ICR10 [R/W] ICR11 [R/W] 00044C H ICR12 [R/W] ICR13 [R/W] ICR14 [R/W] ICR15 [R/W] 000450H ICR16 [R/W] ICR17 [R/W] ICR18 [R/W] ICR19 [R/W] Interrupt Control unit 000454H ICR20 [R/W] ICR21 [R/W] ICR22 [R/W] ICR23 [R/W] 000458H ICR24 [R/W] ICR25 [R/W] ICR26 [R/W] ICR27 [R/W] 00045C H ICR28 [R/W] ICR29 [R/W] ICR30 [R/W] ICR31 [R/W] 000460H ICR32 [R/W] ICR33 [R/W] ICR34 [R/W] ICR35 [R/W] 000464H ICR36 [R/W] ICR37 [R/W] ICR38 [R/W] ICR39 [R/W] 000468H ICR40 [R/W] ICR41 [R/W] ICR42 [R/W] ICR43 [R/W] 00046C H ICR44 [R/W] ICR45 [R/W] ICR46 [R/W] ICR47 [R/W] 000470H to 00047C H 000480H RSRR [R/W] STCR [R/W] TBCR [R/W] CTBR [W] Clock Control unit 10000000 *2 00110011 *2 00XXXX00 *1 XXXXXXXX 000484H CLKR [R/W] WPR [W] DIVR0 [R/W] DIVR1 [R/W] 00000000 *1 XXXXXXXX 00000011 * 1 00000000 *1 000488H to 0005FC H ¾ Reserved

(Continued) Address Register Block 000600H ¾¾ DDR2 [R/W] T-unit Port Direction Register 00000000 000604H ¾¾ DDR6 [R/W] DDR7 [R/W] 00000000 00000000 000608H DDR8 [R/W] DDR9 [R/W] DDRA [R/W] DDRB [R/W] --0--000 00000000 00000000 00000000 00060C H ¾ 000610H ¾¾¾¾ T-unit Port Function Register 000614H ¾¾ PFR6 [R/W] PFR7 [R/W] 000618H PFR8 [R/W] PFR9 [R/W] PFRA [R/W] PFRB1 [R/W] --1--0-- 1111111- 0-001101 00000000 00061C H PFRB2 [R/W] 000620H ¾ 000624H ¾ 000628H to 00063FH ¾ Reserved 000640H ASR0 [R/W] ACR0 [R/W] T-unit 00000000 00000000 1111XX00 00000000 000644H ASR1 [R/W] ACR1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000648H ASR2 [R/W] ACR2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00064C H ASR3 [R/W] ACR3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000650H ASR4 [R/W] ACR4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000654H ASR5 [R/W] ACR5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued) Address Register Block 000658H ASR6 [R/W] ACR6 [R/W] T-unit XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00065C H ASR7 [R/W] ACR7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000660H AWR0 [R/W] AWR1 [R/W] 011111111 11111111 XXXXXXXX XXXXXXXX 000664H AWR2 [R/W] AWR3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000668H AWR4 [R/W] AWR5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00066C H AWR6 [R/W] AWR7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000670H ¾ 000674H ¾ 000678H IOWR0 [R/W] IOWR1 [R/W] IOWR2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX 00067C H ¾ 000680H CSER [R/W] CSHR [R/W] TCR [R/W] 000000001 11111111 00000000 000684H ¾ 000684H to 0007F8H ¾ Reserved 0007FC H ¾¾ 000800H to 000AFC H ¾ Reserved 000B00H ESTS0 [R/W] ESTS1 [R/W] ESTS2 [R] DSU X0000000 XXXXXXXX 1XXXXXXX 000B04H ECTL0 [R/W] ECTL1 [R/W] ECTL2 [W] ECTL3 [R/W] 0X000000 00000000 000X0000 00X00X11

(Continued) Address Register Block 000B08H ECNT0 [W] ECNT1 [W] EUSA [W] EDTC [W] DSU XXXXXXXX XXXXXXXX XXX00000 0000XXXX 000B0C H EWPT [R] 00000000 00000000 000B10H EDTR0 [W] EDTR1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B14H to 000B1C H 000B20H EIA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B24H EIA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B28H EIA2 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B2C H EIA3 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B30H EIA4 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B34H EIA5 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B38H EIA6 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B3C H EIA7 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B40H EDTA [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B44H EDTM [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B48H EOA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B4C H EOA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B50H EPCR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued) Address Register 000B54H EPSR [R/W] DSU XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B58H EIAM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B5C H EIAM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B60H EOAM0/EODM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B64H EOAM1/EODM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B68H EOD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B6C H EOD1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B70H to 000FFCH ¾ Reserved 001000H DMASA0 [R/W] DMAC XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001004H DMADA0 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001008H DMASA1 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 00100C H DMADA1 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001010H DMASA2 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001014H DMADA2 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001018H DMASA3 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 00101C H DMADA3 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001020H DMASA4 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX 001024H DMADA4 [R/W] DMAC XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

n INTERRUPT SOURCES AND INTERRUPT VECTORS (Continued) Interrupt source Interrupt number Interrupt level Offset TBR default address RN Decimal Hex Reset 0 00 ¾ 3FC H 000FFFFC H ¾ Mode vector 1 01 ¾ 3F8H 000FFFF8 H ¾ System reserved 2 02 ¾ 3F4H 000FFFF4 H ¾ System reserved 3 03 ¾ 3F0H 000FFFF0 H ¾ System reserved 4 04 ¾ 3EC H 000FFFEC H ¾ System reserved 5 05 ¾ 3E8H 000FFFE8 H ¾ System reserved 6 06 ¾ 3E4H 000FFFE4 H ¾ Coprocessor absent trap 7 07 ¾ 3E0H 000FFFE0 H ¾ Coprocessor error trap 8 08 ¾ 3DC H 000FFFDC H ¾ INTE instruction 9 09 ¾ 3D8 H 000FFFD8 H ¾ Instruction break exception 10 0A ¾ 3D4 H 000FFFD4 H ¾ Operand break trap 11 0B ¾ 3D0 H 000FFFD0 H ¾ Step trace trap 12 0C ¾ 3CC H 000FFFCC H ¾ NMI request (tool) 13 0D ¾ 3C8 H 000FFFC8 H ¾ Undefined instruction exception 14 0E ¾ 3C4 H 000FFFC4 H ¾ NMI requ 15 0F 15 (F H ) 3C0H 000FFFC0 H ¾ External interrupt 0 16 10 ICR00 3BC H 000FFFBC H 6 External interrupt 1 17 11 ICR01 3B8 H 000FFFB8 H 7 External interrupt 2 18 12 ICR02 3B4 H 000FFFB4 H 11 External interrupt 3 19 13 ICR03 3B0 H 000FFFB0 H 12 External interrupt 4 20 14 ICR04 3AC H 000FFFAC H 13 External interrupt 5 21 15 ICR05 3A8 H 000FFFA8 H 14 External interrupt 6 22 16 ICR06 3A4 H 000FFFA4 H ¾ External interrupt 7 23 17 ICR07 3A0 H 000FFFA0 H ¾ Reload timer 0 24 18 ICR08 39C H 000FFF9C H 8 Reload timer 1 25 19 ICR09 398 H 000FFF98 H 9 Reload timer 2 26 1A ICR10 394 H 000FFF94 H 10 UART0(RX completed) 27 1B ICR11 390 H 000FFF90 H 0 UART1(RX completed) 28 1C ICR12 38C H 000FFF8C H 1 UART2(RX completed) 29 1D ICR13 388 H 000FFF88 H 2 UART0(TX completed) 30 1E ICR14 384 H 000FFF84 H 3 UART1(TX completed) 31 1F ICR15 380 H 000FFF80 H 4 UART2(TX completed) 32 20 ICR16 37C H 000FFF7C H 5 DMAC0(end, error) 33 21 ICR17 378 H 000FFF78 H ¾

(Continued) Interrupt source Interrupt number Interrupt level Offset TBR default address RN Decimal Hex DMAC1(end, error) 34 22 ICR18 374 H 000FFF74 H ¾ DMAC2(end, error) 35 23 ICR19 370 H 000FFF70 H ¾ DMAC3(end, error) 36 24 ICR20 36C H 000FFF6C H ¾ DMAC4(end, error) 37 25 ICR21 368 H 000FFF68 H ¾ A/D 38 26 ICR22 364 H 000FFF64 H 15 I2C3 9 2 7 I C R 2 3 3 6 0 H 000FFF60 H ¾ System reserved 40 28 ICR24 35C H 000FFF5C H ¾ System reserved 41 29 ICR25 358 H 000FFF58 H ¾ System reserved 42 2A ICR26 354 H 000FFF54 H ¾ System reserved 43 2B ICR27 350 H 000FFF50 H ¾ U-TIMER0 44 2C ICR28 34C H 000FFF4C H ¾ U-TIMER1 45 2D ICR29 348 H 000FFF48 H ¾ U-TIMER2 46 2E ICR30 344 H 000FFF44 H ¾ Time base timer overflow 47 2F ICR31 340 H 000FFF40 H ¾ System reserved 48 30 ICR32 33C H 000FFF3C H ¾ System reserved 49 31 ICR33 338 H 000FFF38 H ¾ System reserved 50 32 ICR34 334 H 000FFF34 H ¾ System reserved 51 33 ICR35 330 H 000FFF30 H ¾ System reserved 52 34 ICR36 32C H 000FFF2C H ¾ System reserved 53 35 ICR37 328 H 000FFF28 H ¾ System reserved 54 36 ICR38 324 H 000FFF24 H ¾ System reserved 55 37 ICR39 320 H 000FFF20 H ¾ System reserved 56 38 ICR40 31C H 000FFF1C H ¾ System reserved 57 39 ICR41 318 H 000FFF18 H ¾ System reserved 58 3A ICR42 314 H 000FFF14 H ¾ System reserved 59 3B ICR43 310 H 000FFF10 H ¾ System reserved 60 3C ICR44 30C H 000FFF0C H ¾ System reserved 61 3D ICR45 308 H 000FFF08 H ¾ System reserved 62 3E ICR46 304 H 000FFF04 H ¾ Delay interrupt source bit 63 3F ICR47 300 H 000FFF00 H ¾ System reserved (REALOS use) 64 40 ¾ 2FC H 000FFEFC H ¾ System reserved (REALOS use) 65 41 ¾ 2F8H 000FFEF8 H ¾ System reserved 66 42 ¾ 2F4H 000FFEF4 H ¾ System reserved 67 43 ¾ 2F0H 000FFEF0 H ¾ System reserved 68 44 ¾ 2EC H 000FFEEC H ¾

(Continued) Interrupt source Interrupt number Interrupt level Offset TBR default address RN Decimal Hex System reserved 69 45 ¾ 2E8H 000FFEE8 H ¾ System reserved 70 46 ¾ 2E4H 000FFEE4 H ¾ System reserved 71 47 ¾ 2E0H 000FFEE0 H ¾ System reserved 72 48 ¾ 2DC H 000FFEDC H ¾ System reserved 73 49 ¾ 2D8 H 000FFED8 H ¾ System reserved 74 4A ¾ 2D4 H 000FFED4 H ¾ System reserved 75 4B ¾ 2D0 H 000FFED0 H ¾ System reserved 76 4C ¾ 2CC H 000FFECC H ¾ System reserved 77 4D ¾ 2C8 H 000FFEC8 H ¾ System reserved 78 4E ¾ 2C4 H 000FFEC4 H ¾ System reserved 79 4F ¾ 2C0 H 000FFEC0 H ¾ Used by INT instructions to 255 to FF 2BC H to 000H 000FFEBC H to 000FFC00 H

1. Interrupt Controller (1) Overview The interrupt controller receives and processes arbitration of interrupts.

• Hardware Configuration This module is configured from the following elements.
• ICR register
• Interrupt priority determination circuit
• Interrupt level and interrupt number (vector) generator
• Hold request removal request generator
• Principal Functions This module primarily provides the following functions.
• NMI request / interrupt request detection
• Order of priority determination (according to level and number)
• Notification (to CPU) of interrupt level of source according to determination
• Notification (to CPU) of interrupt number of source according to determination
• Instruction (to CPU) to recover from stop mode when an interrupt other than NMI/interrupt level “11111” is generated
• Generation of hold request removal requests to the bus master

(2) Register List (Continued) Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : bit 7 6 5 4 3 2 1 0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 00000440 H 00000441H 00000442H 00000443H 00000444H 00000445H 00000446H 00000447H 00000448H 00000449H 0000044AH 0000044BH 0000044C H 0000044D H 0000044EH 0000044FH 00000450H 00000451H 00000452H 00000453H 00000454H 00000455H 00000456H 00000457H 00000458H 00000459H 0000045AH 0000045BH 0000045C H 0000045D H 0000045EH 0000045FH R R/W R/W R/W R/W

(Continued) Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : Address : bit 7 6 5 4 3 2 1 0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 ¾¾¾ ICR4 ICR3 ICR2 ICR1 ICR0 R R/W R/W R/W R/W ¾MHALTI ¾ LVL4 LVL3 LVL2 LVL1 LVL0 R R/WR/W R/W R/W R/W ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 HRCL 00000460 H 00000461H 00000462H 00000463H 00000464H 00000465H 00000466H 00000467H 00000468H 00000469H 0000046AH 0000046BH 0000046C H 0000046D H 0000046EH 0000046FH 00000045H

(3) Block Diagram RI00 RI47 (DLYIRQ) LEVEL4 ~ 0 MHALTI VCT5 ~ 0 R-BUS UNMI WAKEUP ICR00 ICR47 (“1” when LEVEL „ 11111) Determine order of priority NMI processing LEVEL determination VECTOR determination LEVEL, VECTOR generation HLDREQ hold request

1. External Interrupt - NMI Control Block (1) Overview The External Interrupt - control block controls external interrupt requests input at the NMI and INT0-7 pins. The request level can be selected from “H,” “L,” “rising edge,” or “falling edge” detection (except for NMI). (2) Register List (3) Block Diagram

• External interrupt enable register (ENIR)
• External interrupt source register (EIRR)
• Request level setting register (ELVR) bit bit bit bit 76 5432 10 EN6EN7 EN5 EN4 EN3 EN2 EN1 EN0 15 14 13 12 11 10 9 8 ER6ER7 ER5 ER4 ER3 ER2 ER1 ER0 15 14 13 12 11 10 9 8 LA7LB7 LB6 LA6 LB5 LA5 LB4 LA4 76 5432 10 LA3LB3 LB2 LA2 LB1 LA1 LB0 LA0 9 9 INT0 ~ 7 NMI R BUS Interrupt request Interrupt enable register Gate Source F/F Edge detection circuit Interrupt source register Interrupt level setting register

1. REALOS Related Hardware REALOS related hardware is used by the REALOS operating system. Therefore, when REALOS is in use, these resources cannot be used by user programs. 1) Delay Interrupt Module (1) Overview The delay interrupt module is a module that generates interrupts for task switching. This module can be used with software instructions to generate and cancel interrupts to the CPU. (2) Register List (3) Block Diagram Address : 7b i t 654 3 21 0 [R/W] ¾¾ ¾ ¾¾¾¾ DLYI DICR00000044H DLYI R-bus Interrupt request

2) Bit Search Module (1) Overview Searches data written to input registers for “0” or “1” or change points, and outputs the value of the detected bits. (2) Register List (3) Block Diagram Address : 0 detection data register Address : 1 detection data register Address : Change point detection register Address : Detection results register BSD0 BSD1 BSDC BSRR 000003F0H 000003F4H 000003F8H 000003FC H D-BUS Address decoder Input latch Detection mode 1 detection data capture Bit search circuit Search results

1. 16-bit Reload Timer (1) Overview The 16-bit timer is configured from a 16-bit down-counter, 16-bit reload register, prescaler for internal count clock generation, and a control register. For the input clock signal, a selection of three internal clock signals (machine clock multiplied by 2, 8, or 32) or external clock is provided. The output pin (TOUT) produces a toggle output waveform at every underflow in reload mode, and a square wave indicating counting in progress in one-shot mode. The input pin (TIN) can be used for event input in external event count mode, and trigger input or gate input in internal clock mode. The external event count function can be used in reload mode or as a frequency multiplier in external clock mode. There are three built-in 16-bit reload timer channels on this device. Channels 0 1and 1 can be used to start DMA transfer from an interrupt signal. (2) Register List

• Control status register (TMCSR)
• 16-bit timer register (TMR)
• 16-bit reload register (TMRLR) 15 14 13 12 11 10 9 8 ¾¾¾ ¾ CSL1 CSL0 MOD2 MOD1 76 5432 10 ¾MOD0 OUTL RELD INTE UF CNTE TRG 15 0 15 0

(3) Block Diagram RELD OUTE OUTL INTE UF CNTE TRG OUT CTL. CSL1 CSL0 MOD2 MOD1 MOD0 IN CTL. f f f 21 35 EXCK GATE

2 IRQ

R B U S 16-bit reload register 16-bit down counter Reload Clock selector Re-trigger Prescaler clear Internal clock Port (TIN) Port (TOT)

1. U-TIMER (16 bit timer for UART baud rate generation) (1) Overview The U-TIMER is a 16-bit timer used to generate the baud rate for the UART . Any desired baud rate can be set using the combination of chip operating frequency and U-TIMER reload value. The U-TIMER can also be used as an interval timer by generating an interrupt from a count underflow event. This device features a 3-channel built-in U-TIMER. By connecting two U-TIMER channels used as interval timers in a cascade connection, it is possible to count intervals up to a maximum of 2 32 · f. The available case connections are channel 0 to channel 1, and channel 1 to channel 2. (2) Register List (3) Block Diagram UTIMR UTIM UTIMC (W) (R) (R/W) 15 087 UTIMR (reload register) UTIM (timer) Clock Load Underflow Under flow U-TIMER 1 To UART control f.f. MUX Channel 0 only f (Peripheral clock)

1. UART (1) Overview The UART is an I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission, providing the following features. This device features a 3-channel built-in UART .

• Full duplex double buffer
• Asynchronous (start-stop synchronized) or CLK synchronized transmission enabled
• Supports multi-processor mode
• Fully programmable baud rate Built-in timer can be set to any desired baud rate (see U-TIMER description)
• Independent baud rate setting from external clock enabled.
• Error detection functions (parity, framing, overrun)
• T ransfer signal NRZ encoded
• DMA transfer start from interrupt enabled
• DMAC interrupt source cleared by write operation to DRCL register. (2) Register List
• Serial input register/Serial output registe (SIDR/SODR)
• Serial status register (SSR)
• Serial mode register (SMR)
• Serial control register (SCR)
• DRCL register (DRCL) SIDR (R)/SODR (W) SMRSCR (R/W) (R/W) (W) SSR DRCL 8 bit 8 bit 15 0 87 76 5432 10 D6D7 D5 D4 D3 D2 D1 D0 76 5432 10 OREPE FRE RDRF TDRE ¾ RIE TIE 76 5432 10 MD0MD1 ¾¾ CS0 ¾ SCKE ¾ 76 5432 10 PPEN SBL CL A/D REC RXE TXE 76 5432 10 ¾¾ ¾ ¾¾¾¾¾

(3) Block Diagram MD1 MD0 CS0 SCKE SOE PEN P SBL CL A/D REC RXE TXE PE ORE FRE RDRF TDRE RIE TIE R - BUS SIDR SODR Control signal From U-TIMER External clock SC Clock select circuit Receiving status decision circuit DMA receiving error signal (to DMAC) RX clock RX control circuit Start bit detect circuit Receiving bit counter Receiving parity counter Receiving shifter Receiving end TX clock RX interrupt (to CPU) TX interrupt (to CPU) TX control circuit Sent start circuit Sending bit counter Sending parity counter Sending shifter Sending start SMR register Control signal SCR register SSR register SC (clock) SI (receiving data) SO (Sending data)

1. A/D Converter (Sequential comparison type) (1) Overview This A/D converter is a module that coverts analog input voltages to digital values, and provides the following features.

• Minimum conversion time 5.4 ms/ch (at machine clock 33 MHz - CKLP)
• Built-in sample & hold circuit
• Resolution 10 bits (8-bit accuracy)
• Analog input: 4 channels by program selection Single conversion mode: Conversion on 1 select channel Scan conversion mode: Select continuous multiple channels. Up to 4 channels can be selected by program. Continuous conversion mode: Continuous conversion on selected channel Stop conversion mode: 1-channel conversion then pause and wait until the next start is applied (enables synchronized conversion start)
• DMA transfer start from interrupt enabled
• Start sources can be selected from software, external trigger (falling edge), reload timer (rising edge). (2) Register List
• Control status register (ADCS)
• Data register (ADCR) bit bit bit bit 15 14 13 12 11 10 9 8 INTBUSY INTE PAUS STS1 STS0 STRT ¾ 76 5432 10 MD0MD1 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 15 14 13 12 11 10 9 8 ¾¾¾ ¾ ¾ ¾ 98 76 5432 10 67 543210

(3) Block Diagram Precautions for Use: When the A/D converter is started from an external trigger or internal timer, the ADCS register A/D start source bits STS1, 0 are set, and at this time the input values for the external trigger and internal timer should be set to the inactive side. If these values are set to the active side, abnormal operation may result. When setting the STS 1, 0 bits, set A TG = “1” input, reload timer (channel 2) = “0” output. Caution: If internal impedance is higher than the specified value, it may not be possible to obtain analog input value sampling within the specified sampling time, so that proper results will not be obtained. AV CC AVRH AV SS R B U S Input switch Sample & hold circuit Channel decoder Internal voltage Sequential Data register (ADCR) AD control register ATG (External pin trigger) Reload timer ch1 (Internal connection) Timing generator PrescalerClock (CLKP)

1. I2C Interface (1) Overview The I2C interface operates as a master/slave device on the I2C bus at serial I/O ports with IC bus support. The following features are provided.

• Master/slave sending and receiving
• Arbitration function
• Clock synchronization function
• Slave address/general call address detection function
• T ransfer direction detection function
• Start condition repeat generation and detection function
• Bus error detection function
• 10-bit / 7-bit master/slave addressing
• Compatible with standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps)
• T ransfer end interrupt / bus error interrupt generation (2) Register List (Continued)
• Bus Control Register (IBCR)
• Bus Status Register (IBSR)
• 10-Bit Slave Address Register Address : 000094H Default value fi Address : 000095H Default value fi Address : 000096H Default value fi Address : 000097H Default value fi R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 BEIE R/W BER SCC MSS ACK GCAA INTE INT R R R R R R R 76 5432 10 RSC R BB AL LRB TRX AAS GCA ADT ¾¾¾¾ ¾ R/W R/W 15 14 13 12 11 10 9 8 ¾¾ ¾ ¾ ¾ TA9 TA8 R/W R/W R/W R/W R/W R/W R/W 76 5432 10 TA6 R/W TA7 TA5 TA4 TA3 TA2 TA1 TA0

(Continued)

• 10-Bit Slave Address Mask Register (ITMK)
• 7-Bit Slave Address Register (ISBA)
• 7-Bit Slave Address Mask Register (ISMK)
• Data Register (IDAR)
• Clock Control Register (ICCR)
• Clock Disable Register (IDBL) Address : 000098H Default value fi Address : 000099H Default value fi Address : 00009BH Default value fi Address : 00009AH Default value fi Address : 00009DH Default value fi Address : 00009EH Default value fi Address : 00009FH Default value fi R 0 ¾¾¾¾ R/W R/W 15 14 13 12 11 10 9 8 RAL R/W ENTB ¾¾ ¾¾ TM9 TM8 R/W R/W R/W R/W R/W R/W R/W 76 5432 10 TM6 R/W TM7 TM5 TM4 TM3 TM2 TM1 TM0 R/W R/W R/W R/W R/W R/W R/W 76 5432 10 SA6 ¾ SA5 SA4 SA3 SA2 SA1 SA0 R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 SM6 R/W ENSB SM5 SM4 SM3 SM2 SM1 SM0 R/W R/W R/W R/W R/W R/W R/W 76 5432 10 R/W D7 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 W TEST EN CS4 CS3 CS2 CS1 CS0 ¾¾¾¾ ¾¾ R/W 76 5432 10 ¾ ¾ ¾¾¾¾ DBL

(3) Block Diagram ICCR EN IDBL DBL ICCR IBSR BB RSC LRB Last Bit TRX ADT AL IBCR BER BEIE INTE INT IBCR SCC MSS ACK GCAA IBSR IDAR AAS GCA ENTB ISMK RAL ITBA ITMK ISBA ISMK CS4 CS3 CS2 CS1 CS0 2345 3 2 Sync First Byte IRQ SCL SDA I2 C operation enabled Clock enabled Clock multiplier 2 Clock select 2 (1/12) Bus busy Repeat start TX/RX Start - stop condition generator Arbitration lost detector Interrupt request Start Master ACK OK GC-ACK OK Slave Global call Slave address compare End Error Shift clock edge change Start - stop condition detector Shift clock generator R bus

1. DMAC (DMA Controller) (1) Overview This module is used to accomplish DMA (Direct Memory Access) transfer on FR family devices. DMA transfer controlled by this module increases system performance by enabling high speed transfer of many types of data without going through the CPU.

• Hardware Configuration This module is principally configured from the following units:
• Five independent DMA channels
• 5-channel independent access control circuit
• 32-bit address registers (reload enabled: 2 per channel)
• 16-bit transfer count registers (reload enabled: 2 per channel)
• 4-bit block count registers (1 per channel)
• External transfer request input pins: DREQ0,DREQ1,DREQ2 (ch0,1,2 only)
• External transfer request acknowledge output pins: DACK0,DACK1,DACK2 (ch0,1,2 only)
• DMA output completed pins: DEOP0,DEOP1,DEOP2 (ch0,1,2 only)
• Fly-by transfer (memory to I/O, memory to memory) (ch0,1,2 only)
• T wo-cycle transfer
• Principal Functions Data transfer using the DMAC module primarily involves the following functions:
• Supports independent data transfer on multiple channels (5 ch) (2) The order can be reversed between ch.0-ch.1. (3) DMAC startup sources
• Input from an external-only pin (edge detection/level detection, ch0,1,2 only)
• Request from a built-in peripheral (shared interrupt request, including external interrupts)
• Software request (register write) (4) T ransfer modes
• Demand transfer / burst transfer / step transfer / block transfer
• Addressing mode 32-bit full address designation (increment/decrement/fixed) (address increment can be specified up to -255 to +255)
• Data type, byte / half-word / word length
• Single-shot / reload selection available

(2) Register Descriptions ch.0 Control/status register A ch.0 Control/status register B ch.1 Control/status register A ch.1 Control/status register B ch.2 Control/status register A ch.2 Control/status register B ch.3 Control/status register A ch.3 Control/status register B ch.4 Control/status register A ch.4 Control/status register B Overall control register ch.0 Transfer source address register ch.0 Transfer source address register ch.1 Transfer source address register ch.1 Transfer source address register ch.2 Transfer source address register ch.2 Transfer source address register ch.3 Transfer source address register ch.3 Transfer source address register ch.4 Transfer source address register ch.4 Transfer source address register (bit) 31 24 23 16 15 08 07 00 0000200 H 0000204 H 0000208 H 000020C H 0000210 H 0000214 H 0000218 H 000021C H 0000220 H 0000224 H 0000240 H 0001000 H 0001004 H 0001008 H 000100C H 0001010 H 0001014 H 0001018 H 000101C H 0001020 H 0001024 H DMACA0 DMACB0 DMACA1 DMACB1 DMACA2 DMACB2 DMACA3 DMACB3 DMACA4 DMACB4 DMACR DMASA0 DMADA0 DMASA1 DMADA1 DMASA2 DMADA2 DMASA3 DMADA3 DMASA4 DMADA4

(3) Block Diagram Read Write DDNO BLK register DDNO register DTCR DSS [3:0] ERIR, EDIR TYPE, MOD, WS IRQ [4:0] MCLREQ X-bus DADM, DASZ [7:0] DADR SDAM, SASZ [7:0] SADR DMA transfer request to bus controller Read/write control To bus controller Bus control block Access address Address counter Counter/buffer Counter/buffer Selector Selector Write back Selector Buffer Counter Selector Write back DTC two-stage register Buffer Counter Selector DMA start source selection circuit & request acceptance control Priority circuit Status transition circuit DMA controller DDAD two-stage register DDAD two-stage register Bus control block Peripheral start request/stop input External pin start request/stop input To interrupt controller Peripheral interrupt clear DMAC 5-channel Block Diagram Write back

1. External Interface (1) Overview The external interface controller controls the interface between the LSI’s internal bus and external memory or I/ O devices. This section describes the functions of the external interface. (2) Features

• Up to 32 bit-length (4 Gbyte space) address output.
• Connects directly to many external memory (8 bit/16 bit) devices, allows control of multiple access timings. Asynchronous SRAM, asynchronous ROM/Flash memory (multiple write strobe type or byte enable type) Page mode ROM/flash memory (2/4/8 page size enabled) Burst ROM/Flash memory (MBM29BL160D/161D/162D etc.) Address/data multiplexed bus (8 bit/16 bit width only) Synchronous memory* (ASIC built-in memory etc.) *: Does not connect to synchronous SRAM.
• 8 independent bank (chip select area) settings, each with corresponding ship select output available Each area size can be set in multiples of 64 KB (from 64 KB to 2 GB per chip select area). Each area can be set in any desired area of logic address space (boundaries limited by area size).
• The following functions can be independently set for each chip select area. Chip select area enable/disable (no access to prohibited areas) Access timing type for each area, etc. Detailed access timing settings (individual access type settings for wait cycle, etc.) Data bus width setting (8 bit/16 bit) Byte ordering endian setting* (big or little). *: CS0 area available with big endian only. Write prohibited setting (read-only areas) Internal cache loading enable/disable settings Pre-fetch function enable/disable settings Maximum burst length setting (1,2,4,8)
• Different detailed timing settings for each access timing type Different settings can be used for each chip select area even for the same access timing type. Auto wait setting up to 15 cycles (asynchronous SRAM, ROM, Flash, I/O areas) Bus cycle extension with external RDY input enabled (asynchronous SRAM, ROM, Flash, I/O areas) First access wait and page wait settings enabled (burst, page mode ROM/FLASH areas) Different idle, recovery cycles setup delay insertion etc. enabled
• Fly-by transfer with DMA enabled T ransfer between memory and I/O with 1 access Memory wait cycle can be synchronized with I/O wait cycle during fly-by Hold time can be obtained by delaying transfer access only Specific idle/recovery cycles can be set for fly-by transfer
• External bus arbitration using BRQ and BGRNT enabled
• Pins not used in external interface can be set for use as general purpose I/O ports

(3) Block Diagram (4) I/O Pins These are the external interface pins. (Some pins have dual functions.) < Normal bus interface > A24 to A0, D31 to D16 CS0 , CS1, CS2, CS3, CS4, CS5, CS6, CS7 AS , SYSCLK, MCLK RD WE , WR0 (UUB) , WR1 (ULB) RDY, BRQ, BGRNT < Memory interface > MCLK LBA ( = AS) , BAA* *: For burst ROM, Flash use MUX CS0 ~ CS7 RD WR0, WR1 AS, BAA BRQ BGRNT RDY 3232 write buffer read buffer switch switch +1 or +2 address buffer ASR ASZ comparator DATA BLOCK ADDRESS BLOCK resisters & controls External pin control block All block control Internal address bus Internal data bus External data bus External address bus

< DMA interface > IOWR , IORD DACK0, DACK1, DACK2 DREQ0, DREQ1, DREQ2 DEOP0/DSTP0, DEOP1/DSTP1, DEOP2/DSTP2 (5) Register List Reserved: This address is reserved, and should always be set to “0.” MODR: Cannot be accessed from user programs. Address 31 24 23 16 15 08 07 00 00000640 H ASR0 ACR0 00000644H ASR1 ACR1 00000648H ASR2 ASR2 0000064C H ASR3 ACR3 00000650H ASR4 ACR4 00000654H ASR5 ACR5 00000658H ASR6 ACR6 0000065C H ASR7 ACR7 00000660H AWR0 AWR1 00000664H AWR2 AWR3 00000668H AWR4 AWR5 0000066C H AWR6 AWR7 00000670H Reserved Reserved Reserved Reserved 00000674H Reserved Reserved Reserved Reserved 00000678H IOWR0 IOWR1 IOWR2 Reserved 0000067C H Reserved Reserved Reserved Reserved 00000680H CSER CHER Reserved TCR 00000684H Reserved Reserved Reserved Reserved 00000688H Reserved Reserved Reserved Reserved 0000068C H Reserved Reserved Reserved Reserved 000007F8H Reserved Reserved Reserved Reserved 000007FC H Reserved (MODR) Reserved Reserved

n ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0 V) *1 : VCC must not be lower than VSS - 0.3 V . *2 : AVCC and AVRH shall never exceed VCC +0.3 V . Also AVRH shall never exceed AVCC . *3 : Maximum output current determines the peak value of any one of the corresponding pins. *4 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins. *5 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. *6 : • Applicable to pins: P20 to P27, P60 to P67, P70, PJ0 to PJ7, PI0 to PI5, PH0 to PH7, PB0 to PB5, P A0 to P A7, P80 to P82, P85, P90 to P97, AN0 to AN3

• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. Parameter Symbol Rating Unit Remarks Min Max Supply voltage V CC VSS - 0.5 V SS + 4.0 V *1 Analog supply voltage AV CC VSS - 0.5 V SS + 4.0 V *2 Analog reference voltage AVRH V SS - 0.5 V SS + 4.0 V *2 Input voltage V I VSS - 0.3 V CC + 0.3 V Analog pin input voltage V IA VSS - 0.3 AV CC + 0.3 V Output voltage V O VSS - 0.3 V CC + 0.3 V Maximum clamp current I CLAMP -2.0 2.0 mA *6 Total maximum clamp current S| ICLAMP | ¾ 20 mA *6 L level maximum output current I OL ¾ 10 mA *3 L level average output current I OLAV ¾ 8m A * 4 L level maximum total output currentSIOL ¾ 100 mA L level average total output currentSIOLAV ¾ 50 mA *5 H level maximum output current I OH ¾- 10 mA *3 H level average output current I OHAV ¾- 4m A * 4 H level maximum total output currentSIOH ¾- 50 mA H level average total output currentSIOHAV ¾- 20 mA *5 Power consumption P D ¾ 750 mW Operating temperature T A 0 +70 °C Storage temperature T STG ¾+ 150 °C

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input.
• Sample recommended circuits: WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 2. Recommended Operating Conditions (VSS = AVSS = 0 V) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Value Unit Remarks Min Max Supply voltage V CC 3.0 3.6 V In normal operation VCC 3.0 3.6 V In stop mode with RAM status maintained Analog supply voltage AV CC VSS - 0.3 V SS + 3.6 V Analog reference voltage AVRH AV SS AV CC V Operating temperature T A 0 +70 °C P-ch N-ch VCC R
• Input/Output Equivalent circuits +B input (0 V to 16 V) Limiting resistance Protective diode

1. DC Characteristics (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C) * : Pins without hysteresis input pins: D16 to D31, RDY , BRQ, INIT Parameter Symbol Pin name Condition Value Unit Remarks Min Typ Max “H” level input voltage VIH See note * ¾ 0.7 · VCC ¾ VCC + 0.3 V VHIS Input pins other than * ¾ 0.8 · VCC ¾ VCC + 0.3 V Hysteresis input “L” level input voltage VIL See note * ¾ VSS ¾ 0.25 · VCC V VILS Input pins other than * ¾ VSS ¾ 0.2 · VCC V Hysteresis input “H” level output voltage VOH D16 to D31 A00 to A24 P60 to PJ7 VCC = 3.0 V IOH = -4.0 mA VCC - 0.5 ¾ VCC V “L” level output voltage VOL D16 to D31 A00 to A24 P60 to PJ7 VCC = 3.0 V IOL = 8.0 mA VSS ¾ 0.4 V Input leak current (Hi-Z output leak current) I LI D16 to D31 A00 to A24 P60 to PJ7 VCC = 3.6 V

0.45 V<VI<VCC

-5 ¾+ 5 mA Pull-up resistance RUP INIT VCC = 3.6 V VI = 0.45 V 12 25 100 k W Pull-down resistance R DOWN P82/BRQ VCC = 3.6 V VI = 3.3 V 12 25 100 k W Supply current ICC VCC fC = 16.5 MHz VCC = 3.3 V ¾ 150 ¾ mA (4x multiplied)

66 MHz

I CCS fC = 16.5 MHz VCC = 3.3 V ¾ 50 ¾ mA Sleep mode ICCH TA = 25 °C VCC = 3.3 V ¾ 50 ¾m A Stop mode Input capacitance C IN Other than: VCC VSS AV CC AV SS ¾¾ 10 ¾ pF

1. AC Characteristics (1) Clock Timing Standards (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C) *1 : When using the PLL, the clock frequency should be around 12.5 MHz to 16.5 MHz. *2 : The values shown represent a minimum clock frequency of 12.5 MHz input at the X0 pin, using the oscillator circuit PLL and a gear ratio of 1/16. Parameter Sym- bol Pin name Condition Value Unit Remarks Min Max Clock frequency (1) f C 12.5 16.5 MHz PLL system*1 (self oscillation 16.5MHz, multiplied x4,maximum internal operation 66MHz)Clock cycle time t C X1 ¾ 60.6 ns Clock frequency (2) f C 10 33 MHz Self oscillation (x2 frequency input) Clock frequency (3) f C X1 10 33 MHz External clockClock cycle time t C X1 40 100 ns Input clock pulse width PWH PWL X1 16 ¾ ns Input clock rise, fall time tCR tCF X1 ¾ 8n s ( t CR + tCF ) Internal operating clock frequency fCP 0.78*2 66 MHz CPU system fCPP 0.78*2 33 MHz Peripheral system fCPT 0.78*2 66 MHz External bus system Internal operating clock cycle time tCP 15.2 1280* 2 ns CPU system tCPP 30.3 1280* 2 ns Peripheral system tCPT 15.2 1280* 2 ns External bus system

• Clock timing measurement conditions:
• Warranted operating range
• External/internal clock setting range Notes :• When using the PLL, the external clock input should be around 16.5 MHz.
• Set PLL oscillator stabilization time > 300 ms.
• The internal clock gear setting should be within the values shown in (1) clock timing standards.

0.8 VCC

0.2 VCC

C = 50 pF Output pin 0 (MHz) 1.95 1.65 fCP / fCPP 66330.78 VCC (V) Internal clock Power supply Warranted operating temperature: (TA = 0 °C to +70 °C) fCPP is represented by the shaded area (MHz) 16.5 4 : 4 2 : 2 1 : 2 fCP , fCPT fCPP Internal clock CPU: Divided ratio for peripherals CPU system Peripheral, external bus systems

(2) Clock Output Timing (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C) *1 : tCYC represents the frequency of one clock cycle including the gear period. *2 : The values shown represent standards for · 1 gear period. For gear period settings of 1/2, 1/4, 1/8, use the following formula replacing n with the value 1/2, 1/4, 1/8 respectively. (1/2 · 1/n) · t CYC - 10 *3 : The values shown represent standards for · 1 gear period. (3) Reset and Hardware Standby Input Standards (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C) * : INIT input time (at power-on) FAR, Ceralock:f · 215 or greater recommended Crystal: f · 221 or greater recommended f : Power on fi X0/X1 period · 2 Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Cycle time t CYC MCLK, SYSCLK tCPT ¾ ns *1 MCLK ›fi MCLK fl SYSCLK ›fi SYSCLK fl tCHCL MCLK, SYSCLK 1/2 · tCYC - 31 / 2 · tCYC + 3n s * 2 MCLK flfi MCLK › SYSCLK flfi SYSCLK › tCLCL MCLK, SYSCLK 1/2 · tCYC - 31 / 2 · tCYC + 3n s * 3 Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Hardware standby input time tHSTL HST tCP · 5 ¾ ns INIT input time (power-on) tINTL INIT * ¾ ns INIT input time (other than power-on) tCP · 5 ¾ ns MCLK, SYSCLK VOH VOL VOH tCYC tCLCHtCHCL INIT 0.2 VCC tRSTL , tHSTL , tINTL HST

(4) Normal Bus Access Read/Write Operation (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C) * : T o extend bus time by automatic wait insertion or RDY input, add to this value (tCYC · number of extended cycles). Parameter Symbol Pin name Condition Value Unit Remarks Min Max CS0 to CS7 setup t CSLCH MCLK, SYSCLK, CS0 to CS7 ¾ 3 ¾ ns CS0 to CS7 hold t CSHCH 3t CYC /2 + 6n s Address setup t ASCH MCLK, SYSCLK, A24 to A00 3 ¾ ns Address hold t CHAX MCLK, SYSCLK, A24 to A00 3t CYC /2 + 6n s Valid address fi valid data input time tAVDV A24 to A00, D31 to D16 ¾ 3/2 · tCYC - 11 ns * WR0 to WR1 delay time tCHWL MCLK, SYSCLK, WR0 to WR1 ¾ 6n s tCHWH ¾ 6n s WR0 to WR1 minimum pulse width tWLWH WR0 to WR1 tCYC - 3 ¾ ns Data setupfi WRx › tDSWH WR0 to WR1, D31 to D16 tCYC ¾ ns WRx ›fi data hold time t WHDX 5 ¾ ns RD delay time tCHRL MCLK, SYSCLK, RD ¾ 6n s tCHRH ¾ 6n s RD flfi valid data input time tRLDV RD D31 to D16 ¾ tCYC - 10 ns * Data setup fi RD ›time tDSRH 10 ¾ ns RD ›fi data hold time t RHDX 0 ¾ ns RD minimum pulse width t RLRH RD tCYC - 3 ¾ ns AS setup t ASLCH MCLK, SYSCLK, AS 3 ¾ ns AS hold t ASHCH 3 ¾ ns

MCLK, SYSCLK AS LBA CS0 ~ CS7 VOH VOH VOH VOL VOL VOH VOH VOL VOH VOL VOL VOL A23 ~ A00 RD D31 ~ D16 WR0 ~ WR1 D31 ~ D16 VOH VOH VOL VOH VOH VOH VOL VOH VOL VOH VOL VOH tASCH tAVDV tRLDV tDSRH tRHDX tWLWH tCHWL tCHWH tCHAX tCHRH tDSWH tWHDX tASHCH tCYC tASLCH tCSHCH tCHRL tRLRH tCSLCH BA1 Write

(5) Ready Input Timing (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C) Parameter Symbol Pin name Condition Value Unit Remarks Min Max RDY setup time fi MCLK ›, SYSCLK › tRDYS MCLK, SYSCLK, RDY ¾ 10 ¾ ns MCLK ›, SYSCLK› RDY hold time tRDYH MCLK, SYSCLK, RDY ¾ 0 ¾ ns MCLK, SYSCLK VOHVOH VOL VOL VOL VOH VOL VOH VOH VOL VOH VOL tRDYH tRDYH RDY RDY tCYC tRDYStRDYStCHASL Wait applied Wait not applied

(6) Hold Timing (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C) Note: After a BRQ is accepted, a minimum of 1 cycle is required before BGRNT changes. Parameter Symbol Pin name Condition Value Unit Remarks Min Max BGRNT delay time tCHBGL MCLK, SYSCLK, BGRNT 31 3 . 5 n s tCHBGH 31 3 . 5 n s Pin floating fi BGRNT fltime tXHAL BGRNT tCYC - 10 t CYC + 10 ns BGRNT ›fi valid time t HAHV tCYC - 10 t CYC + 10 ns MCLK, SYSCLK VOH tCHBGL VOL VOH VOH VOH VOH tCHBGH BRQ BGRNT tCYC tHAHVtHXAL Pins High-Z

(7) UART Timing (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C) Notes: • These AC standards are for operation in CLK synchronized mode.

• tCYCP is the cycle time of the peripheral system clock. Parameter Symbol Pin name Condition Value Unit Remarks Min Max Serial clock cycle time t SCYC SC0 to SC2 Internal shift lock mode 8 tCYCP ¾ ns SCLK fl fi SOUT delay time t SLOV SC0 to SC2 SO0 to SO2 -80 80 ns Valid SIN fi SCLK › tIVSH SC0 to SC2 SI0 to SI2 100 ¾ ns SCLK › fi valid SIN hold time tSHIX SC0 to SC2 SI0 to SI2 60 ¾ ns Serial clock “H” pulse width tSHSL SC0 to SC2 External shift lock mode 4 tCYCP ¾ ns Serial clock “L” pulse width tSLSH SC0 to SC2 4 tCYCP ¾ ns SCLK fl fi SOUT delay time t SLOV SC0 to SC2 SO0 to SO2 ¾ 150 ns Valid SINfi SCLK › tIVSH SC0 to SC2 SI0 to SI2 60 ¾ ns SCLK ›fi valid SIN hold time tSHIX SC0 to SC2 SI0 to SI2 60 ¾ ns
• Internal Shift Clock Mode
• External Shift Clock Mode SC0, SC1 SO0, SO1 SI0, SI1 tSCYC tSLOV tIVSH tSHIX VOL VOH VOL VOH VOL VOH VOL VOH VOL SC0, SC1 SO0, SO1 SI0, SI1 tSLOV tSLSH tSHSL tIVSH tSHIX VOH VOL VOH VOL VOL VOL VOH VOL VOH VOL

(8) Timer Clock Input Timing (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C) Note: tCYCP is the cycle time of the peripheral system clock. (9) Trigger Input Timing (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C) Note: tCYCP is the cycle time of the peripheral system clock. Parameter Symbol Pin name Condition Value Unit Remarks Min Max Input pulse width tTIWH tTIWL TIN0 to TIN2 ¾ 2 tCYCP ¾ ns Parameter Symbol Pin name Condition Value Unit Remarks Min Max A/D startup trigger input time tATGX ATG ¾ 5 tCYCP ¾ ns tTIWH tTIWL TIN0 to TIN2 ATG tATGX, tINP, tPTG

(10) DMA Controller Timing (VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C) Parameter Symbol Pin name Condition Value Unit Remarks Min Max DREQ input pulse width tDRWH DREQ 0 to DRE2 5 tCYC ¾ ns DSTP input pulse width tDSWH DSTP 0 to DSTP2 5 tCYC ¾ ns DACK delay time tCLDL MCLK, SYSCLK, DACK0 to DACK2 ¾ 6 ns tCLDH ¾ 6 DEOP delay time tCLEL MCLK, SYSCLK, DEOP 0 to DEOP2 ¾ 6 ns tCLEH ¾ 6 IORD delay time tCLIRL MCLK, SYSCLK ¾ 6 ns tCLIRH ¾ 6 IOWR delay time tCLIWL MCLK, SYSCLK ¾ 6 ns tCLIWH ¾ 6

MCLK, SYSCLK DACK0 ~ DACK2 DEOP0 ~ DEOP2 DREQ0 ~ DREQ2 DSTP0 ~ DSTP2 IORD VOL VOH VOL VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH tCLEL tCLIRL tCLIWL tCLDL tCYC tCLEH tCLIRH tCLIWH tDRWH tDSWH tCLDH BA1 BA2 IOWR

1. A/D Converter Electrical Characteristics (VCC = AVCC = +3.0 V to +3.6 V, VSS = AVSS = 0 V, AVRH = +3.0 V to +3.6 V, TA = 0 °C to +70 °C) *1 : At VCC = AVCC = 3.0 V to 3.6 V , machine clock 33 MHz. *2 : Current in CPU stop mode with A/D converter not operating (VCC = AVCC = AVRH = 3.6 V) Notes : • The relative error increases as AVRH is reduced.

• The output impedance on the external analog input circuit should be used as follows. External circuit output impedance < 7 kW (provisional value) If the output impedance on the external circuit is too great, the analog voltage sampling time may be insufficient. Parameter Symbol Pin name Value Unit Min Typ Max Resolution ¾¾ ¾ 10 10 BIT Total error ¾¾ ¾ ¾ – 10 LSB Linear error ¾¾ ¾ ¾ – 3.0 LSB Differential linear error ¾¾ ¾ ¾ – 2.5 LSB Zero transition error V OT AN0 to AN3 - 10 + 0.5 + 10 LSB Full scale transition error V FST AN0 to AN3 AVRH - 10 AVRH - 1.5 AVRH + 10 LSB Conversion time ¾¾ 5.4 *1 ¾¾ m s Analog port input current I AIN AN0 to AN3 ¾ 0.1 10 mA Analog input voltage V AIN AN0 to AN3 AVss ¾ AVRH V Reference voltage ¾ AVRH AVss ¾ AV CC V Supply current IA AV CC ¾ 600 ¾m A IAH ¾¾ 10 *2 mA Reference voltage supply current IR AVRH ¾ 600 ¾m A IRH ¾¾ 10 *2 mA Inter-channel variation ¾ AN0 to AN3 ¾¾ 5L S B

Definition of A/D Converter Terms

• Resolution Indicates the ability of the A/D converter to discriminate analog variation
• Linear error Expresses the deviation between actual conversion characteristics and a straight line connecting the device’s zero transition point (00 0000 0000‹fi 00 0000 0001) and full scale transition point (11 1111 1110‹fi 11 1111 1111)
• Differential linear error Expresses the deviation of the logical value of input voltage required to create a variation of 1 LSB in output code. 3FF 3FE 3FD 004 003 002 001 AVRL AVRH {1 LSB · (N - 1) + VTO } VNT VFST VTO N - 1 AVRL AVRH N - 2 N - 2 N - 1 VNT V(N - 1)T [Linear Error] [Differential linear error] Digital output Digital output Actual variation (measured value) (measured value) Actual variation Theoretical values (measured value) Analog input Analog input Theoretical Actual variation (measured value) (measured value) Actual variation Linear error in digital output N = VNT - {1 LSB · (N - 1) + VOT }

1 LSB [LSB]

Differential linear error in digital output N = V (N + 1) T - VNT

1 LSB -1

1 LSB = VFST - VOT

1022 [V]

1 LSB” = AVRH - AVRL

1024 [V] VOT : Voltage at which the digital output transitions from (000) H to (001) H . VFST : Voltage at which the digital output transitions from (3FE) H to (3FF) H . VNT : Voltage at which the digital output transitions from (N-1) to N. [LSB] (theoretical value)

• T otal error Expresses the difference between actual and theoretical values as error, including zero transition error, full- scale error, and linearity error. 3FF 3FE 3FD 004 003 002 001 AVRL AVRH

1.5 LSB

0.5 LSB

{1 LSB · (N - 1) + 0.5 LSB [Total error] Digital output Actual variation (measured value) Actual variation theoretical value Analog input Total error in digital output N = VNT - {1 LSB” · (N - 1) + 0.5 LSB”}

1 LSB” [LSB]

VOT ” (theoretical value) = AVRL + 0.5 LSB” [V] VFST ” (theoretical value) = AVRH - 1.5 LSB” [V] VNT : Voltage at which digital output transitions from (N-1) to N.

(Continued) (1) Sample output voltage characteristics (TA = +25 °C) (2) Sample input voltage characteristics (TA = +25 °C) (3) Sample supply current characteristics Output voltage (V) Supply voltage (V) 0.4 0.3 0.2 0.1 0.0 3.0 3.2 3.4 3.6 Supply voltage (V) Output voltage (V) 3.6 3.4 3.2 3.0 2.8 3.0 3.2 3.4 3.6 Sample output H voltage (VOH ) characteristics Sample output L voltage (V OL ) characteristics 3.0 2.0 1.0 0.0 3.0 3.2 3.4 3.6 V IH VIL Input voltage (V) Supply voltage (V) 3.0 2.0 1.0 0.0 3.0 3.2 3.4 3.6 V IH VIL Supply voltage (V) Input voltage (V) Sample input H/L level characteristics (CMOS) Sample input H/L level characteristics (hysteresis) 200 150 100 3.0 3.2 3.4 3.6 Supply current (mA) Supply voltage (V) 200 150 100 0.0 02 5 7 0 T emperature ( °C) Supply current (mA) Sample supply current (ICC ) characteristics (TA = +25 °C, 66 MHz) Sample supply current (ICC ) characteristics (VCC = 3.3 V, 66 MHz)

(Continued) (4) Port resistance characteristics Sample sleep current (ICCS ) characteristics (TA = +25 °C, 33 MHz) 3.0 3.2 3.4 3.6 Supply current (mA) Supply voltage (V) Sample sleep current (ICCS ) characteristics (VCC = 3.3 V, 33 MHz) 02 5 7 0 Supply current (mA) T emperature ( °C) Sample A/D supply current (IA) characteristics (TA = +25 °C, 33 MHz) 500 400 300 200 3.0 3.2 3.4 3.6 Supply current (mA) Supply voltage (V) Sample A/D reference current (IR ) characteristics (TA = +25 °C, 33 MHz) 500 400 300 200 3.0 3.2 3.4 3.6 Supply current (mA) Supply voltage (V) 3.0 3.2 3.4 3.6 Supply voltage (V) Resistance (kW ) 3.0 3.2 3.4 3.6 Supply voltage (V) Resistance (kW ) Sample pull-up resistance characteristics (TA = +25 °C) Sample pull-down resistance characteristics (TA = +25 °C)

Part number Package Remarks MB91307BPFV 120-pin, Plastic LQFP (FPT-120P-M21) Lead-free package MB91V307RCR 135-pin, Ceramic PGA (PGA-135C-A02) For development tool use

120-pin, Plastic LQFP (FPT-120P-M21) Dimensions in mm (inches) C 2001 FUJITSU LIMITED F120033S-c-3-3 1 30 90 61 120 (.009±.002) M0.08(.003) INDEX .006–.001 +.002 –0.03 +0.05 0.145 "A" 0.08(.003) LEAD No. .059–.004 +.008 –0.10 +0.20 1.50 Details of "A" part 0~8° (Mounting height) 0.60±0.15 (.024±.006) 0.25(.010) (.004±.002) 0.10±0.05 (Stand off)

All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0212 ª FUJITSU LIMITED Printed in Japan