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Technical content

Features

 Dual-Input, Single-Output Load Switch  Input Supply Operating Range: - 4~10.5 V at VIN - 4~6.5 V at VBUS  Typical RON: - 95 mΩ at VIN=5 V - 70 mΩ at VBUS=5 V  Bi-Directional Switch for VIN and VBUS  Slew Rate Controlled: - 50 µs at VIN for < 4.7 µF COUT - 90 µs at VBUS for < 4.7 µF COUT  Maximum ISW: 2 A Per Channel  Break-Before-Make Transition  Under-Voltage Lockout (UVLO)  Over-Voltage Lockout (OVLO)  Thermal Shutdown  Logic CMOS IO Meets JESD76 Standard for GPIO Interface and Related Power Supply Requirements  ESD Protected: - Human Body Model: >3 kV - Charged Device Model: >1.5 kV - IEC 61000-4-2 Air Discharge: >15 kV - IEC61000-4-2 Contact Discharge: >8 kV

Applications

 Input Power Selection Block Supporting USB and Wireless Charging  Smartphone / Tablet PC

Description

The FPF3040 is a 20 V-rated Dual-Input Single-Output (DISO) load switch consisting of two channels of slew- rate-controlled, low-on-resistance, N-channel MOSFET switches with protection features. The slew-rate- controlled turn-on characteristic prevents inrush current and the resulting excessive voltage droop on the input power rails. The input voltage range operates from 4 V to 6.5 V at V BUS and from 4 V to 10.5 V at V IN to align with the needs of low-voltage portable device power rails. VIN and V BUS have the over-voltage protection functionality of typical 12 V and 7.5 V, respectively, to avoid unwanted damage to system. VIN and V BUS bi-directional switching allows reverse current from V OUT to V IN or V BUS for On-The-Go, (OTG) Mode. The switching is controlled by logic input EN and VIN_SEL is capable of interfacing directly with low-voltage control signal General-Purpose Input / Output (GPIO). FPF3040 is available in 1.8 mm x 2.0 mm Wafer-Level Chip-Scale Package (WLCSP), 16-bump, 0.4 mm pitch.

Ordering Information

Mark Channel Typical RON per Channel at 5VIN Rise Time (tR) Package FPF3040UCX QY DISO 95 mΩ for VIN 50 µs for V IN 1.8 mm x 2.0 mm Wafer-Level Chip-Scale Package (WLCSP), 16-Bump, 0.4 mm Pitch 70 mΩ for VBUS 90 µs for V BUS

Figure 3. Pin Assignment (Top View) Figure 4. Pin Assignment (Bottom View) A1, B1, C1 V BUS Input / Output VBUS at USB: Power input / output. bi-directional switch when VIN_SEL = LOW. A4, B4, C4 V IN Input / Output VIN Supply Input: Power input / output. bi-directional switch when VIN_SEL = HIGH. A2, A3, B3, C3 V OUT Input / Output Switch Output: Power input / output. EN can power internal circuit when VIN and VBUS are absent. 1 MΩ pull-down resistor is included. and status output. This signal is ignored during EN=LOW. HIGH means to switch VIN to VOUT. LOW means to switch VBUS to VOUT. HIGH means VIN is used for VOUT. LOW means VBUS is used for VOUT. Default Supply Selector during EN=LOW: Input. Floating means VBUS connects to VOUT. LOW means VIN connects to VOUT. Other Supply Input Status: Open-drain output. HI-Z means both VIN and VBUS are valid. LOW means the other power source is not valid.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF3040 • Rev. 2.4.0 4 FPF3040 — IntelliMAX™ 20V-Rated Dual Input Single Output Power-Source-Selector Switch Truth Table EN V IN>UVLO V BUS>UVLO V IN_SEL DF_IN Other_V IN_AVA V OUT Comment HIGH X X LOW X HI-Z if VIN & VBUS >UVLO LOW if VIN or VBUS <UVLO VBUS VOUT is selected by VIN_SEL Bi-directional channel HIGH X X HIGH X HI-Z if VIN & VBUS >UVLO LOW if VIN or VBUS <UVLO VIN LOW YES NO HIGH X LOW V IN Automatic selection to valid input VIN_SEL is output. LOW NO YES LOW X LOW V BUS LOW YES YES LOW Floating HIGH V BUS VOUT is selected by DF_IN VIN_SEL is output. LOW YES YES HIGH LOW HIGH V IN LOW NO NO X X LOW Floating OFF Notes: 1. Internal pull-down at EN. 2. 1 µA pull-up current source at DF_IN. Absolute Maximum Ratings Stresses exceeding the Absolute Maximum Ratings may dam age the device. The device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameters Min. Max. Unit VPIN VIN, VBUS to GND Continuous -1.4 20 V Pulsed, 100 ms Maximum Non-Repetitive -2.0 VOUT to GND(3) -0.3 16.0 EN, DF_IN, VIN_SEL, Other_VIN_AVA to GND -0.3 6.0 ISW Maximum Continuous Switch Current per Channel 2 A tPD Total Power Dissipation at T A=25°C 2.25 W TJ Operating Junction Temperature -40 +150 °C TSTG Storage Junction Temperature -65 +150 °C JA Thermal Resistance, Junction-to-Ambient (1in. Square Pad of 2 oz. Copper) 55 (4) °C/W ESD Electrostatic Discharge Capability Human Body Model, JESD22-A114 3 kV Charged Device Model, JESD22-C101 1.5 IEC61000-4-2 System Level(5) Air Discharge (VIN, VBUS to GND) 15 Contact Discharge (VIN, VBUS to GND) 8 Notes: 3. If external voltage of more than 10.5 V is applied to VOUT, the slew rate should be less than 1 V/ms from 10.5 V. 4. Measured using 2S2P JEDEC standard PCB. 5. System level ESD can be guaranteed by design. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameters Min. Max. Unit VPIN VIN 4.0 10.5 V VBUS 4.0 6.5 TA Ambient Operating Temperature -40 +85 °C

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF3040 • Rev. 2.4.0 5 FPF3040 — IntelliMAX™ 20V-Rated Dual Input Single Output Power-Source-Selector Switch

Electrical Characteristics

VIN=4 to 10.5 V, V BUS=4 to 6.5 V, T A=-40 to 85°C unless otherwise not ed. Typical values are at V IN=VBUS=5 V, EN=HIGH and TA=25°C. Symbol Parameters Condition Min. Typ. Max. Unit Basic Operation VIN Input Voltage 4.0 10.5 V VBUS 4.0 6.5 V IQ Quiescent Current IOUT=0 mA, EN=HIGH, VIN or VBUS=5 V 55 120 μA IOUT=0 mA, EN=5 V, VIN and VBUS=GND 33 70 μA RON On Resistance for VIN VIN=8 V, IOUT=200 mA, TA=25°C 95 mΩ VIN=5 V, IOUT=200 mA, TA=25°C 95 150 VIN=5 V, IOUT=200 mA, TA=25°C to 85°C(6) 200 On Resistance for VBUS VBUS=6 V, IOUT=200 mA, TA=25°C 70 mΩ VBUS=5 V, IOUT=200 mA, TA=25°C 70 100 VBUS=5 V, IOUT=200 mA, TA=25°C to 85°C(6) 140 VIH Input Logic High Voltage V IN=4 V~10.5 V, VBUS=4 V ~ 6.5 V 1.15 V VIL Input Logic Low Voltage V IN=4 V~10.5 V, VBUS=4 V ~ 6.5 V 0.52 V REN_PD Pull-Down Resistance at EN 707 1000 1360 k Ω Protection VUVLO Under-Voltage Lockout Threshold VIN or VBUS Rising 3.05 3.50 4.00 V VIN or VBUS Falling 2.55 3.00 3.55 V VUVHYS Under-Voltage Lockout Hysteresis 0.5 V VOVLO Over-Voltage Lockout Threshold VIN Rising Threshold 10.85 12.00 13.45 V VIN Falling Threshold 11.5 V VBUS Rising Threshold 6.52 7.50 8.32 V VBUS Falling Threshold 7 V VOVHYS Over-Voltage Lockout Hysteresis VIN 0.5 V VBUS 0.5 V TSDN Thermal Shutdown Threshold 150 °C TSDNHYS Thermal Shutdown Hysteresis 20 °C Reverse Current Blocking IRCB VIN or VBUS Current During RCB V OUT=8 V, VIN or VBUS=GND 30 μA Dynamic Characteristics tR VOUT Rise Time, VBUS (6,7) VIN=VBUS=5 V, RL=150 Ω, CL=4.7 μF, TA=25°C μs VOUT Rise Time, VIN (6,7) 50 tF V OUT Fall Time(6,7) 1.4 ms tTRAN Transition Delay (6,7) 50 100 ms tSD Selection Delay (6,7) 50 μs Notes: 6. This parameter is guaranteed by design and characterization; not production tested. 7. t SD/tTRAN/tR/tF are defined in Figure 5.

Figure 5. Transition Delay (V IN=VBUS=5 V)

regardless of DF_IN. If VIN_SEL is LOW, VBUS is selected. If VIN_SEL is HIGH, VIN is selected. Table 1. Input Power Selection by VIN_SEL selected. If DF_IN is HIGH or floating, V BUS is selected. Table 2. Input Power Selection by DF_IN VIN_SEL shows high. If V BUS is used, VIN_SEL shows LOW. supported if internal control circuitry is powered by EN. LOW and an unselected channel. without an additional power path, such as a MOSFET. Figure 30. Block Diagram of Input Power Selector for Wireless Charging System

Figure 31. 1.8 mm x 2.0 mm Wafer-Level Chip-Scale Package (WLCSP), 16-Bump, 0.4 mm Pitch warranty therein, which covers Fairchild products. http://www.fairchildsemi.com/packaging/.

0.005 CAB

0.05 C E

A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. ±39 MICRONS (547-625 MICRONS). G. DRAWING FILNAME: MKT-UC016AArev2.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF3040 • Rev. 2.4.0 12 FPF3040 — IntelliMAX™ 20V-Rated Dual Input Single Output Power-Source-Selector Switch