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Technical content

Features

  • Over−voltage Protection Up to ±28V
  • Programmable Over−voltage Lockout (OVLO) ♦ Externally Adjustable via OVLO Pin ♦ Default OVLO Level without Additional Components
  • Programmable Under−voltage Lockout (UVLO) ♦ Externally Adjustable via UVLO Pin
  • Active−high Enable Pin (EN) for Device
  • Super−fast OVLO Response Time: Typical 150 ns
  • Negative V oltage Blocking
  • Short Circuit Protection and Auto−restart
  • Selectable Gate Driver V oltage
  • USB OTG Support Mode
  • Open−Drain Output Indicators ♦ OVFLGB for Over V oltage Stress ♦ UVFLAG for Under V oltage Lockout
  • Robust ESD Performance ♦ 2 kV Human Body Model (HBM) ♦ 1 kV Charged Device Model (CDM) Typical Applications
  • Mobile Phones
  • PDAs
  • Notebooks
  • Desktops www.onsemi.com MARKING DIAGRAM 6B = Specific Device Code KK = 2 −Digits Lot Run Traceability Code _ = Pin 1 Identifier XY = 2 −Digit Date Code Z = Assembly Pant Code See detailed ordering and shipping information on page 7 of this data sheet.

ORDERING INFORMATION

X2QFN12 1.6x1.6, 0.4P CASE 722AG 6BKK _XYZ PIN CONNECTIONS 12 11 10 9 3456 OVLO GND UVFLAG OVFLGB UVLO TRCB EN GT_CON GT1 IN OUT GT2 (Top View)

www.onsemi.com PIN FUNCTION DESCRIPTION Pin No. Name Description

1 GND Ground

2 OVLO OVLO Input: Over Voltage Lockout Adjustment Input

3 IN Power Input: External FET Input and Device Supply

4 GT1 Gate 1 Output:

5 GT2 Gate 2 Output:

6 OUT Power Output: External FET Output and Device Supply(More Description)

7 UVFLAG UVLO Flag Output: Open−drain output, turn ON the internal MOS to pull down this pin to indicate no Under−Voltage condition on IN

8 OVFLGB OVP Flag Output: Open−drain output, turn ON the internal MOS to pull down this pin to indicate

Over−Voltage condition on IN

9 EN Enable Input: Active HIGH with internal 500 k/C0087 pull down resistor

10 GT_CON Gate Voltage Control Input: VGS select Pin 0: Vgs = 12 V; 1/floating: Vgs = 6V with internal 500 k/C0087 pull up resistor

11 UVLO UVLO Input: Under Voltage Lockout Adjustment Input

12 TRCB True RCB Enable Input: 0: no TRCB; 1/floating: Block Reverse Current Entirely with internal 500 k/C0087 pull up resistor MAXIMUM RATINGS Symbol Parameter Value Unit VIN Input Voltage Range (Note 1) −28 to +28 V VOUT Output Voltage Range −0.3 to +28 V VI/O Standard I/O Range (UVFLAG, OVFLGB, TRCB, GT_CON) −0.3 to +6 V VHVIO HV I/O Range (OVLO, UVLO, EN) −0.3 to +28 V TJ(max) Maximum Junction Temperature 150 °C TSTG Storage Temperature Range −65 to 150 °C ESDHBM ESD Capability, Human Body Model (Note 2) ±2 kV ESDCDM ESD Capability, Charged Device Model (Note 2) ±1 kV TSLD Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions (Note 3) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101) Latch−up Current Maximum Rating: /C0118150 mA per JEDEC standard: JESD78 3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D THERMAL CHARACTERISTICS Symbol Rating Value Unit R/C0113JA Thermal Characteristics, X2QFN12 (Note 4) Thermal Resistance, Junction−to−Air (Note 5) 139.3 °C/W 4. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 5. Values based on 2S2P JEDEC std. PCB.

www.onsemi.com RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit Vin Supply Voltage on VIN (GT_CON floating) 4.0 22 V Supply Voltage on VIN (GT_CON grounded) 16 VOVLO, UVLO, EN, TRCB, GT_CON, OVFLAG, UVFLAG I/O pins 0 5.5 V Cin IN Capacitor 1 − /C0109F Cout OUT Capacitor 1 − /C0109F TA Ambient Temperature −40 85 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = 2.9 to 23 V, CIN = 0.1 /C0109F, COUT = 0.1 /C0109F, TA = −40 to 85°C; For typical values VIN = 5.0 V, IIN ≤ 3 A, CIN = 0.1 /C0109F, TA = 25°C, for min/max values TA = −40°C to 85°C; unless otherwise noted. (Note 6) Symbol Parameter Test Condition Min Typ Max Unit LEAKAGE AND QUIESCENT CURRENTS IQ Input Quiescent Current on VIN VIN = 5 V, VOVLO = 1 V, TRCB = 0, VOUT floating − 160 − /C0109A VIN = 20 V, VOVLO = 1 V, TRCB = 0, VOUT floating − 400 − IOFF Device turned off current VIN = 5 V, VEN = 0 V, VOUT = 0 V − 120 − /C0109A IIN_Q Supply Current during Over Voltage VIN = 20 V, VOVLO = 1.8 V, VOUT = 0 V − 180 − /C0109A IOVLO OVLO Input Leakage Current VOVLO = VOVLO_TH −100 − 100 nA OVER VOLTAGE AND UNDER VOLTAGE LOCKOUT VDEF_OVLO Default Over−Voltage Trip Level VIN rising, TA = −40 to 85°C 5.9 6.1 6.3 V VDEF_UVLO Default Under−Voltage Trip Level VIN falling, TA = −40 to 85°C 1.8 2.0 2.2 V VOVLO_TH OVLO set threshold VOVLO rising from 1.1 V to 1.3 V, the OVLO voltage to switch off power FET 1.15 1.19 1.23 V VHYS_OVLO OVLO threshold hysteresis − 2 − % VUVLO_TH UVLO set threshold VUVLO falling from 1.3 V to 1.1 V, the UVLO voltage to switch off power FET 1.15 1.17 1.23 V VHYS_UVLO UVLO threshold hysteresis − 2 − % VOV_RNG Adjustable OVLO range VOVLO > 0.5 V 4 − 22 V TRCB (IN TRCB MODE ONLY, I.E. VTRCB = HIGH/FLOAT) VDROP TRCB trigger level VIN = 5 V, ILOAD = 100 mA − 35 − mV tREL TRCB release time VIN = 5 V − 1 − ms I/O THRESHOLDS VIH_OVLO VIL_OVLO OVLO Input Threshold Voltage Voltage Increasing, Logic High Voltage Decreasing, Logic Low High Low 0.3 0.15 V V GATE DRIVER VGS Turn on status gate positive voltage over OUT (Note 8) VIN = VOUT = 5 V, VGT_CON = 0 V − 12 − V VIN = VOUT = 5 V, VGT_CON = 1.8 V − 6 − IGS Turn on status gate positive current VTRCB = 0 V, VIN = VOUT = 5 V, VGT_CON = 1.8 V, ILOAD = 10 mA − − 10 /C0109A OVP turn off gate current (Note 9) VIN = 5 V, VGT_CON = 1.8 V, VOVLO from 1.1 V to 1.3 V − − 3 A

www.onsemi.com ELECTRICAL CHARACTERISTICS (VIN = 2.9 to 23 V, CIN = 0.1 /C0109F, COUT = 0.1 /C0109F, TA = −40 to 85°C; For typical values VIN = 5.0 V, IIN ≤ 3 A, CIN = 0.1 /C0109F, TA = 25°C, for min/max values TA = −40°C to 85°C; unless otherwise noted. (Note 6) (continued) Symbol UnitMaxTypMinTest ConditionParameter I/O AND LOGIC CONTROL VIH I/O Logic High Voltage Pins: EN, TRCB, GT_CON 1.2 − − V VIL I/O Logic Low Voltage − − 0.5 V VOL Output Low Voltage of Open−Drain pins VI/O = 3.3 V, ISINK = 1 mA, Pins: UVFLAG, OVFLGB − − 0.4 V ILKG Leakage Current of I/O pins VI/O = 3.3 V, Logic de−asserted, Pins: UVFLAG, OVFLGB, GT_CON −0.5 − 0.5 /C0109A TIMING tSW_DEB De−bounce Time of Power FET turned on Time from 2.5 V < VIN < VIN_OVLO to VOUT = 0.1 x VIN − 15 − ms tOTG_DEB De−bounce Time of OTG turned on Time from VOUT > 2.8 V to VIN = 0.1 x VOUT − 15 − ms tUV_DEB De−bounce Time of UVFLAG flag Time from VIN > VIN_UVLO to UVFLAG < 0.4 V − 130 − /C0109s tOV_DEB De−bounce Time of OVFLGB flag Time from VIN < VIN_OVLO to OVFLGB > 1.8 V − 1 − ms tR Switch Turn−On rising Time (Note 9) VIN = 5 V, RL = 100 /C0087, CL = 22/C0032/C0109F, VOUT from 0.1 x VIN to 0.9 x VIN − 2 − ms tOFF Switch Turn−Off Time (Note 8, 9) RL = 10 /C0087, CL = 0 μF, time from VIN > VOVLO to VOUT = 0.9 x VIN Internal OVP level External OVP level (Note 10) 100 ns ns Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Performance guara nteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 7. Refer to the APPLICATION INFORMATION section. 8. Based on the recommended MOSFET devices. 9. Values based on design and/or characterization 10.Depends on the capacitance on OVLO pin.

www.onsemi.com FUNCTION DESCRIPTION General FPF2260A is an OVP controller to drive external N−type MOSFETs. The device can protect next stage system which is optimized to lower voltage working condition, especially with ultra −high charging current. The device includes multi−functions including OVP, Advanced TRCB, and Negative Stress protection. Power MOSFET Driver The FPF2260A integrates charge pump driver to control external N−type MOSFET pair. The drive voltage can be configured by GPIO for different MOSFET. The drive voltage for MOSFET can be configured by GPIO pin GT_CON. V GS could be set to 6 V by pull GT_CON to high or floating. Or, VGS will be set to 12 V by pulling GT_CON to ground. True Reverse Current Blocking and USB OTG The FPF2260A support advanced TRCB mode by pulling TRCB pin to high or floating it. In the advanced TRCB mode, no reverse current will be seen from OUT to IN through the external MOSFETs if V OUT – VIN > 30 mV . When advanced TRCB mode is active, OTG operation is not supported. If OTG is needed, TRCB pin needs to be pulled down to ground. Enable Control The GPIO EN is an active high control pin. When the voltage is pulled low, FPF2260A will disable the external MOSFETs by connecting GT1 to IN and GT2 to OUT. When EN is logic high, FPF2260A will close external MOSFET if there are no over stressed condition. Under Voltage Lockout FPF2260A will turn the FETs off when the voltage on IN is lower than the UVLO threshold VIN_UVLO. Whenever IN voltage ramps up to higher than the threshold, the power FET will be turned on automatically after tDEB de−bounce time if there is no other over stressed condition. The external resistor ladder can be decided according to the following equation: VIN_UVLO /C0043VUVLO_TH /C0032[1 /C0041R1 /C0324(R2 /C0041R3)] (eq. 1) where R1, R2 and R3 are the resistors in figure 1. Over Voltage Lockout The power FET will be turned off whenever IN voltage higher than VIN_OVLO. The value of VIN_OVLO can be set by external resistor ladder or just be default value VIN_OVLO. When VOVLO ≤ 0.3 V , VOVLO is decided by default value. When VOVLO > 0.3 V , the power switch will be turned off once VOVLO > VOVLO_TH. The external resistor ladder can be decided according to the following equation: VIN_OVLO /C0043VOVLO_TH /C0032[1 /C0041(R1 /C0041R2) /C0324R3] (eq. 2) where R1, R2 and R3 are the resistors in figure 1. Negative Voltage Protection FPF2260 support negative voltage protection to help system avoid unexpected negative stress. The gate of first external power FET, GT1, will be pulled down with the voltage on IN when it is negative. This behavior can keep the external FET at off status till −28 V . APPLICATIONS INFORMATION Input Decoupling (Cin) A ceramic or tantalum at least 0.1 /C0109F capacitor is recommended and should be put before and close the connection point of MOSFET and FPF2260A IN. Higher capacitance and lower ESR will improve the overall line and load transient response. Output Decoupling (Cout) The FPF2260A is a stable component and does not require a minimum Equivalent Series Resistance (ESR) for the output capacitor. The minimum output decoupling value is 0.1 /C0109F and can be augmented to fulfill stringent load transient requirements. Hints for PCB Layout The external MOSFET is an important part to FPF2260A. The connection of gate should be as short as possible to avoid parasitic resistance and inductance for better OVP performance. Part Number Marking Package Shipping† FPF2260ATMX 6B X2QFN12 5000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

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