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Technical content
Features
DISO Load Sw itches Input Supply Operating Range: 1.5 V ~ 5.5 V RON 50 mΩ at V IN=3.3 V Per Channel (Typical) True Reverse-Current Blocking (T RCB) Fixed Slew Rate Controlled 130 µs for < 1 µF COUT ISW: 1.5 A Per Channel ( Max imum) Quick Discharge Feature on FPF1321 Logic CMOS IO Meets JESD76 Standard for GPIO Interface and R elated Pow er Supply Requirements ESD Protected: - Human Body Model: >6 kV - Charged Device Model: >1.5 kV - IEC 61000-4-2 Air Discharge: >15 kV - IEC 61000-4-2 Contact Discharge: >8 kV
Applications
Smart phones / Tablet PCs Portable Devices Near Field Communication ( NFC) Capable S IM Card Pow er Supply
Description
The FPF 1320/21 is a Dual-Input Single-O utput ( DISO) load sw itch consisting of tw o sets of s lew -r ate controlled, low on-resistance, P- channel MOSFET sw itches and integrated analog features. The slew -rate- controlled turn- on character istic prevents inrush current and the resulting excessive voltage droop on the pow er rails. The input voltage range operates from 1.5 V to
5.5 V to align w it h the requirements of low -voltage
portable device pow er rails . FPF1320/21 perfor ms seamless pow er -source transitions betw een tw o input pow er rails using the SEL pin w ith advanced break - before-make operation. FPF1320/21 has a TRCB function to bloc k unw anted reverse current from output to input during ON/OFF states. The sw itch is controlled by logic inputs of the S EL and EN pins, w hich are capable of interfacing directly w ith low-voltage control signals (GPIO). FPF1321 has 65 Ω on -chip load resistor for output quick discharge w hen EN is LOW. FPF1320/21 is available in 1.0 mm x 1.5 mm WLCSP, 6-bu mp, w ith 0.5 mm pitch. FPF1 321B is available in 1.0 mm x 1. 5 mm WLCSP, 6 -bump, 0.5 mm pitch w it h bac kside laminate.
Ordering Information
Channel (Typ.) at 3.3 VIN Revers e Current Blocking Output Discha rge Rise Time (tR) Package FPF1320UCX QS DISO 50 mΩ Yes NA 130 µs 1.0 mm X 1.5 mm Wafer-Level Chip- Scale Package (WLCSP) 6-Bumps, 0.5 mm Pitc h FPF1321UCX QT DISO 50 mΩ Yes 65 Ω 130 µs FPF1321BUCX QT D ISO 50 mΩ Yes 65 Ω 130 µs 1.0 mm X 1.5 mm Wafer-Level Chip- Scale Package (WLCSP ) 6-Bumps, 0.5 mm Pitc h w ith Backside Laminate
Figure 4. Pin Assignments A1 EN Enable input. Active HIGH. There is an internal pull-dow n resistor at the EN pin. A2 VINA Supply Input. Input to the pow er sw itch A. C2 VINB Supply Input. Input to pow er sw itch B. Table 1. Truth Table
w ww.onsemi.com FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch Absolute Maximum Ratings Stresses exceeding the A bsolute Max i mu m Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameters Min. Max. Unit VIN VINA, VINB, VSEL, VEN, VOUT to GND -0.3 6 V ISW Maximum Continuous Sw itch Current per Channel 1.5 A PD Total Pow er Dissipation at TA=25°C 1.2 W TSTG Operating and Storage Junction Temperature -65 150 °C ΘJA Thermal Resistance, Junction- to-Ambient (1 in.2 Pad of 2-oz. Copper) 85(1) °C/W 110(2) ESD Electrostatic Discharge Capability Human Body Model, JESD22-A114 6.0 kV Charged Device Model, JESD22-C10 1 1.5 Air Discharge ( VINA, VINB to GND), IEC61000-4-2 System Level 15.0 Contact Discharge ( VINA, VINB to GND), IEC61000-4-2 System Level 8.0 Notes: 1. Measured using 2S2P JEDEC std. PCB. 2. Measured using 2S2P JEDEC PCB cold-plate method. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet spec ifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameters Min. Max. Unit VIN Input Voltage on VINA, VINB 1.5 5.5 V TA Ambient Operating Temperature -40 85 °C
www.onsemi.com FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Electrical Characteristics
Symbol Parameter s Condition Min. Typ. Max. Unit Basic Operation VINA, VINB Input Voltage 1.5 5.5 V ISD Shutdow n Current SEL=HIGH or LOW, EN=GND, VOUT=GND, VINA=VINB=5.5 V 5 µA IQ Quiescent Current IOUT=0mA, SEL=HIGH or LOW, EN=HIGH, VINA=VINB=5.5 V 12 22 μA RON On-Resistance VINA=VINB=5.5 V, IOUT=200 mA , TA=25°C 42 60 mΩ VINA=VINB=3.3 V, IOUT=200 mA , TA=25°C 50 VINA=VINB=1.8 V, IOUT=200 mA, TA=25°C to 85°C 80 VINA=VINB=1.5 V, IOUT=200 mA, TA=25°C 170 VIH SEL, EN Input Logic High Voltage VINA, VINB=1.5 V – 5.5 V 1.15 V VIL SEL, EN Input Logic Low Voltage VINA, VINB=1.8 V – 5.5 V 0.65 V SEL, EN Input Logic Low Voltage VINA, VINB=1.5 V – 1.8 V 0.60 VDROOP_OUT Output Voltage Droop w hile Channel Sw itching from Higher Input Voltage Low er Input Voltage(3) VINA=3.3 V, VINB=5 V, Sw itching from VINA VINB, RL=150 Ω, COUT=1 µF 100 mV ISEL/IEN Input Leakage at SEL and EN Pin 1.2 μA RSEL_PD/REN_PD Pull-Dow n Resistance at SEL or EN Pin 7 MΩ RPD Output Pull-Dow n Resistance SEL=HIGH or LOW, EN=GND, IFORCE=20 mA , TA=25°C, FPF1321 65 Ω True Reverse Current Blocking VT_RCB RCB Protection Trip Point VOUT - VINA or VINB 45 mV VR_RCB RCB Protection Release Trip Point VINA or VINB -VOUT 25 mV IRCB VINA or VINB Current During RCB VOUT=5.5 V, VINA or VINB=Short to GND 9 15 μA tRCB_ON RCB Response Time w hen Device is ON (3) VINA or VINB=5 V, VOUTVINA,B=100 mV 5 µs Continued on the following page…
www.onsemi.com FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch Electrical Characteristics (Continued) Symbol Parameter s Condition Min. Typ. Max. Unit Dynamic Characteristics tDON Turn-On Delay(4) VINA or VINB=3.3 V, RL=150 Ω, CL=1 µF, TA=25°C, SEL: HIGH, EN: LOW HIGH 120 μs tR VOUT Rise Time(4) 130 μs tON Turn-On Time(6) 250 μs tDOFF Turn-Off Delay(4) VINA or VINB=3.3 V, RL=150 Ω, CL=1 µF, TA=25°C, SEL: HIGH, EN: HIGH LOW 15 μs tF VOUT Fall Time(4) 320 μs tOFF Turn-O ff T im e(7) 335 μs tDOFF Turn-Off Delay(4,5) VINA or VINB =3.3 V, RL=150 Ω, CL=1 µF, TA=25°C, SEL: HIGH, EN: HIGH LOW, Output Discharge Mode, FPF1321 6 μs tF VOUT Fall Time(4,5) 110 μs tOFF Turn-O ff T im e(5,7) 116 μs tTRANR Transition Time LOW HIGH(4) VINA=3.3 V, VINB=5 V, Sw itching from VINA VINB, SEL: LOW HIGH, EN: HIGH, RL=150 Ω, CL=1 µF, TA=25°C 3 μs tSLH Sw itch-Over Rising Delay(4) 1 μs tTRANF Transition Time HIGH LOW(4) VINA=3.3 V, VINB=5 V, Sw itching from VINB VINA, SEL: HIGH LOW, EN: HIGH, RL=150 Ω, C=1 µF, TA=25°C 45 μs tSHL Sw itch-Over Falling Delay(4) 5 μs N otes: 3. This parameter is guaranteed by design and characterization; not production tested. 4. tDON/tDOFF/tR/tF/tTRANR/tTRANF/tSLH/tSHL are defined in Figure 5. 5. FPF1321 output discharge is enabled during off. 6. tON=tR + tDON. 7. tOFF=tF + tDOFF.
Figure 5. Dynamic Behavior Timing Diagram
www.onsemi.com FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch Operation and Application Description The FPF1320 and FPF1321 are dual-input single-output pow er multiplexer sw itches w ith controlled turn- on and seamless pow er source transition. The core is a 50 mΩ P-channel MOSFET and contr oller capable of functioning over a w ide input operating range of 1.5 V to 5.5 V per channel . The E N and SEL pins are active- HIGH, GPIO/CMOS -compatible input . They control the state of the sw itch and input pow er source selecti on, respectively. TRCB functionality blocks unw anted reverse current during both ON and OFF states w hen higher VOUT than VINA or VINB is applied. FPF1321 has a 65 Ω output discharge path during off. Input Capacitor To limit the voltage drop on the input supply caused by transient inrush current w hen the sw itch turns on into a discharged load capac itor ; a capacitor must be placed betw een the VINA or VINB pins to the GND pin. At least 1 µF ceramic capacitor, C IN, placed c lose to the pins , is usually sufficient. H igher-value C IN can be used to reduce more the voltage drop. Inrush Current Inrush current occurs w hen the dev ice is turned on. Inrush current is depend ent on output capac itance and slew rate control capability, as expressed by: LOAD R INITIALIN OUTINRUSH It VVCI +−×= (1) w here: COUT: Output capacitance; tR: Slew rate or rise time at VOUT; VIN: Input voltage, VINA or VINB; VINITIAL: Initial voltage at COUT, usually GND; and ILOAD: Load current. Higher inrush current causes higher input voltage drop, depending on the distributed input resistance and input capacitance. High inrush current can cause problems. FPF1320/1 has a 130 µs of slew rate capability under
3.3 VIN at 1 µF of C OUT and 150 Ω o f RL so inrush
current and input voltage drop can be minimized. Power Source Selection Input pow er source selection can be controlled by the SEL pin. When SEL is LOW, output is pow ered from V INA w hile SEL is HIGH, V INB is pow ering output. The SEL signal is ignored during device OFF. Output Voltage Drop during Transition Output voltage drop usually occurs during input pow er source transition per iod from low voltage to high voltage. The drop is highly dependent on output capacitance and load current . FPF1320/1 adopts an advanced break -before- m ake control, w hich can result in minimized output voltage drop during the transition time. Output Capacitor Capacitor C OUT of at least 1 µF is highly recommended betw een the VOUT and GND pins to achieve minimized output voltage drop during input pow er source transition. This capacitor also prevents parasitic board inductance. True Re verse-Current Blocking The true r everse-current blocking feature protects the input source against current flow from output to input regardless of w hether the load sw itch is on or off. Board Layout For best performance, all traces should be as short as possible. To be most effective, the input and output capacitors should be placed close to the device to minimize t he effect that parasitic trace inductance on nor mal and short-circuit operation. W ide traces or large copper planes for pow er pins ( V INA, V INB, V OUT and GND) minimize the parasitic electrical effects and the thermal impedance.
Figure 34. 6-Ball, 1.0 x 1.5 mm, Wafer-Level Chip -Scale Package (WLCSP) conditions, specifically the warranty therein, which covers ON Semi conductor products.
0.05 C E
A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. ±43 MICRONS (539-625 MICRONS). G. DRAWING FILNAME: MKT-UC006AFrev2.
0.005 C A B
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