FPD87392AXA TI1 | Alldatasheet

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www.ti.com SNOSA80C –JUNE 2003–REVISED APRIL 2013 FPD87392AXA+3.3VTFT-LCDTimingControllerwithDualLVDSInputs/DualRSDS™ OutputsforTFT-LCDMonitorandNotebook(SXGA/SXGA+/UXGA) Check forSamples: FPD87392AXA 1FEATURES DESCRIPTION The FPD87392AXA Panel Timing Controlleris an 23• InputFrequency Range from 30 MHz to85 MHz integratedFPD-Link + RSDS ™ + TFT-LCD Timing• Support DisplayResolutionsSXGA Controller.The logicarchitectureis implemented(1280x1024),SXGA+ (1400x1050)and UXGA using standard and default timing controller (1600x1200) functionalitybased on an Embedded Gate Array.The deviceis reconfigurableto the needs of a specific• Embedded Gate ArrayforCustom Panel applicationby providinguser-definedspecificationsorTiming customersuppliedVHDL/Verilogcode.• RSDS ™ (Reduced Swing Differential Signaling)Column DriverBus forLow Power The FPD87392AXA is a timing controllerthat combines an LVDS dualpixelinputinterfacewithTI'sand Reduced EMI Reduced Swing DifferentialSignaling(RSDS ™ )• DrivesRSDS ™ Column Driverup to170 Mb/s outputcolumn driverinterfaceforSXGA, SXGA+ andwithan 85 MHz Clock UXGA resolutions.Itresideson the TFT-LCD panel

  • 6 or 8 BitLVDS Dual PixelInputInterface and providesthe data bufferingand controlsignal (FPD-Link) generation.The RSDS ™ data path to the column drivercontributestowardloweringradiatedEMI and• Virtual8-BitColorDepth inFRC Mode reduced system dynamic power consumption.The• FlexibleRSDS ™ Data Output Mapping for RSDS ™ dual12 pairdifferentialbus conveys up toBottom or Top Mount 24-bitcolordata for SXGA/SXGA+/UXGA panels
  • Supports 1 and 2 LineInversionMode forRVS when usingVESA 60Hz standardtiming. Output
  • Supports Graphics ControllerswithSpread Spectrum InterfaceforLower EMI
  • Free Run Mode Function
  • Fail-SafeFunctioninDE Mode (Bonding Option)
  • Supports DE Mode and SYNC Only Mode (Bonding Option)
  • Power-On-Reset Support
  • CMOS CircuitryOperates from a 2.7Vto3.6V Supply
  • OperationFrequency:54 MHz (Max)@ VCC :2.7 ∼∼ 3.0V
  • OperationFrequency:85 MHz (Max)@ VCC :3.0 ∼∼ 3.6V
  • 128 TQFP Package withBody Size14mm x 14mm x 1.0mm, 0.4mm Pitch These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2RSDS isa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2003–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNOSA80C –JUNE 2003–REVISED APRIL 2013 www.ti.com System Diagram Figure1. Block Diagram oftheLCD Module

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Vertical & Horizontal Counter I/O MUX RSDS TM Tx DATA SWAP Data Path & Timing Ref. 8-6 Bit Translator Clock Synchronization FPD-Link TMFPD-Link TM RxINO[2:0]+/- RxCLKO+/- RxINO[3]+/- (Optional for 8-bit) RxINE[2:0]+/- RxCLKE+/- RxINE[3]+/- (Optional for 8-bit) RSTB TEST[2:1] STH_F RSR[3:0]P/N_F RSG[3:0]P/N_F RSB[3:0]P/N_F RSB[3:0]P/N_B RSG[3:0]P/N_B RSR[3:0]P/N_B STH_B PI RSKEW[2:0] Column & Row Driver Control RSCKP/N_F RSCKP/N_B EMBEDDED GATE ARRAY CLK. OBSOLETE FPD87392AXA www.ti.com SNOSA80C –JUNE 2003–REVISED APRIL 2013 Block Diagram Figure2. Block Diagram Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:FPD87392AXA

SNOSA80C –JUNE 2003–REVISED APRIL 2013 www.ti.com FunctionalDescription DUAL FPD-LINK RECEIVERS The LVDS based FPD-Link Receiversinputsvideodata and controltimingthrough8 pairsof LVDS channels plus2 pairsofLVDS clockstoprovide24-bitcolororuse only6 pairsofLVDS channelsplus2 LVDS clocksto provide18-bitcolor.The videodataisconvertedtoa paralleldatastreamand routedtothe8-6bittranslator. SPREAD SPECTRUM SUPPORT The FPD-Link receiversupportsgraphicscontrollerswithSpread Spectrum interfacesforreducingEMI. The Spread Spectrum methods supportedare Centerand Down Spread.A maximum of2% totalissupportedata frequencymodulationof100kHz maximum. 8-6BIT TRANSLATOR 8-bitdataisreducedtoa 6-bitdatapathviaa timemultiplexedditheringtechniqueor simpletruncationofthe LSBs. Thisfunctionisenabledviatheinputcontrolpins. DATAPATH BLOCK AND RSDS TRANSMITTER 6(8)-bitvideodata(RGB) isinputtotheDatapathBlocksupportsup toan 85 MHz dualpixelrate.The datais delayed to alignthe Column DriverStartPulse (STH) with the Column Driverdata.The dual data bus (RSR[3:0]P/N,RSG[3:0]P/N,RSB[3:0]P/N)outputsat a 170 MHz rateon 24 differentialoutputchannels.The clockisoutputon the(Front,Back) RSCKP/N differentialpairs.The RSDS Column Driverslatchdataon both positiveand negativeedges oftheclock.The swap functionprovidesflexibleRSDS dataoutputmappings for eitherTop or Bottom mount.The RSDS outputsetup/holdtimingsare alsoadjustablethroughtheRSKEW[2:0] inputpins. TIMING CONTROL FUNCTION The TimingControlfunctiongeneratescontrolto Column Drivers,Row Drivers,and power supply.The GPOs (GeneralPurpose Outputs)provideforCD latchpulse,REV, and Row Drivercontrolgeneration.The General Purpose Outputs allowthe user to generatecontrolanywhere withinthe frame data.Standard Row Driver interfaceorCustom Row Driverinterfacescan be implementedwiththeGPOs (GeneralPurposeOutputs). RSDS OUTPUT VOLTAGE CONTROL The RSDS outputvoltageswing iscontrolledthroughan externalloadresistorconnectedto the RPI pin.The RSDS outputsignallevelscan be adjustedtosuittheparticularapplication.Thisisdependenton overallLCD module designcharacteristicssuch as traceimpedance,termination,etc.The RSDS outputvoltageisinversely relatedtotheRPI value.Lower RPI valueswillincreasetheRSDS outputvoltageswingand consequentlyoverall power consumptionwillalsoincrease.

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www.ti.com SNOSA80C –JUNE 2003–REVISED APRIL 2013

REVISION HISTORY

Changes from RevisionB (April2013)toRevisionC Page Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:FPD87392AXA

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