FPD87392_13 TI1 | Alldatasheet

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www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 FPD87392BXB+3.3VTFT-LCDTimingControllerwithDualLVDSInputs/DualRSDS™ OutputsforTFT-LCDMonitorandNotebook(SXGA/SXGA+/UXGA) Check forSamples: FPD87392 1FEATURES DESCRIPTION The FPD87392BXB Panel Timing Controlleris an 23• InputFrequency Range from 25 MHz to85 MHz integratedFPD-Link + RSDS ™ + TFT-LCD Timing• Support DisplayResolutionsSXGA Controller.The logicarchitectureis implemented(1280x1024),SXGA+ (1400x1050)and UXGA using standard and default timing controller (1600x1200) functionalitybased on an Embedded Gate Array.The deviceis reconfigurableto the needs of a specific• Embedded Gate ArrayforCustom Panel applicationby providinguser-definedspecificationsorTiming customersuppliedVHDL/Verilogcode.• RSDS ™ (Reduced Swing Differential Signaling)Column DriverBus forLow Power The FPD87392BXB is a timing controllerthat combines an LVDS dualpixelinputinterfacewithTI'sand Reduced EMI Reduced Swing DifferentialSignaling(RSDS ™ )• DrivesRSDS ™ Column Driverup to170 Mb/s outputcolumn driverinterfaceforSXGA, SXGA+ andwithan 85 MHz Clock UXGA resolutions.Itresideson the TFT-LCD panel

  • 6 or 8 BitLVDS Dual PixelInputInterface and providesthe data bufferingand controlsignal (FPD-Link) generation.The RSDS ™ data path to the column drivercontributestowardloweringradiatedEMI and• Virtual8-BitColorDepth inFRC Mode reduced system dynamic power consumption.The• FlexibleRSDS ™ Data Output Mapping for RSDS ™ dual12 pairdifferentialbus conveys up toBottom or Top Mount 24-bitcolordata for SXGA/SXGA+/UXGA panels
  • Supports 1 and 2 LineInversionMode forRVS when usingVESA 60Hz standardtiming. Output
  • Supports Graphics ControllerswithSpread Spectrum InterfaceforLower EMI
  • Free Run Mode Function
  • Fail-SafeFunctioninDE Mode (Bonding Option)
  • Supports DE Mode and SYNC Only Mode (Bonding Option)
  • Power-On-Reset Support
  • CMOS CircuitryOperates from a 3.0Vto3.6V Supply
  • 128 TQFP Package withBody Size14mm x 14mm x 1.0mm, 0.4mm Pitch Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2RSDS isa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2004–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com System Diagram Figure1. Block Diagram oftheLCD Module

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Vertical & Horizontal Counter I/O MUX RSDS TM Tx DATA SWAP Data Path & Timing Ref. 8-6 Bit Translator Clock Synchronization FPD-Link TMFPD-Link TM RxINO[2:0]+/- RxCLKO+/- RxINO[3]+/- (Optional for 8-bit) RxINE[2:0]+/- RxCLKE+/- RxINE[3]+/- (Optional for 8-bit) RSTB TEST[2:1] STH_F RSR[3:0]P/N_F RSG[3:0]P/N_F RSB[3:0]P/N_F RSB[3:0]P/N_B RSG[3:0]P/N_B RSR[3:0]P/N_B STH_B PI RSKEW[2:0] Column & Row Driver Control RSCKP/N_F RSCKP/N_B EMBEDDED GATE ARRAY CLK. OBSOLETE FPD87392 www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 Block Diagram Figure2. Block Diagram FunctionalDescription DUAL FPD-LINK RECEIVERS The LVDS based FPD-Link Receiversinputsvideodata and controltimingthrough8 pairsof LVDS channels plus2 pairsofLVDS clockstoprovide24-bitcolororuse only6 pairsofLVDS channelsplus2 LVDS clocksto provide18-bitcolor.The videodataisconvertedtoa paralleldatastreamand routedtothe8-6bittranslator. SPREAD SPECTRUM SUPPORT The FPD-Link receiversupportsgraphicscontrollerswithSpread Spectrum interfacesforreducingEMI. The Spread Spectrum methods supportedare Centerand Down Spread.A maximum of2% totalissupportedata frequencymodulationof100kHz maximum. 8-6BIT TRANSLATOR 8-bitdataisreducedtoa 6-bitdatapathviaa timemultiplexedditheringtechniqueor simpletruncationofthe LSBs. Thisfunctionisenabledviatheinputcontrolpins. DATAPATH BLOCK AND RSDS TRANSMITTER 6(8)-bitvideodata(RGB) isinputtotheDatapathBlocksupportsup toan 85 MHz dualpixelrate.The datais delayed to alignthe Column DriverStartPulse (STH) with the Column Driverdata.The dual data bus (RSR[3:0]P/N,RSG[3:0]P/N,RSB[3:0]P/N)outputsat a 170 MHz rateon 24 differentialoutputchannels.The clockisoutputon the(Front,Back) RSCKP/N differentialpairs.The RSDS Column Driverslatchdataon both positiveand negativeedges oftheclock.The swap functionprovidesflexibleRSDS dataoutputmappings for eitherTop or Bottom mount.The RSDS outputsetup/holdtimingsare alsoadjustablethroughtheRSKEW[2:0] inputpins. Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:FPD87392

SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com TIMING CONTROL FUNCTION The TimingControlfunctiongeneratescontrolto Column Drivers,Row Drivers,and power supply.The GPOs (GeneralPurpose Outputs)provideforCD latchpulse,REV, and Row Drivercontrolgeneration.The General Purpose Outputs allowthe user to generatecontrolanywhere withinthe frame data.Standard Row Driver interfaceorCustom Row Driverinterfacescan be implementedwiththeGPOs (GeneralPurposeOutputs). RSDS OUTPUT VOLTAGE CONTROL The RSDS outputvoltageswing iscontrolledthroughan externalloadresistorconnectedto the RPI pin.The RSDS outputsignallevelscan be adjustedtosuittheparticularapplication.Thisisdependenton overallLCD module designcharacteristicssuch as traceimpedance,termination,etc.The RSDS outputvoltageisinversely relatedtotheRPI value.Lower RPI valueswillincreasetheRSDS outputvoltageswingand consequentlyoverall power consumptionwillalsoincrease. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) SupplyVoltage(VDD ) −0.3Vto+4.0V DC TTL InputVoltage(VIN) −0.3Vto(VDD + 0.3V) DC LVDS InputVoltage(VIN) −0.3Vto(VDD + 0.3V) DC OutputVoltage(VOUT ) −0.3Vto(VDD + 0.3V) JunctionTemperature +150°C StorageTemperatureRange (TSTG ) −65°C to+150°C Lead Temperature(TL)(Soldering10 sec.) 260°C (CZAP = 120 pF MM = 200V, ESD Rating R ZAP = 1500W) HBM = 2000V (1) AbsoluteMaximum Ratingsarethosevaluesbeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimplythat thedevicesshouldbe operatedattheselimits.The tableofElectricalCharacteristicsspecifiesconditionsofdeviceoperation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. OperatingConditions Min Max Units SupplyVoltage(VDD ) 3.0 3.6 V OperatingTemp. Range (TA) 0 70 °C SupplyNoiseVoltage 100 mV PP DC ElectricalCharacteristicsTTL DC ElectricalCharacteristics TA = 0°C to70°C, VDD = 3.0Vto3.6V,IPI = 100 µA (Unlessotherwisespecified) Symbol Parameter Conditions Min Typ Max Units VDD Core SupplyVoltage 3.0 3.3 3.6 V VIH Minimum InputHighVoltage 2.0 V VIL Maximum InputLow Voltage 0.8 V VOH OutputHighVoltage IOH = -8mA VDD −0.6 V VOL OutputLow Voltage IOL = 8 mA 0.4 V IIN InputCurrent VIN = VDD ,GND ±10 µA IPU Pull-UpCurrent VDD = 3.3V,VIN = VDD −50 µA IPD Pull-DownCurrent VDD = 3.3V,VIN = GND +50 µA

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www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 DC ElectricalCharacteristicsTTL DC ElectricalCharacteristics(continued) TA = 0°C to70°C, VDD = 3.0Vto3.6V,IPI = 100 µA (Unlessotherwisespecified) Symbol Parameter Conditions Min Typ Max Units IDD C L(TTL)= 15 pF, R L(RSDS) = 100Ω and C L(RSDS) = 5 pF 170 250 (jig& testfixturecapacitance), (CLK = 65 (CLK = 85AverageSupplyCurrent mAIPI = 100 µA MHz, MHz, (TypicallyPIpinconnectedto13 VDD = 3.3V) VDD = 3.6V) kΩ toground),See Figure3 for inputconditions Figure3. FPD-Link ReceiverInputPatternUsed toMeasure IDD DC ElectricalCharacteristicsFPD-Link (LVDS) ReceiverInputCharacteristics Symbol Parameter Conditions Min Typ Max Units LVDS RECEIVER DC SPECIFICATIONS Note:LVDS ReceiverDC parametersaremeasured understaticand steadystateconditionswhichmay notreflecttheactualperformance intheend application. VTH LVDS DifferentialInputHighThreshold +100 mVVoltage VCM = 1.2V VTLLVDS DifferentialInputLow ThresholdVoltage −100 mV IIN VIN = 2.05V,VDD = 3.6V ±10 µA InputCurrent VIN = 0.55V,VDD = 3.6V ±10 µA VIN InputVoltageRange (Single-ended) VDD = 3.0– 3.6V 0.55 2.00 V |VID| DifferentialInputVoltage 0.100 0.600 V VCM Common Mode VoltageOffset VDD = 3.0– 3.6V 0.55+ |VID|/2 2.05− |VID|/2 V Figure4. FPD-Link ReceiverVID and VCM Definitions Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:FPD87392

SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com DC ElectricalCharacteristicsRSDS Output Symbol Parameter Conditions Min Typ Max Units VOD RSDS DifferentialOutputVoltage ±200 mV R L = 100Ω VOS RSDS OffsetVoltage 1.1 1.3 1.5 V Figure5. RSDS VOD and VOS TestCircuit Figure6. RSDS Output Waveforms: SingleEnded vs Differential AC ElectricalCharacteristicsLVDSData Input(1)(2) TA = 0°C to70°C, VDD = 3.0Vto3.6V,IPI = 100 µA (Unlessotherwisespecified) Symbol Parameter Conditions Min Max Units RPLLS FPD-LinkReceiverPhase Lock Loop Wake-up Time 10 ms RSKM VDD = 3.3V,RxIN Skew Margin(3)and (Figure7) 240 psCLK = 85 MHz (1) (RxCLKP/N = 85 MHz; VDD = 3.0to3.6V,R T = 100Ω;IPI = 100 µA;DutyClock= 50%/50%, ±5%; 25°C) (2) Typicalvalueson thistablearemeasured underStaticand Steadystateconditionswhichmay notbe reflectiveofitsperformanceinthe end application. (3) ReceiverSkew Marginisdefinedas thevaliddatasamplingregionatthereceiverinputs.Thismargintakesintoaccounttransmitter pulsepositions(minand max) and thereceiverinputsetupand holdtime(internaldatasamplingwindow:RSPOS). Thismarginallows forLVDS interconnectskew,inter-symbolinterference(bothdependenton typeand lengthofcable),and sourceclock(FPD-Link TransmitterTxCLK IN)jitter.The specifiedRSKM minimum assumes a TPPOS max of200 ps.RSKM = cableskew (type,length)+ source clockjitter(cycletocycle)+ remainingmargin fordatasampling (≥0)Thisparameterisensuredby design.The limitsare based on statisticalanalysisofthedeviceperformanceoverPVT (Process,Voltage,Temperature)range.

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RxINO[0] R[1]R[2] R[0] G[0] R[5] R[4] R[3] R[2] R[1] R[0] G[0] R[5] Note: *6-Bit Input Mode, LVDS Input Pair RxINx[3] will be Ignored RxINO[1] G[2]G[3] G[1] B[1] B[0] G[5] G[4] G[3] G[2] G[1] B[1] B[0] RxINO[2] B[3]B[4] B[2] ENAB VSYNC HSYNC B[5] B[4] B[3] B[2] ENAB VSYNC T/7 T/7 T/7 T/7 T/7 T/7 T/7 Next cycle Previous cycle VDIFF = 0VVDIFF = 0V RCOP(T) RxCLKO 1 cycle OBSOLETE FPD87392 www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 Acronyms: RSKM ReceiverSkew Margin TPPOS TransmitterPulsePosition RSPOS ReceiverStrobePosition SW StrobeWidth Definitions: SW: Setupand HoldTime (Internaldatasamplingwindow) RSKM: CableSkew (type,length)+ SourceClockJitter(cycletocycle)+ Remainingmarginfordatasampling (≥ 0) CableSkew: Typically10 ps − 40 ps perfoot. Figure7. FPD-Link ReceiverInputSkew Margin Figure8. IdealStrobePositionforLVDS Input Figure9. FPD-Link ReceiverSS InputData Mappings (Default) Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:FPD87392

0.9VDD 0.9VDD VDD VDD RPLLS RxINO[0] R[3]R[4] R[2] G[2] R[7] R[6] R[5] R[4] R[3] R[2] G[2] R[7] Note: *6-Bit Input Mode, LVDS Input Pair RxINx[3] will be Ignored RxINO[1] G[3]G[5] G[4] B[3] B[2] G[7] G[6] G[5] G[4] G[3] B[3] B[2] RxINO[2] B[5]B[6] B[4] ENAB VSYNC HSYNC B[7] B[6] B[5] B[4] ENAB VSYNC T/7 T/7 T/7 T/7 T/7 T/7 T/7 Next cycle Previous cycle VDIFF = 0VVDIFF = 0V RCCP(T) RxCLKO 1 cycle OBSOLETE FPD87392 SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com Figure10. FPD-Link ReceiverNS InputData Mappings Figure11. FPD-Link ReceiverPhase Lock Loop Wake-up Time

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www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 Table1.Output Timing(1)(2) Symbol Parameter Conditions Min Typ Max Units RCHP R T = 100Ω,IPI = 100 µA,RSDS Clock(RSCK) HighPeriod 5.7 nsCLK= 85 MHz RCLP R T = 100Ω,IPI = 100 µA,RSDS Clock(RSCK) Low Period 5.8 nsCLK = 85 MHz SPSTU R T = 100Ω,IPI = 100 µA,STH RisingtoRSCK Falling 3.0 nsCLK = 85 MHz SPHLD R T = 100Ω,IPI = 100 µA,STH FallingtoRSCK Falling 3.0 nsCLK = 85 MHz RSTU R T = 100Ω,C L(RSDS) = 5 pF,IPI = 100RS(R, G, B) SetuptoFallingorRising µA, 3.28 nsEdge ofRSCK CLK = 85 MHz, RSDS[2:0]= “100” RHLD R T = 100Ω,C L(RSDS) = 5 pF,RS(R, G, B) HoldfromFallingor IPI = 100 µA,CLK= 85 MHz, 1.87 nsRisingEdge ofRSCK RSDS[2:0]= “100” (1) (RxCLKP/N = 85 MHz; VDD = 3.0to3.6V,R T = 100Ω;IPI = 100 µA;DutyClock= 50%/50%, ±5%; 25°C) (2) Typicalvalueson thistablearemeasured underStaticand Steadystateconditionswhichmay notbe reflectiveofitsperformanceinthe end application. Table2.RSDS Setup and Hold Time withData Skew ControlValues -ReferenceOnly(1)(2) Setup Time (RSTU) Hold Time (RHLD) RSDS[2:0] Units Min Typ Max Min Typ Max 000 1.26 3.91 001 1.75 3.41 010 2.30 2.90 011 2.77 2.41 ns 100 3.28 1.87 101 3.79 1.37 110 4.27 0.89 111 4.77 0.76 (1) (RxCLKP/N = 85 MHz; VDD = 3.0to3.6V,R T = 100Ω;IPI = 100 µA;DutyClock= 50%/50%, ±5%; 25°C) (2) Typicalvalueson thistablearemeasured underStaticand Steadystateconditionswhichmay notbe reflectiveofitsperformanceinthe end application. Figure12. RSDS and TTL (CMOS) Output Timing Diagram Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:FPD87392

SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com Figure13. RSDS and TTL (CMOS) Output Timing Diagram Figure14. RSDS Output Data Mapping FailureDetect(B/O pin“FDE ” = High) ThisfunctionisvalidinDE mode and FDE pinsetto“High”.InvalidexternalDE pulsedoes notaffecttheinternal operationduringfailurezone.

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www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 Figure15. TF_STR (Frame StartTime) and Tvalid_H(ValidH Time) Graphic Mode TF_STR (Lines)(1) Tvalid_H(Clocks)(1) SXGA 12 74 SXGA+ 12 74 UXGA 12 101 (1) TF_STR (Frame StartTime)and Tvalid_H(ValidH Time)isestimatednumbers.These valuesmay notwork properlyforthespecific applicationand needs optimizationprocedureon theactualsystem. Table3.Output Timing— TTL (1) Comments SXGA SXGA+ UXGA Remarks/Parameter (TPW, OE2, OE1 :3’b000) @ 54 MHz @ 54 MHz @ 81 MHz Unit t1 STH RisingtoActiveData 2 2 2 CLKP/N t2 HighDurationofSTH 1 1 1 CLKP/N t3 STH RisingtoTP Rising 660 720 820 CLKP/N t4 HighDurationofTP 54 54 81 CLKP/N t5 STH RisingtoOE Falling 687 747 861 CLKP/N t6 HighDurationofOE 189 189 284 CLKP/N t7 STH RisingtoCPV 660 720 820 CLKP/N t8 HighDurationofCPV 422 422 540 CLKP/N t9 STH RisingtoSTV 238 298 280 CLKP/N t10 1 1 1 LineHighDurationofSTV (844) (844) (1080) (CLKP/N) t11 STH RisingtoREV (1LINE) 645 705 805 CLKP/N t12 1 1 1 LineHigh/LowDurationofREV (1LINE) (844) (844) (1080) (CLKP/N) t13 STH RisingtoREV2 (1+ 2 LINE) 645 705 805 CLKP/N t14 1 (thefirstline)/21 (thefirstline)/2 1 (thefirstline)/2 LineHigh/LowDurationofREV2 (1+ 2 LINE) (844/1688) (844/1688) (1080/2160) (CLKP/N) (1) Line= Hsync Cycle Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:FPD87392

SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com Table4.TP/OE Duty ControlConfiguration @ 54 MHz @ 81 MHzResolution TPW OEW2 OEW1 TP OE (µs) (CLK) (CLK) 0 0 0 3.5 189 2841.0µs 54 CLK @ 540 0 1 3.0 162 243 MHz 0 1 0 2.5 135 203SXGA, SXGA+ 27 CLK @ 81 @ 54 MHz MHz0 1 1 2.0 108 162 1 0 0 3.5 189 2840.5µsUXGA 27 CLK @ 54@ 81 MHz 1 0 1 3.0 162 243 MHz 1 1 0 2.5 135 20341 CLK @ 81 MHz1 1 1 2.0 108 162 Figure16. TTL Output Timing Diagram

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www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 Figure17. TypicalTTL Output Timing Diagram (continued) Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:FPD87392

SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com Figure18. TTL Output Timing withBlanking Table5.8–BIT RSDS Output Data Mapping DMAP2, DMAP1 DMAP2, DMAP1 Pin No. 00 01 10 11 Pin No. 00 01 10 11 Top Mount Bottom Mount Top Mount Bottom Mount

47 R3P_F R0N_F B0N_B B3P_B 78 R3P_B R0N_B B0N_F B3P_F

48 R3N_F R0P_F B0P_B B3N_B 79 R3N_B R0P_B B0P_F B3N_F

49 R2P_F R1N_F B1N_B B2P_B 80 R2P_B R1N_B B1N_F B2P_F

50 R2N_F R1P_F B1P_B B2N_B 81 R2N_B R1P_B B1P_F B2N_F

51 R1P_F R2N_F B2N_B B1P_B 82 R1P_B R2N_B B2N_F B1P_F

52 R1N_F R2P_F B2P_B B1N_B 83 R1N_B R2P_B B2P_F B1N_F

53 R0P_F R3N_F B3N_B B0P_B 84 R0P_B R3N_B B3N_F B0P_F

54 R0N_F R3P_F B3P_B B0N_B 85 R0N_B R3P_B B3P_F B0N_F

56 G3P_F G0N_F G0N_B G3P_B 87 G3P_B G0N_B G0N_F G3P_F

57 G3N_F G0P_F G0P_B G3N_B 88 G3N_B G0P_B G0P_F G3N_F

58 G2P_F G1N_F G1N_B G2P_B 89 G2P_B G1N_B G1N_F G2P_F

59 G2N_F G1P_F G1P_B G2N_B 90 G2N_B G1P_B G1P_F G2N_F

60 G1P_F G2N_F G2N_B G1P_B 91 G1P_B G2N_B G2N_F G1P_F

61 G1N_F G2P_F G2P_B G1N_B 92 G1N_B G2P_B G2P_F G1N_F

62 G0P_F G3N_F G3N_B G0P_B 93 G0P_B G3N_B G3N_F G0P_F

63 G0N_F G3P_F G3P_B G0N_B 94 G0N_B G3P_B G3P_F G0N_F

65 CLKP_F CLKP_B 95 CLKP_B CLKP_F

66 CLKN_F CLKN_B 96 CLKN_B CLKN_F

67 B3P_F B0N_F R0N_B R3P_B 98 B3P_B B0N_B R0N_F R3P_F

68 B3N_F B0P_F R0P_B R3N_B 99 B3N_B B0P_B R0P_F R3N_F

69 B2P_F B1N_F R1N_B R2P_B 100 B2P_B B1N_B R1N_F R2P_F

70 B2N_F B1P_F R1P_B R2N_B 101 B2N_B B1P_B R1P_F R2N_F

71 B1P_F B2N_F R2N_B R1P_B 102 B1P_B B2N_B R2N_F R1P_F

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www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 Table5.8–BIT RSDS Output Data Mapping (continued) DMAP2, DMAP1 DMAP2, DMAP1 Pin No. 00 01 10 11 Pin No. 00 01 10 11 Top Mount Bottom Mount Top Mount Bottom Mount

72 B1N_F B2P_F R2P_B R1N_B 103 B1N_B B2P_B R2P_F R1N_F

73 B0P_F B3N_F R3N_B R0P_B 104 B0P_B B3N_B R3N_F R0P_F

74 B0N_F B3P_F R3P_B R0N_B 105 B0N_B B3P_B R3P_F R0N_F

107 STH_F STH_B 108 STH_B STH_F

Table6.6–BIT RSDS Output Data Mapping (1) DMAP2, DMAP1 DMAP2, DMAP1 PinPin No. 00 01 10 11 00 01 10 11No. Top Mount Bottom Mount Top Mount Bottom Mount

47 HI-Z R0N_F B0N_B HI-Z 78 HI-Z R0N_B B0N_F HI-Z

48 HI-Z R0P_F B0P_B HI-Z 79 HI-Z R0P_B B0P_F HI-Z

53 R0P_F HI-Z HI-Z B0P_B 84 R0P_B HI-Z HI-Z B0P_F

54 R0N_F HI-Z HI-Z B0N_B 85 R0N_B HI-Z HI-Z B0N_F

56 HI-Z G0N_F G0N_B HI-Z 87 HI-Z G0N_B G0N_F HI-Z

57 HI-Z G0P_F G0P_B HI-Z 88 HI-Z G0P_B G0P_F HI-Z

62 G0P_F HI-Z HI-Z G0P_B 93 G0P_B HI-Z HI-Z G0P_F

63 G0N_F HI-Z HI-Z G0N_B 94 G0N_B HI-Z HI-Z G0N_F

67 HI-Z B0N_F R0N_B HI-Z 98 HI-Z B0N_B R0N_F HI-Z

68 HI-Z B0P_F R0P_B HI-Z 99 HI-Z B0P_B R0P_F HI-Z

73 B0P_F HI-Z HI-Z R0P_B 104 B0P_B HI-Z HI-Z R0P_F

74 B0N_F HI-Z HI-Z R0N_B 105 B0N_B HI-Z HI-Z R0N_F

(1) For6–bitoutputmode, RSDS pair3P/Ns willbe inHI-Zmode. Table7.LVDS Inputand RSDS Output Data RxMap BIT_CFG2 BIT_CFG1 InputData Output Data FunctionalDescription 0 0 0 8-bit 8-bit Data isunchanged (NS mapping) 0 0 1 8-bit 6-bit 2 MSBs areHI-Z,FRC Enabled(NS) 0 1 0 6-bit 8-bit 2 LSBs arezero(NS) 0 1 1 6-bit 6-bit 2 MSBs areHI-Z(NS) 1 0 0 8-bit 8-bit Data isunchanged (SS mapping) 1 0 1 8-bit 6-bit 2 MSBs areHI-Z,FRC Enabled(SS) Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:FPD87392

SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com Table7.LVDS Inputand RSDS Output Data (continued) RxMap BIT_CFG2 BIT_CFG1 InputData Output Data FunctionalDescription 1 1 0 6-bit 8-bit 2 LSBs arezero(SS) 1 1 1 6-bit 6-bit 2 MSBs areHI-Z(SS) InputSignalTiming Sync only mode, no DE inputted,is supportedwhen the SYNC pin (BondingOption pin)is enable high. Whenever DE signalisinputted,itworks as DE mode. IntheDE mode, H-blankmin isconsideredwithFailure detectionmode enabled.Inthedefaultsmode, Tvalid_Hshouldbe subtractedinthetablebelow. Sync Mode (Bonding Option)(1) DE Mode (1) Number ofNumber ofH-Timing V-Timing TotalPixelH-Timing (clocks) V-Timing(lines) Total(clocks) (lines) ClocksHorizontalGraphic inaFrom From Sync LinesinaMode H-Blank HorizontalSync TotalH-Timing toData TotalV-Timing H-Blank FrameDetection LinetoData Typ Min Max Typ Min Max Min Min Typ Typ SXGA 248 1430 2047 38 1066 2047 150 2 1066 1688 SXGA+ 128 1550 2047 12 1066 2047 150 2 1066 1688 UXGA 304 1804 4095 46 1250 2047 204 2 1250 2160 (1) H = Lines Figure19. Video SignalFormat Table8.Supports VESA Standard inSYNC Mode (B/O SYNC Pin = High) SXGA SXGA+ UXGA Unit WIDTH 1280 1400 1600 clock HFP 48 48 64 clock Horizontal HSW 112 112 192 clock HBP 248 128 304 clock HEIGHT 1024 1050 1200 Line VFP 1 1 1 Line Vertical VSW 3 3 3 Line VBP 38 12 46 Line

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www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 Power Up Sequence (Defaults) When Power isON, theTCON starttooperateand generatethecontrolsignalsby inputtedLVDS signals.LVDS Receiverwilltakemaximum 10 ms forthePLL wake-up time.Whether LVDS signalsexistbeforethepower-on doesn’teffect.When theReset isreachto2.0V,theR, G, B dataand controlsignalsareoutputtedsequentially and thesequence isjustas followingfigure. Figure20. Power Up Sequence Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:FPD87392

Ground. Power. TEST2 VDD A VSS A 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 R XINO [0] R XINO [2] R XINO [1] R XINO [1] R XINO [0] R XINO [3] R X CLK O + R X CLK O - R XINO [2] R XINO [3] R XINE [0] R XINE [2] R XINE [1] R XINE [1] R XINE [0] R XINE [3] R X CLK E+ R X CLK E- R XINE [2] RX INE [3] VDD A VSS A VSS A VSS A VDD A VSS A VSS A PDI V DD A VDD BIT_CFG1 BIT_CFG2 DMAP1 DMAP2 VSS VDD RSKEW[0] RSKEW[1] RSKEW[2] VSS I O R[3]P_F R[3]N_F R[2]P_F R[2]N_F R[1]P_F R[1]N_F R[0]P_F R[0]N_F VDD I O G[3]P_ F G[3]N_F G[2]P_ F G[2]N_F G[1]P_ F G[1]N_F VSS I O CLKP_F CLKN_F B[3]P_ F B[3]N_F B[2]P_ F B[2]N_F B[1]P_ F B[1]N_F B[0]P_ F B[0]N_F VDD I O P I VSSI O R[3]P_ B R[3]N_B R[1]P_ B R[1]N_B R[0]P_ B R[0]N_B VDD I O CLKP_B CLKN_B R[2]N_B R[2]P_ B VSS I OB[3]P_ BB[3]N_ BB[2]P_ BB[2]N_ BB[1]P_ B VSS REV2 REV1 STV NC VDD VSS CPV NC OE MODE1 VDD VSS TPW OEW1 OEW2 TEST1 B[1]N_ BB[0]P_ BB[0]N_ B VDD I O STH_F STH_B VDD TP VSS RSTB MODE0 FPD87392BXB DMAP[2:1]=00 G[3]P_ B G[2]P_ B G[2]N_ B G[1]P_ B G[1]N_ B G[0]P_ B G[0]N_ B G[3]N_ B G[0]P_ F G[0]N_F RxMap OBSOLETE FPD87392 SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com Pin Connection Figure21. DMAP[2:1]=00

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Ground. Power. TEST2 VDD A VSS A 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 R XINO [0] R XINO [2] R XINO [1] R XINO [1] R XINO [0] R XINO [3] RX CLK O + R XCLK O - R XINO [2] R XINO [3] R XINE [0] R XINE [2] R XINE [1] R XINE [1] R XINE [0] R XINE [3] R XCLK E+ R XCLK E- R XINE [2] R XINE [3] VDD A VSS A VSS A VSS A VDD A V SS A VSS A PDI V D DA VDD BIT_CFG1 BIT_CFG2 DMAP1 DMAP2 VSS VDD RSKEW[0] RSKEW[1] RSKEW[2] VSS I O R[0]N_F R[0]P_F R[1]N_F R[1]P_F R[2]N_F R[2]P_F R[3]N_F R[3]P_F VDD I O G[0]N_F G[0]P_ F G[1]N_F G[1]P_ F G[2]N_F G[2]P_ F G[3]N_F G[3]P_ F VSS I O CLKP_F CLKN_F B[0]N_F B[0]P_ F B[1]N_F B[1]P_ F B[2]N_F B[2]P_ F B[3]N_F B[3]P_ F VDD I O P I VSSI O R[0]N_B R[0]P_ B R[2]N_B R[2]P_ B R[3]N_B R[3]P_ B VDD I O CLKN_B CLKP_B G[0]N_ B G[1]N_ B G[1]P_ B G[2]N_ B G[2]P_ B G[3]N_ B G[3]P_ B G[0]P_ B R[1]P_ B R[1]N_B VSS I OB[0]N_ BB[0]P_ BB[1]N_ BB[1]P_ BB[2]N_ B RxMap VSS REV2 REV1 STV NC VDD VSS CPV NC OE MODE1 VDD VSS TPW OEW1 OEW2 TEST1 B[2]P_ BB[3]N_ BB[3]P_ B VDD I O STH_F STH_B VDD TP VSS RSTB MODE0 FPD87392BXB DMAP[2:1]=01 OBSOLETE FPD87392 www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 Figure22. DMAP[2:1]=01 Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:FPD87392

Ground. Power. TEST2 VDD A VSS A 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 R XINO [0] R XINO [2] R XINO [1] R XINO [1] R XINO [0] R XINO [3] R X CLK O + R X CLK O - R XINO [2] RX INO [3] R XINE [0] R XINE [2] R XINE [1] R XINE [1] R XINE [0] R XINE [3] R X CLK E+ R X CLK E- R XINE [2] R XINE [3] VDD A VSS A VSS A VSS A VDD A VSS A VSS A PDI VDD A VDD BIT_CFG1 BIT_CFG2 DMAP1 DMAP2 VSS VDD RSKEW[0] RSKEW[1] RSKEW[2] VSS I O B[0]N_ B B[0]P_ B B[1]N_ B B[1]P_ B B[2]N_ B B[2]P_ B B[3]N_ B B[3]P_ B VDD I O G[0]N_ B G[0]P_ B G[1]N_ B G[1]P_ B G[2]N_ B G[2]P_ B G[3]N_ B G[3]P_ B VSS I O CLKP_B CLKN_B R[0]N_B R[0]P_ B R[1]N_B R[1]P_ B R[2]N_B R[2]P_ B R[3]N_B R[3]P_ B VDD I O P I VSSI O B[0]N_F B[0]P_ F B[2]N_F B[2]P_ F B[3]N_F B[3]P_ F VDD I O G[0]N_F G[0]P_ F G[1]N_F G[2]N_F G[2]P_ F G[3]N_F G[3]P_ F CLKP_F CLKN_F G[1]P_ F B[1]P_ F B[1]N_F VSS I O R[0]N_F R[0]P_F R[1]N_F R[1]P_F R[2]N_F NC VSS REV2 REV1 STV NC VDD VSS CPV TP OE MODE1 VDD VSS TPW OEW1 OEW2 TEST1 R[2]P_F R[3]N_F R[3]P_F VDD I O STH_B STH_F VDD RxMap VSS RSTB MODE0 FPD87392BXB DMAP[2:1]=10 OBSOLETE FPD87392 SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com Figure23. DMAP[2:1]=10

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Ground. Power. TEST2 VDD A VSS A 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 R XINO [0] R XINO [2] R XINO [1] R XINO [1] R XINO [0] R XINO [3] R XCLK O + R XCLK O - R XINO [2] RX INO [3] R XINE [0] R XINE [2] R XINE [1] R XINE [1] R XINE [0] R XINE [3] R XCLK E+ R XCLK E- RX INE [2] R XINE [3] VDD A VSS A VSS A VSS A VDD A VSS A VSS A PDI VDD A VDD BIT_CFG1 BIT_CFG2 DMAP1 DMAP2 VSS VDD RSKEW[0] RSKEW[1] RSKEW[2] VSS I O B[3]P_ B B[3]N_ B B[2]P_ B B[2]N_ B B[1]P_ B B[1]N_ B B[0]P_ B B[0]N_ B VDD I O G[3]P_ B G[3]N_ B G[2]P_ B G[2]N_ B G[1]P_ B G[1]N_ B G[0]P_ B G[0]N_ B VSS I O CLKP_B CLKN_B R[3]P_ B R[3]N_B R[2]P_ B R[2]N_B R[1]P_ B R[1]N_B R[0]P_ B R[0]N_B VDD I O P I VSSI O B[3]P_ F B[3]N_F B[1]P_ F B[1]N_F B[0]P_ F B[0]N_F VDD I O G[3]P_ F G[3]N_F G[2]P_ F G[1]P_ F G[1]N_F G[0]P_ F G[0]N_F CLKP_F CLKN_F G[2]N_F B[2]N_F B[2]P_ F VSS I O R[3]P_F R[3]N_F R[2]P_F R[2]N_F R[1]P_F RxMap VSS REV2 REV1 STV NC VDD VSS CPV NC OE MODE1 VDD VSS TPW OEW1 OEW2 TEST1 R[1]N_F R[0]P_F R[0]N_F VDD I O STH_B STH_F VDD TP VSS RSTB MODE0 FPD87392BXB DMAP[2:1]=11 OBSOLETE FPD87392 www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 Figure24. DMAP[2:1]=11 Pin Descriptions Table9.System Interface Symbol Pin No. Type Function RxINO[0]P/Nand 4,5 LVDSI FPD-LinkData DifferentialPair0 Input RxINE[0]P/N 19,20 RxINO[1]P/Nand 6,7 LVDSI FPD-LinkData DifferentialPair1 Input RxINE[1]P/N 21,22 RxINO[2]P/Nand 8,9 LVDSI FPD-LinkData DifferentialPair2 Input RxINE[2]P/N 23,24 RxINO[3]P/Nand 12,13 LVDSI FPD-LinkData DifferentialPair3 Input RxINE[3]P/N 25,26 RxCLKOP/N and 10,11 LVDSI FPD-LinkClockDifferentialPairInput RxCLKEP/N 27,28 Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:FPD87392

SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com Table10.RSDS Interface Symbol Pin No. Type Function B[3:0]P/N_B 47–54 RSO BlueReduced Swing DifferentialOutputstoBack Column Drivers G[3:0]P/N_B 56–63 RSO Green Reduced Swing DifferentialOutputstoBack Column Drivers R[3:0]P/N_B 67–74 RSO Red Reduced Swing DifferentialOutputstoBack Column Drivers CLKP/N_B 65,66 RSO ClockReduced Swing DifferentialOutputstoBack Column Drivers B[3:0]P/N_F 78–85 RSO BlueReduced Swing DifferentialOutputstoFrontColumn Drivers G[3:0]P/N_F 87–94 RSO Green Reduced Swing DifferentialOutputstoFrontColumn Drivers R[3:0]P/N_F 98–105 RSO Red Reduced Swing DifferentialOutputstoFrontColumn Drivers CLKP/N_F 95,96 RSO ClockReduced Swing DifferentialOutputstoFrontColumn Drivers PI 76 I ExternalResistorInputforRSDS Output(VOD )LevelControl RSKEW[2:0] 43,44,45 I OutputRSDS Data Skew Control(Default3’b000) Table11.Column/Row DriverControl Symbol Pin No. Type Function TP 110 TO LineLatchSignalOutputtoColumn Drivers STH_B 107 TO HorizontalStartSignalOutputtoBack Column Drivers STH_F 108 TO HorizontalStartSignalOutputtoFrontColumn Drivers REV1 114 TO Data InversionOutputtoColumn Driver(1Line) REV2 113 TO Data InversionOutputtoColumn Driver(1+ 2 Line) STV 115 TO Row DriverStartPulse CPV 119 TO Row DriverShiftClock OE 121 TO ControlTFT Gate PulseWidthtoRow Drivers Table12.ControlInput Symbol Pin No. Type Function BIT_CFG1/2 37,38 I LVDS Inputand RSDS OutputBitSelection MODE[1:0] 122,33 I GraphicMode Selection “00”:SXGA, “01”:SXGA+, “10”:UXGA, “11”:Don ’tCare DMAP1/2 39,40 I RSDS OutputData Mapping TPW 125 I TP DutyControl(DefaultLow) OEW1/2 126,127 I OE DutyControl(Default2’b00) TEST1/2 128,1 I TestMode Low: Normal Operation,High:TestMode PDI 32 I LVDS Power Down (ActiveLow) RSTB 34 I System Reset(ActiveLow) RxMap 120 I RxMap=1(SS Mapping);RxMap=0, NS Mapping NC 111,116 No Connect

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www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 Table13.Power Supply Symbol Pin No. Type Function VDD 36,42,109, P DigitalPower forLogicCore and LVDS Deserializer 117,123 VSS 35,41,112, G DigitalGround forLogicCore and LVDS Deserializer 118,124 VDDA 2,16,17,31 P Power forLVDS PLL and AnalogBandgap VSSA 3,14,15,18, G Ground forLVDS PLL and AnalogBandgap 29,30 VDDIO 55,75,86, P DigitalI/OPower and RSDS Outputs 106 VSSIO 46,64,77, G DigitalI/OGround and RSDS Outputs Table14.Bonding Option (B/O) Symbol Pin No. Type Function SYNC B/O PU SYNC Mode -High:Enable,Low: Disable FRM B/O PU FreeRun Mode -High:Enable,Low: Disable FDE B/O PU FailureDetection-High:Enable,Low: Disable POR B/O PU Power-On-Reset-High:Enable,Low: Disable Pin Types I -Input(3.3VTTL-Compatible) TO -TTL Output(3.3VTTL-Compatible) LVDSI -Low VoltageDifferentialSignalInput RSO -Reduced Swing DifferentialOutput P -Power G -Ground PU -Pull-Up PD -Pull-Down Appendix 1.DE Mode Timing Details DE Mode (DisabledSYNC Pin) Always truewhenever DE isexistas inputtedsignal.IfVSYNC ,H SYNC and DE areavailable,DE mode issuperior and generatethecontroltiming.“V-blankDetection”periodistwo cyclesofthepreviousDE signals.AftertheV- blankdetectionperiod,“Counter”starttocountwhenever DE signalavailablefollowedon therisingedge. Case 1:DisabledFailureDetectionMode Figure25. DE Mode (DisabledSYNC Pin) Case 2:EnabledFailureDetectionMode (SXGA). Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:FPD87392

SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com Appendix 2.Free Run Mode Function(B/O Pin FRM “Low ” toDisable) EitherinputDE signal,ENA, on theDE mode or VSYNC on theSYNC mode are lostmore than5 frames(here, “lost” means ENA orVSYNC signalmore than5 frameswithoutchange),thentheTCON willentertheFree Run Mode. IntheFree Run Mode, theverticaland horizontalperiodwillfollowVESA 60 Hz standardand outputdata willbe intheLow Level. When TCON detectsinputsignalback tonormal(“normal”means ENA orVSYNC signalhas tochange fromLow LeveltoHigh Level),thenoutputcontrolsignalswillreturntotheNormal Mode. Inthenextframe,outputdata willalsoreturntoNormal Mode. Figure26. Free Run Mode Function(B/O Pin FRM “Low ” toDisable)

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www.ti.com SNOSAD3B –JUNE 2004–REVISED APRIL 2013 Appendix 3.Power-Up Sequence on “POR Enabled” Mode When Bondingoptionpins,POR (Power-On-Reset),enablesetto“High”,TCON startrunningas POR mode. If theinputLVDS clockslostwithany reasonsduringthenormaloperation,POR outputsignal(RST_N) willbe low untilLVDS clockcomeback again.The Reset counterstarttocountwithLVDS clockresume thenturntonormal operationmode beforethe10 ms PLL Wake-Up timelimits. Figure27. Power-Up Sequence on “POR Enabled” Mode Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:FPD87392

SNOSAD3B –JUNE 2004–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionA (April2013)toRevisionB Page

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