FPD87352

FPD87352 TI1 | Alldatasheet

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www.ti.com SNOSAG3C –JULY 2004–REVISED APRIL 2013 FPD87352CXA+3.3VTFT-LCDTimingControllerwithSingleLVDS Input/DualRSDS™ OutputsIncludingRTC(Response TimeCompensation)forTFT-LCDMonitorsandTV (XGA/WXGA/HDTVI,II,-) Check forSamples: FPD87352 1FEATURES DESCRIPTION The FPD87352CXA is an integratedFPD-Link™ + 23• InputFrequency Range from 30 MHz to95 MHz RSDS + TFT-LCD Timing Controller.The logic• Support DisplayResolutionsXGA (1024x768), architectureis implemented using standard andWXGA (1280x768),HDTV I(1280x768),HDTV II defaulttimingcontrollerfunctionalitybased on an (1366x768)and HDTV -(1280x800) Embedded Gate Array.The deviceisreconfigurable to the needs of a specificapplicationby providing• Embedded Gate ArrayforCustom Panel user-definedspecificationsor customer suppliedTiming VHDL/Verilogcode.• LVDS SinglePixelInput(8-Bit/6-Bit)Interface (FPD-Link) The FPD87352CXA isan idealTimingControllerfor LCD TV Applications.Ithas a unique feature,RTC• RSDS Dual Bus Output (8-Bit/6-Bit) thatwillimprovetheintra-graylevelresponsetimeof• DrivesRSDS Column Driversup to47.5MHz a LCD TV panel. Improving the intra-graylevelClock response time of the LCD panel willresultin a dramaticallyimproved Motion PictureImage Quality• FlexibleRSDS Data Output Mapping for ofvideocontentthataredisplayedon theLCD panel.Bottom or Top Mount The RTC featureisaccomplishedthroughapplication• RTC (Response Time Compensation) Function ofa BoostorOverdriveVoltagethatwillforcetheLC• 2 Wired SerialEEPROM InterfaceSupport materialto respond more rapidly.This Boost or (RTC LUT) Overdriveisaccomplishedthroughcombinationofan internalor externalEEPROM LUT (Look Up Table),• InterfacewithExternalFrame Memory which contains the boost/overdrivelevels,and• Virtual8-BitColorDepth inFRC/Dithering externalmemory thatactsas a Frame Buffer.Mode The FPD87352CXA is a timing controllerthat• Supports Graphics ControllerswithSpread combines an LVDS singlepixelinputinterfacewithSpectrum InterfaceforLower EMI National'sReduced Swing DifferentialSignaling• Supports ExternalSpread Spectrum (SSCG) (RSDS) output column driver interface for

• DE Only Mode XGA/WXGA/HDTV I,II,-resolutions.Itresideson the FlatPanel Displayand providesthe data buffering• CMOS CircuitryOperates from 3.0V–3.6V; and controlsignalgeneration.FPD-Link, a lower0°C –70°C dynamic power, low EMI (Electro Magnetic• 176 LQFP Package withBody Size24 mm x 24 Interference)interfaceis used between thistiming mm x 1.4mm, 0.5mm Pitch controllerand the hostsystem.A RSDS interfaceis used between the timingcontrollerand the column drivers. The dual13/10pairdifferentialbus conveysup to24- bitcolordataforXGA, WXGA and HDTV panels. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2RSDS isa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2004–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

/12 + CLK, RSDS BUS (Back)/12 + CLK, RSDS BUS (Front) Column Start Pulse (Front) Column Start Pulse (Back Panel Timing Controller XGA (1024 x 768) up to 95 MHz WXGA (1280 x 768) up to 95 MHz HDTV I (1280 x 720) up to 95 MHz Dot Inversion LCD panel TFT-LCD Array * Optional for 8 bit color Gray scale Reference Gray Scale Voltage Reference BUS Line Data Latch RD n RD n Row Start Pulse Row Clock EEPROM /10 Address[9:0] /6 Memory control /32 Frame data interface /2 FPD-Link [3]* /2 FPD-Link CLK /2 FPD-Link [2] /2 FPD-Link [1] /2 FPD-Link [0] Polarity Control RSDS CD RSDS CD RSDS CD HDTV II (1366 x 768) up to 95 MHz HDTV- (1280 x 800) up to 95 MHz

2 Kb or More, 400 kHz Max

/2 2-wire serial interface Panel Power Supply VDD VSS 64 Mb SDRAM 5 C OBSOLETE FPD87352 SNOSAG3C –JULY 2004–REVISED APRIL 2013 www.ti.com System Diagram Figure1. Block Diagram oftheLCD Module

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(64 Mb SDRAM) DE Filter SSC Internal ROM LUT Register2-wire serial EEPROM Interface FPD-Link Receiver RxIN0P/N RxIN1P/N RxIN2P/N RxIN3P/N RxCLKP/N RESETN TEST Control Options SSCKO SSCKI SSCTR SCL SDA RSF/BR[3:0]P/N RGB data RSKEW[2:0] PI RSF/BG[3:0]P/N RSF/BB[3:0]P/N RSF/BCKP/N TP POL F/BSTH CPV OE STV RVC RGB dataDE DCLK DE_in DCLK_in DATA_in MCLK, RAM interface Mth frame RGB data M-1th frame RGB data Mth frame RGB data DCLK DCLK DCLK, SYNC, DE SYNC LUT Value LUT Address CLK, RGB data OBSOLETE FPD87352 www.ti.com SNOSAG3C –JULY 2004–REVISED APRIL 2013 Block Diagram Figure2. Block Diagram FunctionDescription FPD-LINK RECEIVER The LVDS based FPD-Link Receiverreceivesinputvideodata and controltiming.Four LVDS channelsplus clockprovide24-bitcolor. RESETN initializesthe chipwiththe defaultregistervaluesforthe LUT valuesfrom internalROM or external EEPROM. SSC (SPREAD SPECTRUM CONTROL) This SSC functionprovidesa means forreducingEMI. This featureuses externalSSC signalsource that providessynchronizedspreadspectrumforRSDS and controlsignaloutputs. 2-WIRE SERIAL EEPROM INTERFACE The SerialEEPROM InterfacecontrolstheFPD87352CXA initializationofLUT register.IftheEEPROM isnot present,theLUT valueisprovidedby internalROM ofFPD87352CXA. CLK & DATA SYNCHRONIZER Thisfunctiondelaysand alignsdatatomatch theinternaldataprocesswhich includedRSDS skew controlby RSKEW[2:0]. Allthedataprocessesare needed tobe alignedeach datapaththroughRSDS outputand LCD timingcontrolsignal. Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:FPD87352

SNOSAG3C –JULY 2004–REVISED APRIL 2013 www.ti.com LUT REGISTER ThisblockprovidestheRTC referencevaluestobe processedon theRTC Data ProcessorBlock.The settingof RTC referencevaluesisprovidedby theexternalEEPROM innormalcondition.IftheexternalEEPROM isnot presentitwilluse theinternalROM's RTC referencevalues.The RTC referencevaluesarethenew grayvalues dependingon thedifferencebetween thecurrentframes'RGB graydataand thepreviousframe'sRGB graydata ofsame pixel. RTC DATA PROCESSOR Thisfunctiongeneratesnew grayvaluesdependingon thedifferenceofthecurrentRGB graydataand same pixelof the previousframe.The referencevaluesfetchfrom the LUT (Look Up Table)valuesin the LUT Register. RSDS INTERFACE WITH SKEW CONTROL ThisfunctionalblocktransformsCMOS levelsignaltoRSDS forthesystem clock(DCLK) and RGB colordata. The RSDS skew is controlledby RSKEW[2:0] with delay steps between the RSF/BCKP/N and RSF/BR/G/B[3:0]P/NwhichisimplementedinCLK & Data synchronizer. VERTICAL & HORIZONTAL LCD TIMING CONTROL ThisfunctionblockgeneratestheTTL(CMOS) levelsignalfortheinterfaceofcolumn driversand row driversin theLCD system.Allsignalsaresynchronizedby RSF/BCKP/N whichisRSDS dataclockforthecolumn drivers. The clockskew controlmust notchange thetypicaltimingofTTL(CMOS) levelsignals.

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REVISION HISTORY

Changes from RevisionB (April2013)toRevisionC Page Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:FPD87352

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