FPD87346BXA

FPD87346BXA TI1 | Alldatasheet

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FPD87346BXA Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controllerwith Reduced Swing Differential Signaling (RSDS) Outputs Literature Number: SNOSAC6A

September 22, 2011 Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT- LCD Timing Controller with Reduced Swing Differential Signaling (RSDS™) Outputs General Description The FPD87346BXA is a timing controller that combines an LVDS single pixel input interface with National's Reduced Swing Differential Signaling (RSDS™) output driver interface for (SVGA) XGA and Wide XGA resolutions. It resides on the TFT-LCD panel and provides the data buffering and control signal generation for (SVGA) XGA, and Wide XGA graphic modes. The RSDS™ path to the column driver contributes toward lowering radiated EMI and reducing system dynamic power consumption. This single RSDS™ bus conveys the 8-bit color data for (SV- GA) XGA, and Wide XGA panels at 170 Mb/s when using VESA 60 Hz standard timing.

Features

■ Reduced Swing Differential Signalling (RSDS™) digital bus reduces dynamic power, EMI and bus width from the timing controller ■ LVDS single pixel input interface system ■ Input clock range from 40 MHz to 85 MHz ■ Drives RSDS™ Column Drivers at 170 Mb/s with an 85 MHz clock (Max.) ■ Virtual 8 bit color depth in FRC/Dithering mode ■ Single narrow 9-bit differential Source Driver bus minimizes width of Source PCB ■ Ability to drive (SVGA) XGA and Wide XGA TFT-LCD Systems ■ Failure detect function in DE mode (Bonding Option) ■ CMOS circuitry operates from a 3.0V–3.6V supply System Diagram 20101601 FIGURE 1. Block Diagram of the LCD Module

201016 Version 2 Revision 4 Print Date/Time: 2011/09/22 09:36:00

FIGURE 2. Block Diagram needs of TFT-LCD Manufacturers. function is enabled via the input control pins. the Column Driver Start Pulse with the Column Driver data. are also adjustable through the RSDS[2:0] input pins. characteristics such as trace impedance, termination, etc.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) −0.3V to +4.0V DC TTL Input Voltage (VIN) −0.3V to (VDD + 0.3V) DC Output Voltage (VOUT) −0.3V to (VDD + 0.3V) Junction Temperature +150°C Storage Temperature Range (T STG) −65°C to +150°C Lead Temperature (TL) (Soldering 10 sec.) 260°C ESD Rating: (C ZAP = 120 pF, R ZAP = 1500Ω) MM = 200V, HBM = 2000V Operating Conditions Min Max Units Supply Voltage (VDD) 3.0 3.6 V Operating Temp Range (TA) 0 70 °C Supply Noise Voltage (VDD) 200 mVPP Spread Spectrum Support, LVDS Spreading Range ± 2.0 % Modulation Rate 100 kHz Operating Frequency (f) 40 85 MHz TTL DC ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min Typ Max Units VOH Minimum High Level Output Voltage STV, CPV, OE IOH = -6 mA

2.4 VTP, REV IOH = -8 mA

STH IOH = -24 mA VOL Maximum Low Level Output Voltage STV, CPV, OE IOL = +6 mA

0.4 VTP, REV IOL = +8 mA

STH IOL = +24 mA VIH Minimum High Level Input Voltage 2.0 V VIL Maximum Low Level Input Voltage 0.8 V IIN Input Current VIN = VDD, GND –10 +10 µA IDD Average Supply Current f = 85 MHz VDD = 3.6V, CL(TTL) = 15 pF, IPI = 100 µA (Typically PI pin connected to 13 kΩ to ground) RL(RSDS) = 100Ω and CL(RSDS) = 5 pF (jig & test fixture capacitance), See Figure 3 for input conditions 85 150 mA Note 1: “Absolute Maximum Rating” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. 3 www.national.com

FIGURE 3. FPD-Link Receiver IDD Pattern Note 2: LVDS Receiver DC parameters are measured under static and steady state conditions which may not reflect the actual performance in the end application. FIGURE 4. |VID| and VCM Allowable Operating Range

Note 3: VOSRSDS = (V(F&B)CLKP + V(F&B)CLKN)/2 or VOSRSDS = (V(F&B)XYP + V(F&B)XYN)/2. VODRSDS = V(F&B)CLKP − V(F&B)CLKN or VODRSDS = V(F&B)XYP − V(F&B)XYN. The load between the positive and negative output is 100Ω. FIGURE 5. RSDS Waveform - Single Ended and Differential FIGURE 6. Typical RSDSVOD vs. RPI Response Curve

Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window: RSPOS). TxCLK IN) jitter (less than 190 ps). The specified RSKM minimum assumes a TPPOS max of 200 ps. This parameter is guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (Process, Voltage, Temperature) range. FIGURE 7. FPD87346BXA (FPD-Link Receiver) Input Skew Margin

FIGURE 8. FPD87346BXA (FPD-Link Receiver) Input Data Mapping FIGURE 9. FPD87346BXA (FPD-Link Receiver) Phase Lock Loop Wake-up Time

Symbol Parameter Conditions Min Typ Max Units TO1 TTL Output Rising from RSCLK Rising CL(TTL) = 15 pF, RT = 100Ω, CL(RSDS) = 5 pF, IPI = 100 µA, f = 85 MHz 0.0 11.25 ns TO2 TTL Output Falling from RSCK RisingCL(TTL) = 15 pF, RT = 100Ω, CL(RSDS) = 5 pF, IPI = 100 µA, f = 85 MHz 0.0 11.25 ns RCHP RSDS Clock (RSCK) High Period RT = 100Ω, CL(RSDS) = 5 pF, IPI = 100 µA, f = 85 MHz 5.7 ns RCLP RSDS Clock (RSCK) Low Period RT = 100Ω, CL(RSDS) = 5 pF, IPI = 100 µA, f = 85 MHz 5.8 ns RSTU RS(R,G,B) Setup to Falling or Rising Edge of RSCK RT = 100Ω, CL(RSDS) = 5 pF, IPI = 100 µA, f = 85 MHz, RSDS[2:0] = [000] 3.2 ns RHLD RS(R,G,B) Hold from Falling or Rising Edge of RSCK RT = 100Ω, CL(RSDS) = 5 pF, IPI = 100 µA, f = 85 MHz, RSDS[2:0] = [000] 1.8 ns SPSTU STH Rising to RSCK Falling RT = 100Ω, CL(RSDS) = 5 pF, IPI = 100 µA, f = 85 MHz 5.0 ns SPHLD STH Falling to RSCK Falling RT = 100Ω, CL(RSDS) = 5 pF, IPI = 100 µA, f = 85 MHz 4.0 ns TABLE 1. Typical Simulation Results of RSDS Skew Control Values* (VDD = 3.3V; RT = 100ohms; IPI = 100 µA; 25°C) RSDS[2:0] f = 65 MHz f = 85 MHz UnitRSTU RHLD RSTU RHLD 000 5.03 1.83 3.23 1.83 ns001 5.26 1.31 3.75 1.31 010 6.03 0.83 4.23 0.83 011 6.53 0.33 4.73 0.33 100 3.01 3.77 1.21 3.77 ns101 3.49 3.33 1.69 3.33 110 4.00 2.86 2.20 2.86 111 4.50 2.36 2.70 2.36 *The skew control value in the table are only sampling values of a specific condition and is not a parametric value. Typical values on this table are measured under Static and Steady state conditions which may not be reflective of its performance in the end application. www.national.com 8

FIGURE 10. FPD87346BXA RSDS and TTL Output Timing Diagram

Note: RSCKP/N, RSR[2:0]P/N, RSG[2:0]P/N and RSB[2:0]P/N are differential outputs, STH is a single ended TTL output. FIGURE 11. FPD87346BXA RSDS Output Data Mapping

FIGURE 12. FPD87346BXA Failure Detection

(800 x 600) XGA (1024 x 768) WXGA I (1280 x 768) WXGA II (1280 x 800) Unit Clock Frequency 1/Tclk f typ 40 65 82 69 MHz Vertical Timing Total Tv min 620 772 772 804 Th typ 628 806 806 816 max 664 850 850 900 Active Tvact min – – – – typ 600 768 768 800 max – – – – Horizontal Timing Total Th min 1050 1050 1320 1320 Tclk typ 1056 1344 1688 1408 max 1056 1800 2000 2000 Active Thact min – – – – typ 800 1024 1280 1280 max – – – – Output Timing—TTL DE (Data Enable) Mode Only Parameter Comments Display Mode WIDE(0/1) (Pin 57) SVGA (WIDE=0) XGA (WIDE=0) WXGA (WIDE=1) Remarks/ Unit t1 STH Rising to Active Data 2 2 2 RxCLKP/N t2 High Duration of STH 1 1 1 RxCLKP/N t3 STH Rising to TP 1031 1031 1285 RxCLKP/N t4 High Duration of TP 8 8 10 RxCLKP/N t5 STH Rising to OE 904 904 1147 RxCLKP/N t6 High Duration of OE 159 159 180 RxCLKP/N t7 STH Rising to CPV 1031 1031 1283 RxCLKP/N t8 High Duration of CPV 684 684 724 RxCLKP/N t9 STH Rising to STV 368 368 565 RxCLKP/N t10 High Duration of STV 1 1 1 H Line (Note 6) t11 STH Rising to REV (1HRVS) 390 390 567 RxCLKP/N t12 High/Low Duration of REV (1HRVS) 1 1 1 H Line (Note 6) t13 STH Rising to REV (2HRVS) 371 371 567 RxCLKP/N t14 High/Low Duration of REV (2HRVS) 2 2 2 H Line (Note 6) Note 6: H Line: Hsync Cycle www.national.com 12

FIGURE 13. FPD87346BXA TTL Output Timing Diagram

FIGURE 14. FPD87346BXA TTL Output Timing Diagram (continued)

FIGURE 15. FPD87346BXA ROn (Sn) Configuration Timing Diagrams

FIGURE 16. Pinout Assignments

RxIN[0]P/N 3, 4 LVDSI FPD-Link Data Differential Pair 0 Input RxIN[1]P/N 5, 6 LVDSI FPD-Link Data Differential Pair 1 Input RxIN[2]P/N 7, 8 LVDSI FPD-Link Data Differential Pair 2 Input RxIN[3]P/N 11, 12 LVDSI FPD-Link Data Differential Pair 3 Input RxCLKP/N 9, 10 LVDSI PFD-Link Clock Differential Pair Input Sub-Total Pin Count Column Driver Interface Symbol Pin Type Function R[2:0]P/N 26–31 RSO Red Reduced Swing Differential Outputs to Column Drivers G[2:0]P/N 36–41 RSO Green Reduced Swing Differential Outputs to Column Drivers B[2:0]P/N 42–47 RSO Blue Reduced Swing Differential Outputs to Column Drivers CLKP/N 34, 35 RSO Clock Reduced Swing Differential Outputs to Column Drivers TP 50 TO, 8mA Line Latch Signal Output to Column Drivers STH 52 TO, 24mA Horizontal Start Signal Output to Column Drivers REV 51 TO, 8mA Alternative Signal Output for each 1 or 2 Horizontal Line to Column Drivers and LC Control Sub-Total Pin Count Row Driver Interface Symbol Pin Type Function STV 53 TO, 6mA Row Driver Start Pulse CPV 54 TO, 6mA Row Driver Shift Clock OE 55 TO, 6mA Control TFT Gate Pulse Width to Row Drivers Sub-Total Pin Count Control Pins Symbol Pin Type Function FRC 56 I Data Dithering Option: 0: 8-Bit Input, Dithering (FRC) 1: 6-Bit Input, Non Dithering (No FRC) RSDS[2:0] 20–22 I RSDS Skew/Timing Control (See Table 1) WIDE 57 I 0: SVGA (800 x 600) 0: XGA (1024 x 768) 1: WXGA (1280 x 768/800) RO[2:0] 60–62 I Alternate each 1 Horizontal/2 Horizontal on REV with OE Timing (See Table 2 and Figure 15) RES 59 I Reserved pin, tie to high (VDD) TEST 23 I 0: Normal Operation 1: Test Mode Sub-Total Pin Count 17 www.national.com

VDD 17 P Digital Power for Logic Core and LVDS Deserializer VSS 63 G Digital Ground for Logic Core and LVDS Deserializer VDDIO 18, 32, 48, P Digital I/O Power and RSDS Outputs VSSIO 16, 25, 33, G Digital I/O Ground and RSDS Outputs VDDA 1 P Power for LVDS PLL and Analog Bandgap VDDD 2 P Digital Power for LVDS Input Buffer VSSD 13 G Digital Ground for LVDS Input Buffer VSSP 15 G Ground for LVDS PLL and Analog Bandgap VSSA 14 G Ground for LVDS PLL and Analog Bandgap Sub-Total Pin Count Other Symbol Pin Type Function PI 24 I Reference for Reduced Swing Differential Outputs RSTZ 19 I System Reset; Active Low NC 58 I No Connect Sub-Total Pin Count Total Pin Count

64 System Interface = 10

Column Driver = 23 Row Driver = 3 Control Pins = 10 Power Supply = 15 Other = 3 Bonding Options (B/O) Symbol Pin Type Function FAIL_ON B/O PD Failure Detect Function ON/OFFLow : OFF (Default) High : ON Pin Types I -Input (LVTTL-Compatible) TO -TTL Output (LVTTL-Compatible) LVDSI -Low Voltage Differential Signal Input RSO -Reduced Swing Differential Output P -Power G -Ground B/O -Bonding Option PD -Internal Pull-Down PU -Internal Pull-Up www.national.com 18

Physical Dimensions inches (millimeters) unless otherwise noted 64-pin TQFP Package Order Number FPD87346BXAVS 19 www.national.com

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201016 Version 2 Revision 4 Print Date/Time: 2011/09/22 09:36:01

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