FPD87346 TI1 | Alldatasheet

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www.ti.com SNOSA51A –MAY 2004–REVISED APRIL 2013 FPD87346LowEMI,LowDynamicPower(SVGA)XGA/WXGATFT-LCDTimingController withReducedSwingDifferentialSignaling(RSDS™ )Outputs Check forSamples: FPD87346 1FEATURES DESCRIPTION The FPD87346 isa timingcontrollerthatcombines 2• Reduced Swing DifferentialSignalling an LVDS single pixel input interfacewith TI's(RSDS ™ )DigitalBus Reduces Dynamic Reduced Swing DifferentialSignaling(RSDS ™ )Power, EMI and Bus Width from theTiming outputdriverinterfacefor(SVGA) XGA and WideController XGA resolutions.Itresideson the TFT-LCD panel

  • LVDS SinglePixelInputInterfaceSystem and providesthe data bufferingand controlsignal generationfor(SVGA) XGA, and Wide XGA graphic• InputClock Range from 40 MHz to85 MHz modes. The RSDS ™ path to the column driver• DrivesRSDS ™ Column Driversat170 Mb/s contributestoward lowering radiated EMI andwithan 85 MHz Clock (Max.) reducingsystemdynamicpower consumption.
  • Virtual8 BitColorDepth inFRC/Dithering ThissingleRSDS ™ bus conveys the8-bitcolordataMode for(SVGA) XGA, and Wide XGA panelsat170 Mb/s• SingleNarrow 9-BitDifferentialSource Driver when usingVESA 60 Hz standardtiming. Bus MinimizesWidth ofSource PCB
  • AbilitytoDrive(SVGA) XGA and Wide XGA TFT-LCD Systems
  • FailureDetectFunctioninDE Mode
  • CMOS CircuitryOperates from a 3.0V–3.6V Supply These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. System Diagram Figure1. Block Diagram oftheLCD Module Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2004–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

Timing Ref. 8-6 Bit Translator RxIN[3]± RxIN[2]± RxIN[1]± RxIN[0]± RxCLK± RSDS[2:0] RSR[2:0]P/N RSG[2:0]P/N RSB[2:0]P/N STH RSTZ RPI Column & Row Driver Control RSCKP/N CLK. FPD-Link TM H Ref. V Ref. Vertical & Horizontal Timing Generation Serializer OBSOLETE FPD87346 SNOSA51A –MAY 2004–REVISED APRIL 2013 www.ti.com Block Diagram Figure2. Block Diagram FunctionalDescription FPD-LINK RECEIVER The LVDS based FPD-LinkReceiverinputsvideodataand controltimingthrough4-LVDS channelsplusclockto provide24-bitcoloror 3-LVDS channelscan be used for18-bitcolor.The videodataisconvertedtoa parallel datastreamand routedtothe8-6bittranslator. SPREAD SPECTRUM SUPPORT The FPD-Link receiversupportsgraphicscontrollerswithSpread Spectrum interfacesforreducingEMI. The Spread Spectrum methods supportedare Centerand Down Spread.A maximum of2% totalissupportedata frequencymodulationof100kHz maximum. 8-6BIT TRANSLATOR 8-bitdataisreducedtoa 6-bitdatapathviaa timemultiplexedditheringtechniqueor simpletruncationofthe LSBs. Thisfunctionisenabledviatheinputcontrolpins. DATAPATH BLOCK AND RSDS TRANSMITTER 6(8)-bitvideodata(RGB) isinputtotheDatapathBlocksupportsup toan 85 MHz pixelrate.The dataisdelayed to alignthe Column DriverStartPulse (STH) with the Column Driverdata.The data bus (RSR[2:0]P/N, RSG[2:0]P/N,RSB[2:0]P/N)outputsata 170 MHz rateon 9 differentialoutputchannels.The clockisoutputon theRSCKP/N differentialpair.The RSDS Column Driverslatchdataon bothpositiveand negativeedges ofthe clock.The RSDS outputsetup/holdtimingsarealsoadjustablethroughtheRSDS[2:0]inputpins. TIMING CONTROL FUNCTION The TimingControlfunctiongeneratescontrolto Column Drivers,Row Drivers,and power supply.The GPOs (GeneralPurpose Outputs)provideforCD latchpulse,REV, and Row Drivercontrolgeneration.The General Purpose Outputs allowthe user to generatecontrolanywhere withinthe frame data.Standard Row Driver interfaceorCustom Row Driverinterfacescan be implementedwiththeGPOs (GeneralPurposeOutputs). RSDS OUTPUT VOLTAGE CONTROL The RSDS outputvoltageswing iscontrolledthroughan externalloadresistorconnectedto the R PI pin.The RSDS outputsignallevelscan be adjustedtosuittheparticularapplication.Thisisdependenton overallLCD module designcharacteristicssuch as traceimpedance,termination,etc.The RSDS outputvoltageisinversely relatedtotheR PI value.Lower R PI valueswillincreasetheRSDS outputvoltageswingand consequentlyoverall power consumptionwillalsoincrease.

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