FPD87310 NSC | Alldatasheet
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Technical content
Features
n RSDS (Reduced Swing Differential Signaling) Column Driver bus for low power and reduced EMI n Drives RSDS Column Drivers at 130 Mb/s with a 65 MHz clock n 6- or 8-bit LVDS Video System Interface (FPD-Link) n 10 General Purpose Outputs for Column/Row Drivers n Optional EEPROM programming allows fine tuning in development and production environments n Selectable dual initialization value sets to share parts for the different model panel module n Ability to drive XGA/SVGA TFT-LCD Systems n Narrow 9-bit+CLK differential Column Driver Bus minimizes width of Source PCB n CMOS circuitry operates from a 3.3V supply n Supports Graphics Controllers with spread spectrum interface featurefor lower EMI System Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. DS101077-1 PRELIMINARY May 2000 FPD87310 Universal Interface XGA Panel Timing Controller with RSDS™(Reduced Swing Differential Signaling) and FPD-Link © 2000 National Semiconductor Corporation DS101077 www.national.com
Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V DD )4 V DC Input Voltage (VIN) −0.3V to 4.0V DC Output Voltage (VOUT ) −0.3V to V DD +0.3V Storage Temperature Range (TSTG ) −65˚C to +150˚C Lead Temperature (TL) (Soldering 10 sec.) 260˚C ESD Rating: HBM ≥2kV MM ≥200V Operating Conditions Min Max Units Supply Voltage (VDD ) 3.0 3.6 V Operating Temp Range (TA) 0 70 ˚C Operating Frequency (fCLK ) 67 MHz
Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS VDD = 3.3V± 0.3V, VSS = 0.0V (Unless otherwise specified). Symbol Parameter Conditions Min Typ Max Units VOH Minimum High Level Output Voltage VDD = 3.3V, IOH =8m A 2.2 V VOL Maximum Low Level Output Voltage VDD = 3.3V, IOL =8m A 0.8 V VIH Minimum High Level Input Voltage 2.0 V VIL Maximum Low Level Input Voltage 0.8 V IIN Input Current V IN =V SS to VDD −10 10 µA IDD Supply Current f CLK = 65 MHz, RPI = 13kΩ , See Figure 1 140 mA FPD-Link (LVDS) RECEIVER INPUT (RxCLK+/−, RxIN[y]+/−; y = 0, 1, 2, 3) Symbol Parameter Conditions Min Typ Max Units VIHLVDS LVDS Input High Level Threshold Voltage VCM LVDS = +1.2V (Note 2) +100 mV VILLVDS LVDS Input Low Level Threshold Voltage VCM LVDS = +1.2V (Note 2) −100 mV VCM LVDS LVDS Input Common Mode Voltage Range VDIFFLVDS = ± 100 mV (Note 2) 1.25 V IIN LVDS Input Current V IN = +2.4V, VCC = 3.6V ±10 µA VIN = 0V, VCC = 3.6V ±10 µA RSDS TRANSMITTER OUTPUT (RSCKP/N, RSx[y]P/N; x = R, G, B y = 0, 1, 2) Symbol Parameter Conditions Min Typ Max Units VOH RSDS RSDS High Differential Output Voltage VCM RSDS = +1.3V± 5% (Note 3) +150 +200 mV VOL RSDS RSDS Low Differential Output Voltage VCM RSDS = +1.3V± 5% (Note 3) −200 −150 mV VCM RSDS RSDS Common Mode Output Voltage VDIFFRSDS = ± 200 mV (Note 3) 1.3 V Note 1:“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2:VCM LVDS =( VRxCLK+ +V RxCLK− )/2 or VCM LVDS =( VRxIN[y]++V RxIN[y]−)/2; y = 0, 1, 2, 3. VDIFFLVDS =V RxCLK+ −V RxCLK− or VDIFFLVDS =V RxIN[y]+−V RxIN[y]−; y = 0, 1, 2, 3 Note 3:VCM RSDS =( VRSCKP +V RSCKN) /2 or VCM RSDS =( VRSx[y]P+V RSx[y]N)/2; x = R, G, B y = 0, 1, 2 VDIFFRSDS =V RSCKP −V RSCKN or VDIFFRSDS =V RSx[y]P−V RSx[y]N;x=R ,G ,By=0 ,1 ,2 The Termination Resister for differential line between positive and negative output is 100Ω . Pin “PI” is connected to ground by 13.0 kΩ . This parameter is Guaranteed by Design. FPD87310 www.national.com 2
FIGURE 6. FPD87310 Power Up Sequence
RSDS (Reduced Swing Differential Signalling) Output Timing, these parameters are Guaranteed by Design. FIGURE 7. FPD87310 RSDS Output Timing Diagram
Note:RSCKP/N, RSR[2:0]P/N, RSG[2:0]P/N and RSB[2:0]P/N are differential outputs, SP is single ended output. FIGURE 8. FPD87310 RSDS Output Data Mapping
The LVDS based FPD-Link Receiver inputs video data and control timing. 4-LVDS channels plus clock provide 24 bits color. 3-LVDS channels can be used for 18 bits color. The video data is regenerated to a parallel data stream and routed to the 8-6 bit translator. The GPOs (General Purpose Outputs) continue outputting the programmed control sequence at a reduced frame rate. RSTZ initialized the chip with the default register values. SPREAD SPECTRUM SUPPORT The FPD-Link receiver supports graphics controllers with Spread Spectrum interfaces for reducing EMI. The Spread Spectrum method supported is Center Spread. A maximum of 2% Center Spread is supported at a frequency modulation of 200kHz maximum. 8–6 BIT TRANSLATOR 8-bit data is reduced to a 6-bit data path via a time multi- plexed dithering technique or simple truncation of the LSBs. This function is enabled via the Input Control Register bits [4,3]. Care should be taken in providing the correct input color mapping (see Figure 4) DATAPATH BLOCK AND RSDS TRANSMITTER 6-bit video data (RGB) is input to the Datapath Block at a 65 MHz rate. The data is delayed to align the Column Driver Start Pulse (SP) with the Column Driver data. The data (RSR[2:0]P/N, RSG[2:0]P/N, RSB[2:0]P/N) is output at a 130 MHz rate on 9 differential output channels (9 pairs of outputs). The clock is output on the RSCKP/N differential pair. The RSDS Column Drivers latch data on both positive and negative edges of the clock. VERTICAL AND HORIZONTAL COUNTER The counter block provides control to the Column Drivers, Row Drivers, and power supply as GPOs (General Purpose Outputs). Several video input formats are supported; Video timing which is fixed vertically, and horizontally (ENAB is ig- nored); Video timing which is fixed vertically, but uses ENAB for horizontal positioning; ENAB Only Mode which uses ENAB to position both vertically and horizontally. The FIX- _VERT and FIX_HORIZ along with internal ENAB detection circuitry; control the operational mode. The fixed vertical and horizontal position points are programmable. TIMING CONTROL The Timing Control function generates control to Column Drivers, Row Drivers, and power supply. The programmable GPOs (General Purpose Outputs) provide for CD latch pulse, REV, and Row Driver control generation. The General Purpose Outputs allow the user to generate control anywhere within the frame data. Standard Row Driver interface or Custom Row Driver interfaces can be implemented with the 10 GPOs (General Purpose Outputs). Note that GPO[9] must be used for output blanking control. THE GENERAL PURPOSE OUTPUTS Five registers provide the timing definition for each GPO.
- The Horizontal Start Register defines the output pixel number for which the GPO output goes active.
- The Horizontal Duration Register determines how many clocks the output will remain active during the line.
- The Vertical Start Register defines at what line# the out- put become active.
- The Vertical Duration Register defines how many lines the output remains active. DS101077-3 FPD87310 www.national.com9
dicating EEPROM not present), the internal default values are used. Pull-Up must be used on EE_SD pin if external EEPROM is not used. The following parameters are initialized at power up. TABLE 1. FPD87310 Programmable Register Definition input and output interfaces. GPO[9] must be programmed to> 768 lines for data to be output. H , 086H # of 65 MHz clocks after the falling edge of HYSYNC until start of video. H , 088H # of HSYNC from VSYNC falling edge until start of video.
TABLE 1. FPD87310 Programmable Register Definition(Continued) input and output interfaces. Duration) define the control timing relative to the Internal line and pixel counters. Output can be uniquely configured. See the GPO programming examples for details.
- GPO[9]: provides programmable data and clock blanking.
TABLE 1. FPD87310 Programmable Register Definition(Continued) input and output interfaces. the Vertical Duration Register is overwritten. “1” - Early Start capability. lines/frames (auto-detected) to determine the vertical start position. [4:3] GPO[9:1] Combination Select. “00” - Select GPO[x] as programmed. (No combination function). “01” - Select GPO[x] “ANDed” with GPO[x-1]. “10” - Select GPO[x] “ORed” with GPO[x-1]. “11” - Select GPO[x] and GPO[x-1] on alternating frames. [6:5] Power-up sequence delay. “00” - Outputs active after 1st VSYNC after EEPROM download. “01” - Outputs active after 2nd VSYNC after EEPROM download. “10” - Outputs active after 3rd VSYNC after EEPROM download. “11” - Outputs actve after 4th VSYNC after EEPROM download. TABLE 2. Internal Default Register Values and EEPROM Memory Map
56 E4 8 GPO9 Control Register reg_gpo9_cont 30 09
55 E3 E2 11 GPO9 Vertical Duration reg_gpo9_Icount 00 00 00 00
54 E1 E0 11 GPO9 Vertical Start reg_gpo9_Istart 00 01 00 01
53 DF DE 11 GPO9 Horizontal Duration reg_gpo9_pcount 00 40 00 40
52 DC DD 11 GPO9 Horizontal Start reg_gpo9_pstart 03 86 03 86
51 DB 8 GPO8 Control Register reg_gpo8_cont 21 09
50 DA D9 11 GPO8 Vertical Duration reg_gpo8_Icount 00 00 00 01
49 D8 D7 11 GPO8 Vertical Start reg_gpo8_Istart 00 01 00 01
48 D6 D5 11 GPO8 Horizontal Duration reg_gpo8_pcount 00 00 00 40
47 D4 D3 11 GPO8 Horizontal Start reg_gpo8_pstart 00 01 01 C2
46 D2 8 GPO7 Control Register reg_gpo7_cont 00 09
45 D1 D0 11 GPO7 Vertical Duration reg_gpo7_Icount 00 00 00 01
44 CF CE 11 GPO7 Vertical Start reg_gpo7_Istart 00 00 00 01
43 CD CC 11 GPO7 Horizontal Duration reg_gpo7_pcount 00 00 00 40
TABLE 2. Internal Default Register Values and EEPROM Memory Map(Continued)
42 CB CA 11 GPO7 Horizontal Start reg_gpo7_pstart 00 00 01 42
41 C9 8 GPO6 Control Register reg_gpo6_cont 00 09
40 C8 C7 11 GPO6 Vertical Duration reg_gpo6_Icount 00 00 00 01
39 C6 C5 11 GPO6 Vertical Start reg_gpo6_Istart 00 00 00 01
38 C4 C3 11 GPO6 Horizontal Duration reg_gpo6_pcount 00 00 00 40
37 C2 C1 11 GPO6 Horizontal Start reg_gpo6_pstart 00 00 00 C2
36 C0 8 GPO5 Control Register reg_gpo5_cont 00 01
35 BF BE 11 GPO5 Vertical Duration reg_gpo5_Icount 00 00 00 01
34 BD BC 11 GPO5 Vertical Start reg_gpo5_Istart 00 00 00 01
33 BB BA 11 GPO5 Horizontal Duration reg_gpo5_pcount 00 00 00 40
32 B9 B8 11 GPO5 Horizontal Start reg_gpo5_pstart 00 00 00 42
31 B7 8 GPO4 Control Register reg_gpo4_cont 00 00
30 B6 B5 11 GPO4 Vertical Duration reg_gpo4_Icount 00 00 00 00
29 B4 B3 11 GPO4 Vertical Start reg_gpo4_Istart 00 01 00 01
28 B2 B1 11 GPO4 Horizontal Duration reg_gpo4_pcount 00 50 00 50
27 B0 AF 11 GPO4 Horizontal Start reg_gpo4_pstart 03 FA 03 FA
26 AE 8 GPO3 Control Register reg_gpo3_cont 00 20
25 AD AC 11 GPO3 Vertical Duration reg_gpo3_Icount 00 00 00 00
24 AB AA 11 GPO3 Vertical Start reg_gpo3_Istart 00 01 00 01
23 A9 A8 11 GPO3 Horizontal Duration reg_gpo3_pcount 02 A0 00 00
22 A7 A6 11 GPO3 Horizontal Start reg_gpo3_pstart 03 86 00 02
21 A5 8 GPO2 Control Register reg_gpo2_cont 00 01
20 A4 A3 11 GPO2 Vertical Duration reg_gpo2_Icount 00 01 00 01
19 A2 A1 11 GPO2 Vertical Start reg_gpo2_Istart 00 01 00 01
18 A0 9F 11 GPO2 Horizontal Duration reg_gpo2_pcount 05 46 00 A0
Symbol Pin Count Type Function RxIN[0]+/− 2 LVDSI FPD-Link Data Differential Pair 0 Input RxIN[1]+/− 2 LVDSI FPD-Link Data Differential Pair 1 Input RxIN[2]+/− 2 LVDSI FPD-Link Data Differential Pair 2 Input RxIN[3]+/− 2 LVDSI FPD-Link Data Differential Pair 3 Input (Used in 8 Bits Video Application) RxCLK+/− 2 LVDSI FPD-Link Clock Differential Pair Input RSTZ 1 STI Reset Input, Active Low COLUMN DRIVER INTERFACE Symbol Pin Count Type Function RSR[2:0]P/N 6 RSDSO Red Reduced Swing Differential Outputs to Column Drivers RSG[2:0]P/N 6 RSDSO Green Reduced Swing Differential Outputs to Column Drivers RSB[2:0]P/N 6 RSDSO Blue Reduced Swing Differential Outputs to Column Drivers RSCKP/N 2 RSDSO Clock Reduced Swing Differential Outputs to Column Drivers SP 1 TO Start Pulse Output to Column Driver DS101077-2 Thin Quad Flatpak (TQFP80) FPD87310 www.national.com 18
Pin Description(Continued) Symbol Pin Count Type Function PI 1 I Reference for Reduced Swing Differential Outputs GENERAL PURPOSE OUTPUTS Symbol Pin Count Type Function GPO[9:0] 10 TO/OD General Purpose Outputs (Programmable) EEPROM INTERFACE Symbol Pin Count Type Function EE_SD 1 I/OD EEPROM Serial Data EE_SC 1 OD EEPROM Clock POWER SUPPLY Symbol Pin Count Type Function VDD A 1 P FPD-Link PLL and Bandgap Power VDD D 2 P FPD-Link Receiver Power VDD 5 P Digital Power VDD IO 6 P Digital I/O Power VSS P 1 G FPD-Link PLL Ground VSS A 1 G FPD-Link Bandgap Ground VSS D 1 G FPD-Link Receiver Ground VSS 5 G Digital Ground VSS IO 6 G Digital I/O Ground TEST/CONFIGURATION Symbol Pin Count Type Function FIX_VERT 1 I Selects VSYNC or ENAB for Vertical Timing ”0” = ENAB Vertical Timing ”1” = VSYNC Vertical Timing FIX_HORIZ 1 I Selects HSYNC or ENAB for Horizontal Timing “0” = ENAB Horizontal Timing “1” = HYNC Horizontal Timing TEST[0,1,2,4,5] 5 I Test/Configuration Pins TEST[0]-Must be “0” TEST[1]-Must be “0” TEST[2] EEPROM Init Value Download Control “0” - Downloaded every 5 frames “1” - Downloaded once at Power-Up TEST[4]-Must be “0” TEST[5]-Must be “0” Pin Type Legend I TTL Input STI Schmitt Trigger TTL Input I/TO TTL Input/TRI-STATE ® Output TO TRI-STATE Output OD Open Drain Output LVDSI Low Voltage Differential Signal Input RSDSO Reduced Swing Differential Sgnal Output P Power G Ground Appendix A: GPO (General Purpose Output) Programming Examples The GPO control generation is based on the internal line count and pixel count shown inFigures 16, 17. Two pro- grammable registers (Vertical Start and Vertical Duration) control the vertical component of the control signal. This es- tablishes at what line and for how many lines the control sig- FPD87310 www.national.com19
Component generates pulses within that vertical time period.
- A pulse once a frame (either in pixels or lines)
- Pulsed during active video (pulses are blanked during
vertical blanking period of frame). signals are included in the following pages. TABLE 3. GPO Pulse Generation and lasting for #D pixel clocks. 4# A # B # C # D Pulse generation begins at line #A and continue for #B lines. Note 5:GPO[0]: provides for the data inverting function enabled by bit[3] of the Output Format Control Register. RSB[2:0]P/N, RSCKP/N and SP).
alternates polarity each frame. This control signal is used as the reversal signal. Positive going pulse causes output to toggle. be in toggle mode, but it cannot be “0”. circuitry is enabled (bit[1] = “1”). ues, signal are negative. (bit[0] = “1”). FIGURE 25. Example #4c: GPO Vertical Scope View
Appendix A: GPO (General Purpose Output) Programming Examples (Continued) Special Function GPOs FPD87310 has been provided two special purpose GPOs for manipulating the Output RGB Data, also the Clock and SP output can be controlled by GPO[9]. 1. GPO[0] Output Data Inverting. Output _Format_Control_Register bits[4:3] 2. GPO[9] Output Data Blanking. Input_Format_Control_Register bits[7:6] FPD87310 www.national.com 24
TABLE 4. GPO[0] Inverting and GPO[9] Blanking Logical Function TABLE 5. GPO[9] Blanking for Clock and SP FIGURE 26. GPO[0] Inverting and GPO[9] Blanking Method
FIGURE 27. GPO (General Purpose Output) Generation Method
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