FPD87208

FPD87208_13 TI1 | Alldatasheet

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RSDS CD RSDS CD RSDS CD RSDS CD n n n n R A . An R E . En XGA 1024 X 768 WXGA 1280 X 768/800/854 TFT-LCD Array Gray Scale Voltage Reference BUS Line Transfer Signal, Inversion Control /9 + CLK, RSDSa BUS Start Pulse Start Pulse Gray scale Reference Panel Power Supply VDD GND Gate Clock Out enable XGA/WXGA Panel Timing Controller FPD87208AXA Integrated LVDS Receiver /2 LinkCLK /2 Link[2] /2 Link[1] /2 Link[0] FPD-Link .- - OBSOLETE FPD87208 www.ti.com SNOSAC5C –APRIL 2004–REVISED APRIL 2013 FPD87208AXA+2.5VLowEMI,LowDynamicPowerXGA/WXGATFT-LCDTiming ControllerwithReducedSwingDifferentialSignalingRSDS™ Outputs Check forSamples: FPD87208 1FEATURES DESCRIPTION The FPD87208AXA is a timing controllerthat 23• Reduced Swing DifferentialSignaling(RSDS) combines an LVDS singlepixelinputinterfacewithTIDigitalBus Reduces Dynamic Power, EMI and Reduced Swing DifferentialSignaling(RSDS ™ )Bus-Width from theTiming Controller output driverinterfacefor XGA and Wide XGA

• LVDS SinglePixelInputInterfaceSystem resolutions.Itresideson the TFT-LCD panel and provides the data bufferingand controlsignal• InputClock Range from 25 MHz to85 MHz generationforXGA, and Wide XGA graphicmodes.• DrivesRSDS Column Driversat170 Mb/s with The RSDS path to the column drivercontributesan 85 MHz Clock (Max) toward loweringradiatedEMI and reducingsystem
• BIST Function dynamicpower consumption.
• CMOS CircuitryOperates from a 2.25V–2.75V; ThissingleRSDS bus conveysthe6-bitcolordatafor0°C –70°C XGA, and threedifferentWXGA resolutions.
• 64 TQFP Package withBody Size10 mm x 10 mm x 1.0mm System Diagram Figure1. Block Diagram oftheLCD Module These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2RSDS isa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2004–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNOSAC5C –APRIL 2004–REVISED APRIL 2013 www.ti.com AbsoluteMaximum Ratings (1)(2) SupplyVoltage(VDD ) −0.3Vto+3.0V DC TTL InputVoltage(VIN) −0.3Vto(VDD + 0.3V) DC LVDS InputVoltage(VIN) −0.3Vto(VDD + 0.3V) DC OutputVoltage(VOUT ) −0.3Vto(VDD + 0.3V) JunctionTemperature +150°C StorageTemperatureRange (TSTG ) −65°C to+150°C Lead Temperature(TL)(Soldering10 sec.) 260°C HBM: R ZAP = 1.5kΩ,C ZAP = 100 pF 2 kV ESD Rating MM: R ZAP = 0Ω,C ZAP = 200 pF 200V (1) AbsoluteMaximum Ratingsarethosevaluesbeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimplythat thedevicesshouldbe operatedattheselimits.The tableofElectricalCharacteristicsspecifiesconditionsofdeviceoperation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. OperatingConditions Min Max Units SupplyVoltage(VDD ) 2.25 2.75 V OperatingTemp. Range (TA) 0 70 °C SupplyNoiseVoltage 200 mV PP DC ElectricalCharacteristicsTTL DC ElectricalCharacteristics VDD = 2.5V±0.25V,TA = 0°C to70°C, IPI = 100 µA (Unlessotherwisespecified) Symbol Parameter Conditions Min Typ Max Units VDD SupplyVoltage 2.25 2.5 2.75 VIH Minimum InputHighVoltage 1.8 V VIL Maximum InputLow Voltage 0.7 V VOH OutputHighVoltage IOH = −8 mA 0.8x VDD VOL OutputLow Voltage IOL = 8 mA 0.4 IIN VIN = VDD 10 µA InputCurrent VIN = GND 10 µA IDD CLK = 85 MHz, RPI = 12.3k C L(TTL)= 50 pF, 80 120R L(RSDS) = 100Ω andAverageSupplyCurrent IP = 100 µA IP = 100 µA mAC L(RSDS) = 5 pF VDD = 2.5V VDD = 2.75V(jig& testfixturecapacitance), See Figure3 forinputconditions

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HSYNCVSYNCENAB HSYNCVSYNCENAB1 0 0 11 1 ...0 ...1 0 0 11 10 0 0 1 1 0 0 ...1 0 0 11 10 0 0 1 1 0 0 RxIN[2] RxIN[1] RxIN[0] T/7 T/7 T/7 T/7 T/7 T/7 T/7 1 cyclePrevious cycle Next cycle RxCLKIN VDIFF = 0V VDIFF = 0V VCM = 1.25V 600 mV VDD - 0.4V GND VCM = (1.25V); |VID| = 350 mV Typical Application VCM = 50 mV VCM = 300 mV |VID| = 100 mV VCM range with Minimum |VID| 1.425V |VID| = 350 mV 1.075V 100 mV |VID| = 100 mV |VID| = 600 mV VCM range with Maximum |VID| VDD - 1.0V |VID| = 600 mV |VID| = 600 mV VDD - 0.4V |VID| = 100 mV VDD - 0.50V VCM = (VDD - 0.4V) - |VID|/2 VCM = (VDD - 0.4V) - |VID|/2 OBSOLETE FPD87208 www.ti.com SNOSAC5C –APRIL 2004–REVISED APRIL 2013 DC ElectricalCharacteristicsFPD-Link (LVDS) ReceiverInput(RxCLKP/N; RxIN[y]P/N,y = 0,1,2) Symbol Parameter Conditions Min Typ Max Units LVDS RECEIVER DC SPECIFICATIONS Note:LVDS ReceiverDC parametersaremeasured underStaticand Steadystateconditionswhichmay notbe reflectiveofits performanceintheend application.ThisdeviceiscompatiblewithTIA644 SPEC. V0 and V2.4. VTH LVDS DifferentialInputH ighThreshold +100 mVVoltage VCM = 1.2V VTLLVDS DifferentialInputLow ThresholdVoltage −100 mV IIN VIN = VDD –0.4V, ±10 µAVDD = 2.75VINputCurrent VIN = 0V,VDD = 2.75V ±10 µA VIN INputVoltageRange 0 VDD –0.4 V |VID| D ifferentialInputVoltage 0.100 0.600 V VCM (VDD –0.4)−C ommon M ode VoltageOffset 0 + |VID|/2 V|VID|/2 LVDS VID and VCM AllowableOperatingRange Figure2. |VID|and VCM Definitions FPD-Link ReceiverInputPatternUsed toMeasure IDD Figure3. FPD-Link ReceiverIDD Pattern Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:FPD87208

R PI (k:) 200 300 400 500 600 700 800 900 1000 VOD (mV) 106 14 18 VDD = 2.75V VOD vs. RPI VDD = 2.25V VDD = 2.5V VOUT P GND GND +200 mV +200 mV -200 mV -200 mV VOD RSDS Single Ended Differential VOS RSDS VOUT N (VOUT P)-(VOUT N) OBSOLETE FPD87208 SNOSAC5C –APRIL 2004–REVISED APRIL 2013 www.ti.com DC ElectricalCharacteristicsRSDS Output (CLKP/N,xyP/N;x = R, G, B;y = 0,1,2),VDD = 2.25Vto2.75V(Unlessotherwisespecified) Symbol Parameter Conditions Min Typ Max Units |VOD RSDS | DifferentialOutputVoltageTyp. R L = 100Ω 200 (Figure4) mV IPI = 100 µAVOS RSDS OffsetVoltage 1.2 V Figure4. RSDS Output Waveforms: SingleEnded vs Differential Figure5. TypicalRSDS VOD vs R PI Response Curve

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Vdiff = 0VRxIN[3:0] Ideal Rx Strobe Position SW RSM (rightside) RSPOS max Ideal Tx Pulse Position Ideal Tx Pulse Position RSM (leftside) RSPOS min Acronyms: RSM RSPOS SW Definitions: SW R eceiver Strobe M argin R eceiver Strobe Pos ition Strobe W idth Setup and Hold Time (Internal data sampling window) VSS VDD VI VSS VDD VO VT- VT+ VH VT- VT+ VH VH = VT+ - VT- VO VI OBSOLETE FPD87208 www.ti.com SNOSAC5C –APRIL 2004–REVISED APRIL 2013 DC ElectricalCharacteristicsSchmittTrigger Symbol Parameter Conditions Min Typ Max Units VH HysteresisVoltage VT+ – VT− 0.4 V VT− HysteresisLow ThresholdVoltage 1.2 V VT+ HysteresisHighThresholdVoltage 1.6 V IINHYS VIN = VDD 20 µA InputCurrent VIN = VSS −20 0 µA Figure6. HysteresisDefinition AC ElectricalCharacteristics LVDS Data InputR T = 100Ω,IPI = 100 µA, f= 85 MHz (Unlessotherwisespecified) TA = 0°C to70°C, VDD = 2.5V±0.25V,IPI = 100 µA (Unlessotherwisespecified) Symbol Parameter Conditions Min Max Units FRXCLK RxCLK Frequency(LVDS) 25 85 MHz RPLLS FPD-LinkReceiverPhase Lock Loop Wake-Up Time 10 ms RMS RxIN StrobeMargin(1)and (Figure7) F = 85 MHz 400 ps (1) ReceiverStrobeMarginisdefinedas thevaliddatasamplingregionatthereceiverinputs. Figure7. FPD-Link ReceiverInputSkew Margin Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:FPD87208

(SSCTR=H) RPLLS VDD Case A

0.9 VDD

(SSCTR=H) RPLLS VDD Case B R = 14.5 k: FPD87208AXA21 OBSOLETE FPD87208 SNOSAC5C –APRIL 2004–REVISED APRIL 2013 www.ti.com Table1.Ring OscillatorCharacteristicsR T = 100Ω,IPI = 100 µA, f= 85 MHz (Unlessotherwisespecified) Symbol Parameter Conditions Min Typ Max Units RESOSC RingOscillator R = 14.5KΩ;VDD = 40 MHzClockFrequency 2.5V Figure8. Applicationdiagram ofRing Oscillator Figure9. FPD-Link ReceiverPhase Lock Loop Wake-Up Time

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ENABB[4] G[3] R[2] VSYNC HSYNC ENAB VSYNC T/7 T/7 T/7 T/7 T/7 T/7 T/7 RxIN[2] RxIN[1] RxIN[0] 1 cyclePrevious cycle Next cycle RxCLKIN RCOP(T) VDIFF = 0V VDIFF = 0V OBSOLETE FPD87208 www.ti.com SNOSAC5C –APRIL 2004–REVISED APRIL 2013 Note:R/G/B[7]sareMSBs and R/G/B[0]sareLSBs Figure10. FPD-Link ReceiverInputData Mapping Table2.Output Timing R T = 100Ω,IPI = 100 µA, f= 85 MHz (Unlessotherwisespecified) Symbol Parameter Conditions Min Typ Max Units RCHP RSDS Clock(RSCK) HighPeriod C L(RSDS) = 5 pF 5.8 ns RCLP RSDS Clock(RSCK) Low Period C L(RSDS) = 5 pF 5.8 ns SPSTU STH RisingtoRSCK Falling 4.0 ns C L(TTL)= 15 pF SPHLD STH FallingtoRSCK Falling 4.0 ns RSTU (1) RSDS SetuptoFallingorRisingEdge 3.3 nsofRSCK C L(RSDS) = 5 pF RSDS[2:0]=[011]RHLD (1) RSDS HoldfromFallingorRising 2.1 nsEdge ofRSCK (1) Refertothetable“RSDS Setupand HoldTime withData Skew ControlValues”foreach skew control. Table3.RSDS Setup and Hold Time withData Skew ControlValues— ReferenceOnly (RxCLKP/N = 85 MHz, R T = 100Ω,IPI = 100 µA, VDD = 2.5V;Duty Clock = 50%/50%, ±2%; 25°C)(1) Setup Time (RSTU, nS) Hold Time (RHLD, nS) RSDS[2:0] Units Min Typ Max Min Typ Max 000 1.83 3.61 001 2.33 3.09 010 2.83 2.61 011 3.31 2.10 ns 100 3.85 1.55 101 4.34 1.03 110 4.81 0.53 111 5.33 0.01 (1) Typicalvalueson thistablearemeasured underStaticand Steadystateconditionswhichmay notbe reflectiveofitsperformanceinthe end application. Table4.RSDS and TTL Output Tr/Tf Symbol Parameter Conditions Min Typ Max Units RSTr/RSTf RSDS OutputRising/FallingTime (All C L(RSDS) = 5 pF 1.5 nsRSDS Outputs) TTL Tr/Tf TTL OutputRisingand FallingTime C L = 15 pF (20%–80%) 2.0 ns Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:FPD87208

2.0V 2.0V RSCKP/N STH RSR[2:0]P/N RSG[2:0]P/N RSB[2:0]P/N EVEN ODDInvalid Data RSTU RSTURHLD (differential RSDS signal) (single ended TTL signal) 1st Pixel Data RHLD R T = 100: RSCKP/N RSR[2:0]P/N RSG[2:0]P/N RSB[2:0]P/N RSDS N(egative) Output RSDS P(ositive) Output IPI = 100 PA (Source Current) PI (Typically with RPI = 12.3 k:) C L(RSDS) = 5 pF C L(TTL) TTL Outputs TTLOUT (Typically IRSDS = 20 x IPI) 10% 10% 90% 90% Tr Tf TTL Out RSTr RSTf RSDS Out -120 mV -120 mV +120 mV OBSOLETE FPD87208 SNOSAC5C –APRIL 2004–REVISED APRIL 2013 www.ti.com Figure11. RSDS and TTL Output Timing Diagram

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1st Data 2nd Data 3rd Data 0V0V 0V RSTU RHLDRSTU RHLD 2.0V SPHLDSPSTU 2.0V RSB[2]P/N RSB[1]P/N RSB[0]P/N RSG[2]P/N RSG[1]P/N RSG[0]P/N RSR[2]P/N RSR[1]P/N RSR[0]P/N Note: RSCKP/N, RSR[2:0]P/N, RSG[2:0]P/N and RSB[2:0]P/N are differential outputs, STH is a single ended TTL output. OBSOLETE FPD87208 www.ti.com SNOSAC5C –APRIL 2004–REVISED APRIL 2013 Figure12. RSDS Output Data Mapping Table5.InputSignalTiming— ReferenceOnly XGA WXGA1 WXGA2 WXGA3Signal Item Symbol Unit(1024x 768) (1280x 768) (1280x 800) (1280x 854) Clock 1/Tclk F Typ 65 82 68 69 MHzFrequency Min 774 774 806 860 Total Tv Typ 806 806 816 880 Max 1024 1024 1024 1024Vertical ThTiming Min - - - - Active Tvact Typ 768 768 800 854 Max - - - - Min 1078 1334 1334 1334 Total Th Typ 1344 1688 1408 1408 Max 2047 2047 2047 2047Horizontal TclkTiming Min 100 100 100 100 Active Thact Typ 1024 1280 1280 1280 Max - - - - Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:FPD87208

SNOSAC5C –APRIL 2004–REVISED APRIL 2013 www.ti.com Output Timing— TTL Table6.DisplayResolutionSelectionControl DTM1 DTM0 DisplayMode Resolution 0 0 WXGA1 1280 x 768 0 1 WXGA2 1280 x 800 1 0 XGA 1024 x 768 1 1 WXGA3 1280 x 854 Table7.TTL Timing SelectionControl:RO[2:0] XGA RO[2:0] 000 001 010 011 100 101 110 111 Unit T1 2 2 2 2 2 2 2 TCLK T2 1 1 1 1 1 1 1 TCLK T3 1030 1030 1030 1030 1030 1030 1030 TCLK T4 16 24 16 24 32 48 42 TCLK T5 912 960 960 912 842 912 802 TCLK T5′ 782 830 830 782 712 782 672 TCLK T6 200 160 160 130 220 220 260 TCLK T6′ 130 130 130 130 130 130 130 TCLKTEST MODET7 1038 1056 1056 976 874 976 834 TCLK T8 650 650 650 650 680 680 725 TCLK T9 348 348 348 348 348 348 348 TCLK T10 1 1 1 1 1 1 1 HLINE T11 348 348 348 348 348 348 348 TCLK T12 1 1 1 1 1 1 1 HLINE T13 (1) 567 567 567 567 567 567 567 TCLK T14 (1) 2 2 2 2 2 2 2 HLINE (1) Timingbased on firstoccurrenceofSTH. WXGA RO[2:0] 000 001 010 011 100 101 110 111 Unit T1 2 2 2 2 2 2 2 TCLK T2 1 1 1 1 1 1 1 TCLK T3 1286 1286 1286 1286 1286 1286 1286 TCLK T4 16 24 16 24 32 48 42 TCLK T5 1168 1216 1216 1168 1098 1168 1058 TCLK T5′ 1038 1086 1086 1038 968 1038 928 TCLK T6 200 160 160 130 220 220 260 TCLK T6′ 130 130 130 130 130 130 130 TCLKTEST MODET7 1294 1312 1312 1232 1130 1232 1090 TCLK T8 650 650 650 650 680 680 725 TCLK T9 348 348 348 348 348 348 348 TCLK T10 1 1 1 1 1 1 1 HLINE T11 348 348 348 348 348 348 348 TCLK T12 1 1 1 1 1 1 1 HLINE T13 (1) 567 567 567 567 567 567 567 TCLK T14 (1) 2 2 2 2 2 2 2 HLINE (1) Timingbased on firstoccurrenceofSTH.

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(1HRVS) REV (2HRVS) | | STH RGBP/N (RSDS) CLKP/N (RSDS) DE (embedded in LVDS RxIN)

595 N(H Line)

N: 768 (XGA) 768/800/854 (WXGA) 1 2 3 4 5 6 Y. 595 N OBSOLETE FPD87208 www.ti.com SNOSAC5C –APRIL 2004–REVISED APRIL 2013 Figure13. TTL Output Timing Diagram Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:FPD87208

(RSDS) CPV STV* DE (1HRVS) REV (2HRVS) REV* t12 t14 t11 t13 * Timing based on first occurrence of STH signal to the left of the measured output. t10 t6' t5' OE2 (Embedded in LVDS RxIN) || | OBSOLETE FPD87208 SNOSAC5C –APRIL 2004–REVISED APRIL 2013 www.ti.com Figure14. TTL Output Timing Diagram (Continued)

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32 VDD IO

31 RSR[2]P

30 RSR[2]N

29 RSR[1]P

28 RSR[1]N

27 RSR[0]P

26 RSR[0]N

25 VSS IO

24 VDD IO

22 RESOSC

21 RSDS2

20 RSDS1

19 RSDS0

18 RSTZ

17 VSS IO

RXIN[0]N 3 RXIN[0]P 4 RXIN[1]N 5 RXIN[1]P 6 RXIN[2]N 7 RXIN[2]P 8 RXCLKN 9 RXCLKP 10 IDREV 11 BIST 12 VDD A 13 VSS A 14 VSS P 15 VDD IO 16

48 VDD IO

47 RSB[2]P

46 RSB[2]N

45 RSB[1]P

44 RSB[1]N

43 RSB[0]P

42 RSB[0]N

35 RSCLKP

34 RSCLKN

33 VSS IO

64 PIN TQFP

RSG[2]P RSG[2]N RSG[1]P RSG[1]N RSG[0]P RSG[0]N 1st Frame VDD LVDS IN Control Signals RESET STV OE2 Max. 10 ms LVDS Rx PLL Wake-up Time 2nd 5th 6th RGB Out OE1 OE Signal Normal Out- OE Signal Normal Out- Data Signal Normal Out-Invalid OBSOLETE FPD87208 www.ti.com SNOSAC5C –APRIL 2004–REVISED APRIL 2013 Output Timing— Power-Up Sequence (referenceonly) Figure15. Power-Up Sequence Connection Diagram Figure16. PinoutAssignment Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:FPD87208

SNOSAC5C –APRIL 2004–REVISED APRIL 2013 www.ti.com Pin Descriptions Table8.LVDS Rx Inputs PinSymbol Type FunctionCount RxIN[0]N/P 2 LVDSI LVDS Rx Data DifferentialInputPairs RxIN[1]N/P 2 LVDSI LVDS Rx Data DifferentialInputPairs RxIN[2]N/P 2 LVDSI LVDS Rx Data DifferentialInputPairs RxCLKN/P 2 LVDSI LVDS Rx ClockDifferentialInputPairs Sub-Total 8PinCount Table9.RSDS Tx Outputs PinSymbol Type FunctionCount R [2:0]P/N 6 RSO Red Reduced Swing DifferentialOutputstoColumn Drivers G [2:0]P/N 6 RSO Green Reduced Swing DifferentialOutputstoColumn Drivers B [2:0]P/N 6 RSO BlueReduced Swing DifferentialOutputstoColumn Drivers CLKP/N 2 RSO ClockReduced Swing DifferentialOutputstoColumn Drivers Sub-Total 20PinCount Table10.RSDS Tx Bias ReferenceInput PinSymbol Type FunctionCount PI 1 CurrentReferenceforRSDS Tx Output(1.23V) Sub-Total 1PinCount Table11.CMOS Input(2.75VMaximum) PinSymbol Type FunctionCount RSDS[2:0] 3 I RSDS Skew/TimingControl RO[2:0] 3 I DisplayTimingSelection POLSET 1 I 0:Two LineInversion;1:One LineInversion DTM[1:0] 2 I DisplayMode Selection(XGA, WXGA1, WXGA2, WXGA3) RESOSC 1 AI RC oscillatorreferenceforBIST function. 14.5kΩ = ∼40 MHz IDREV IDREV = HIGH (default,pullhigh):Outputdatais3F duringverticalblanking.IDREV =1 PU LOW: Outputdatais00 duringverticalblanking. BIST 1 I BIST ControlFunction(ActiveHigh),tiedtogroundfornorm mode RESETZ 1 SchmittI TCON Reset(ActiveLow) Sub-Total 13PinCount

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www.ti.com SNOSAC5C –APRIL 2004–REVISED APRIL 2013 Table12.CMOS Outputs (2.75VMaximum) PinSymbol Type FunctionCount STV 1 TO Row DriverStartPulse CPV 1 TO Row DriverShiftClock TP 1 TO LineLatchSignalOutputtoColumn Drivers STH 1 TO HorizontalStartSignalOutputtoColumn Drivers REV 1 TO AlternativeSignalOutputforeach 1 or2 HorizontalLinetoColumn Drivers OE1 1 TO ControlTFT Gate PulseWidthtoRow Drivers OE2 1 TO ControlTFT Gate PulseWidthtoRow Drivers Sub-Total 7PinCount Table13.Power Supply PinSymbol Type FunctionCount VDD 1 P DigitalPower forLogicCore VSS 1 G DigitalGround forLogicCore VDDIO 4 P DigitalI/Oand RSDS Power VSSIO 4 G DigitalI/Oand RSDS Ground VDDA 1 P FPD Receiver— Power forAnalog VDDD 1 P FPD Receiver— Power forDigital VSSD 1 G FPD Receiver— Ground forDigital VSSP 1 G FPD Receiver— Ground forPLL VSSA 1 G FPD Receiver— Ground forAnalog Sub-Total 15PinCount TotalPin System Interface= 8 Count RSDS Tx Out = 20 RSDS Tx BiasReferenceInput= 164 CMOS Input(control)= 13 CMOS Output= 7 Power Supply= 15 Pin Types AI -AnalogInput I -Input(LVTTL) TO -TTL Output(LVTTL) LVDSI -Low VoltageDifferentialSignalInput RSO -Reduced Swing DifferentialOutput P -Power G -Ground PD -PullDown PU -PullUp SchmittI-SchmittTriggeredInput Copyright© 2004–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:FPD87208

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REVISION HISTORY

Changes from RevisionB (April2013)toRevisionC Page

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