FPD85308 NSC | Alldatasheet
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Features
n FPD-Link System Interface utilizes Low Voltage Differential Signaling (LVDS). n Supports Graphics Controllers with Spread Spectrum interfaces for lower EMI n System programmable via EEPROM n Suitable for notebook and monitor applications n 8-bit or 6-bit system interface n XGA or SVGA capable n Supports single or dual port column drivers n Programmable outputs provide customized control for standard or in-house column drivers and row drivers n Programmable slew rate controlled outputs on CD interface for reduced EMI n Polarity pin reduces CD data bus switching n CMOS circuitry operates from a 3.3V supply System Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. DS101356-1 PRELIMINARY May 2001 FPD85308 Panel Timing Controller © 2001 National Semiconductor Corporation DS101356 www.national.com
Distributors for availability and specifications. Characteristics” specifies conditions of device operation. Note 2:This limit assumes a maximum cable skew of 350 ps. Actual automated test equipment limit is 400 ps due to tester accuracy. FIGURE 1. FPD85308 (Receiver) Phase Lock Loop Set Time
FIGURE 11. GPO Control Generation
Device SpecificationsTA = 0˚C to 70˚C, VDD = 3.3V (unless otherwise specified) (Continued) Block Diagram FPD85308 Default Timing DS101356-22 Vertical Backporch = 35 Lines/Frame =∼825 Pixels/Line =∼1200 Horizontal Backporch =∼100 Displayed pixels/line = 1024 (Valid data during ENAB High time) Displayed lines/frames = 768 Frequency = 65 MHz (or less) DS101356-3 FPD85308 www.national.com 8
The LVDS based FPD-Link Receiver receives inputs video data and control timing. Four LVDS channels plus clock provide 24-bit color. Three LVDS channels can be used for 18-bit color. The video data is regenerated to a parallel data stream and routed to the 8 to 6 Bit Translator. The General Purpose Outputs (GPOs) continue outputting the programmed control sequence at a reduced frame rate. RSTZ initialized the chip with the default register values. EEPROM configuration data is loaded if EEPROM is detected. (EEPROM address 80H = “00”). Spread Spectrum Support The FPD-Link receiver supports graphics controllers with Spread Spectrum interfaces for reducing EMI. The Spread Spectrum method supported is Center Spread. A maximum of 2% Center Spread at a modulation frequency of 200 KHz is supported. 8 to 6 Bit Translator 8-bit data is reduced to a 6-bit data path via a time multi- plexed dithering technique or a simple truncation of the LSBs. This function is enabled via the Input Control Register bits 4 and 3. See Table 2Input Format Control register. Data Alignment This function delays and aligns data to match the CD/panel architecture. Programmable selections in the Output Format Control Register bits 0 and 1 provide support for various LCD panel architectures. See Figures 12, 13, 14, 15, 16for additional explanation. Dual Bus, Single Port CD Interface When interfacing two busses to a bank of single port column drivers, the RGB data must be aligned/delayed with respect to the size of the column drivers being used. The CD Size register is programmed to support single port column drivers of up to 384 outputs (128 pixels). Dual Bus, Dual Port CD Interface When interfacing with dual port column drivers, data is sim- ply output with odd and even data on separate outputs. Single Bus, Single Port CD Interface The single bus, single port column driver interface provides support of existing SVGA systems. All data is output on a single bus. The second bus can be turned off when using this configuration. Output Formatting The output formatting function provides several capabilities to reduce noise EMI and to generate customized timing. These capabilities are selectable/programmable via the Out- put Format Control, Output Enable/Polarity Control, and Out- put Drive Control Registers. See Table 2 for specific bit definitions. Data Bus Skewing This function aligns the two output channels in either a non-skewed data format (simultaneous switching) or a skewed data format. The skewed format delays the even channel data and control by 1⁄2 clock. This reduces the number of outputs which switch simultaneously. SeeFigures 12, 13, 14, 15, 16. Data Bus Skewing is enabled by setting bit 2 in the Output Format Control register. Programmable Slew Rates Programmable edge rates allow the Data, Polarity, Start Pulse, and Clock outputs to be adjusted for better imped- ance matching for noise and EMI reduction. Bits [7:6] of the Output Enable/Polarity Control Register control OSP and ESP outputs. The Output Drive Control register control the OCLK, ECLK, ORGB/OPOL, ERGB/EPOL outputs. Polarity Generation When enabled, a polarity indication (OPOL, EPOL) is output for each data bus. When in the dual bus output configuration, if the number of transitions from pixel to pixel exceed 18 bits from a total of 36 bits, the data is then inverted and a polarity indication corresponding to that bus is set active. In the single bus (ORGB bus) applications such as SVGA, when the number of pixel to pixel transitions exceed 9 bits from a total of 18 bits, the data is inverted and the OPOL is set active. This features requires the use of a CD with a polarity input. In SKEWED dual output data bus applications, OPOL and EPOL are aligned with their respective buses and should be used as the Polarity generation input to the CD which supports dual bus/Polarity generation. In Non-Skewed dual output bus applications, OPOL is aligned with both data buses and should be used as the Polarity Generation input to the CD. The polarity function is enabled by setting bit 6 of the Output Format Control register (EEPROM address D2). The OCLK and ECLK polarity is also programmable. Inver- sion and TRI-STATE control of OCLK and ECLK is provided by bits [3:0] of the Output Enable/Polarity Control Register. The ERGB/ESP/EPOL and ORGB/OSP/OPAL outputs can be disabled (TRI-STATE) using bits [5:4] of the Output Enable/Polarity Control register. Programmable Positioning of CD Start Pulse The position of the CD Start Pulse is programmable. This allows use with column drivers having non-standard start pulse timing. The CD Start Pulse position is determined by bits [3:0] of the Output Format Control Register (EEPROM address D3). Data Blanking Data, Polarity, Start Pulse and Clock can be blanked (forced to “0”) during horizontal and/or vertical blanking periods. GPO [8] is programmed to correspond to display periods. When GPO [8] is low, outputs are forced to “0”. This reduces amount of switching over the frame time thus reducing power. See GPO programming procedure in APPENDIX A: GPO Programming Examples. Line Inversion When enabled (Bit 3 of the Output Format Register), the polarity of the output data is determined by GPO [0]. Bit 4 defines the relationship between GPO [0] and the output data. Bit 5 provides a variation of this where the Odd and Even data is of different polarity. This could be used in a system with CDs on both top and bottom of the panel in which dot inversion is desired. FPD85308 www.national.com9
Functional Description(Continued) White Data The White Data function generates all “1” data beginning at line 769 and continuing until the beginning of the next frame. This function is controlled via D6 Register Bit 7. Timing Control The Timing Control function generates control to column drivers, row drivers, and power supply. The programmable GPOs provide for CD latch pulse, REV, and gate driver control generation. The GPOs allow the user to generate control anywhere within the frame data. Standard gate driver interface or custom gate interfaces can be implemented with the nine GPOs. Note that GPO [8] must be used for output blanking control. Five registers provide the timing definition for each GPO. The Horizontal Start register defines the output pixel number for which the GPO output goes active. The Horizontal dura- tion register determines how many clocks the output will remain active during the line. The Vertical Start register defines at what line # the output becomes active, and the Vertical duration register defines how many lines the output remains active. Each output has a control register (bit 0) which defines the GPO polarity (active high or low). Another bit in the control register (bit 1) enables the “toggle” mode. This mode is useful in REV generation when alternating polarity is required from line to line. Frame to Frame polarity changes are made by programming an odd # in the vertical duration register when in “toggle” mode. Please note that ODD Frame size inputs are not supported in ’’toggle mode’’ function. Two of the General Purpose Outputs have additional capa- bilities. GPO [8] controls output blanking and must be used for this purpose. If output blanking is not desired, this register must be programmed to always be active. White data gen- eration (all “1” data) at the end of each frame is generated when D6 register bit 7 is set. When this bit is set, white data is output after line #768 if GPO [8] is active. GPO [0] is capable of performing line inversion on the output data. Bits [5:3] of the Output Format Control register provides control for this function. See APPENDIX A: GPO Programming Examples. SERIAL EEPROM INTERFACE The Serial EEPROM Interface controls the FPD85308 initial- ization. If the EEPROM is not present (EESD and EESC are pulled high), or if EEPROM address 80H is not “00”, the internal default values are used to initialize all programmable functions of the FPD85308. At power-up, the FPD85308 configures the internal program- mable registers with data from the EEPROM. After the FPD85308 is initialized, the EEPROM can be accessed by the system in which display configuration and manufacturing information can be obtained. The EEPROM can be pro- grammed “in system” providing quick evaluation of different display timing. External access to the EEPROM must be preceded by ap- plying a “1” to pin TEST [2] in order to interrupt the FPD85308 download. The FPD85308 initialization data begins at EEPROM ad- dress 80H. The first 128 bytes (0-7F) are reserved for dis- play identification data. A power-up delay can be programmed using bits [6:5] of the Input Format Control Register. This delays outputting (driv- ing) of the data and control for up to 5 frame times after reset. The TEST [2] pin must be low for a power-up delay to occur. VERTICAL/HORIZONTAL REFERENCE GENERATOR This block provides Vertical and Horizontal Reference points for the Timing Control Function. VSYNC, HSYNC and ENAB along with programmable control from the input control reg- ister bits 0 and 1 (FIX HORIZONTAL and FIX VERTICAL) are used to determine when the video from the host is valid. Three input modes are supported. See Table 1. Fixed Vertical, Fixed Horizontal The horizontal timing is fixed and determined by the Hori- zontal Backporch register. The vertical timing is also fixed and determined by the Vertical Backporch register. ENAB is ignored and is not necessary. Fixed Vertical, ENAB Controlled Horizontal The horizontal timing is controlled by the ENAB timing. The vertical timing is fixed and determined by the Vertical Back- porch register and HSYNC input. ENAB Only In ENAB Only timing, VSYNC and HSYNC are ignored. All timing is derived from the ENAB signal. FPD85308 www.national.com 10
TABLE 1. Input Mode Definition
TABLE 2. FPD85308 Programmable Register Definition Address The control registers provide mode setting information to the input and output interfaces.
TABLE 2. FPD85308 Programmable Register Definition(Continued) Address The control registers provide mode setting information to the input and output interfaces. Table 1for valid mode combinations.
TABLE 2. FPD85308 Programmable Register Definition(Continued) Address The control registers provide mode setting information to the input and output interfaces. configured. See the GPO programming examples for details.
TABLE 2. FPD85308 Programmable Register Definition(Continued) Address The control registers provide mode setting information to the input and output interfaces. programmed rising edge of GPO occurs. toggling, etc. up to 11 bits are set. lines/frame (auto-detected) to determine the Vertical Start position. (Examples) GPO#-1 AND GPO #, (GPO#-2 and GPO#-1) OR GPO# and etc. TABLE 3. EEPROM Memory Map
TABLE 3. EEPROM Memory Map (Continued)
TABLE 3. EEPROM Memory Map (Continued) FIGURE 12. Dual Bus Single Port Column Driver Interface
FIGURE 13. Dual Bus Single Port Column Driver Interface
FIGURE 14. Dual Bus Dual Port Column Driver Interface
FIGURE 15. Dual Bus Dual Port Column Driver Interface
Note 21:RSTZ transition Low-to-High occurs at the completion of the RPLLS delay or later as shown above. Note 22:All outputs* forced low in default timing of FPD85308 during power-up delay time. Note 23:All outputs** forced low in continuous download (every two frame) mode. NS recommend to use the continuous download mode. Note 25:EEPROM download occurs at first detected vertical blanking period. Note 26:Active outputs depends on INPUT FORMAT register bits [5:6].
00 Second VSYNC
01 Third VSYNC
10 Fourth VSYNC
11 Fifth VSYNC
default values in Fixed Vertical mode, the VSYNC signal is generated any time ENAB remains low for more than 2 horizontal periods. this situation, implementation of the circuit inFigure 19, or other functional equivalent, is recommended, (Figure 19). FIGURE 18. Power-up Sequence (INPUT FORMAT[6:5] = “01”)
FIGURE 19. Delay Circuit for Stable RSTZ
Pin No: Pin Count Pin Name I/O Description SYSTEM INTERFACE
2 RXIN_0 ± LVDI FPD-Link data pair 0
2 RXIN_1 ± LVDI FPD-Link data pair 1
2 RXIN_2 ± LVDI FPD-Link data pair 2
2 RXIN_3 ± LVDI FPD-Link data pair 3
(used in 8-bit video applications)
2 RXCLK ± LVDI FPD-Link Clock
1 RSTZ STI Reset, Active Low
1 ECLK POH Even CD Bus Clock
1 ESP POL Even Start Pulse
6 ER0..ER5 POL Even Red Bus: 6 EG0..EG5 POL Even Green Bus: 6 EB0..EB5 POL Even Blue Bus:
1 EPOL POL Even Polarity
1 OCLK POH Odd CD Bus Clock
1 OSP POL Odd Start Pulse
6 OR0..OR5 POL Odd Red Bus: 6 OG0..OG5 POL Odd Green Bus: 6 OB0..OB5 POL Odd Blue Bus:
1 OPOL POL Odd Polarity
9 GPO[8:0] TO General Purpose Outputs
1 EE_SD I/TO EEPROM Serial Data
1 EE_SC I/TO EEPROM Clock
DD A P PLL and Bandgap Supply
1 GND1 G PLL Ground
1 GNDA G Bandgap Ground
DD D P LVDS Receiver Supply
1 GNDD G LVDS Receiver Ground
4 TEST[4–0] I Test/Configuration Pins. TEST[0] — Must be “0” TEST[1] — Must be “0” TEST[2] “0” — EEPROM init values loaded every 2 frames “1” — EEPROM init values loaded once at power-up TEST[4] — Must be “0”
- I/TO — TTL Input/TRI-STATE® output
- TO — TRI-STATE output
- POL — Programmable (Low Drive)
- POH — Programmable (High Drive)
- I — TTL Input
- LVDI — Low Voltage Differential Input FPD85308 www.national.com 24
Pin Description(Continued)
- P — Power
- G — Ground STI — Schmitt Trigger Input FPD85308 www.national.com25
Component generates pulses within that vertical time period.
- A pulse once a frame (either in pixels or lines)
- Pulsed during active video (pulses are blanked during
required to toggle. This generally occurs once each line. nate polarity from frame to frame. signals are included in the following pages. TABLE 4. GPO Pulse Generation
32 MHz clocks from start of output line and lasting for
Note 29:Pulses will occur every other line if Horizontal Duration is greater than a line time.
APPENDIX A: GPO Programming Examples (Continued) GPO Programming Example #1: Generate a control signal which transitions high at the end of each line, has a pulsewidth of 3 µs, and remains low during the vertical blanking period. This control is used for the latch pulse to the column drivers. Horizontal time (clocks/line) = 1300 dot clocks Vertical period (lines/frame) = 850 lines Vertical control is active beginning at line 1 and remains active for 768 lines. GPO Vertical Start Register = 1 GPO Vertical Duration Register = 768d (300h) Positive pulse goes high each line at output clock 512 cor- responding to when the last two pixels are output on OR, OG, OB, ER, EG, EB. Pulse remains high for 98 output clocks (98 x 30.8 ns/clock = 3.02 µs). (Dual Bus output clock = 32.5 MHz for 65 MHz XGA video, 1024 pixels/line, 768 displayed lines/frame). Note:6 counts are added to the output start # because the GPO pixel count begins 6 clocks prior to the output data. GPO Horizontal Start Register = 518d (206h) GPO Horizontal Duration Register = 98d (62h) The control pulses are positive (bit [0] = 0) and the toggle circuitry is disabled (bit1 [1] = 0). GPO Control Register = 0 DS101356-23 FPD85308 www.national.com27
APPENDIX A: GPO Programming Examples (Continued) GPO Programming Example #2: Generate a control signal which transitions low 20 output clocks after the beginning of each output line, has a pulse- width (low) of 12 µs, and goes high during horizontal blank- ing. This control signal is used as an output enable for the gate drivers. Horizontal time (clocks/line) = 1300 dot clocks Vertical period (lines/frame) = 850 lines Control is active beginning at line 2 and remains active for 768 lines. GPO Vertical Start Register = 2 GPO Vertical Duration Register = 768d (300h) Negative pulse goes low each line at output clock 20 corre- sponding to when the 39/40 pixels are output on OR, OG, OB, ER, EG, EB. Pulse remains low for 390 output clocks (390 x 30.8 ns/clock = 12 µs). (Dual Bus output clock =
32.5 MHz for 65 MHz XGA video, 1024 pixels/line, 768
lines/frame). Note:6 counts are added to the output clock # because the GPO start count begins 6 clocks prior to the output data. GPO Horizontal Start Register = 26d (1ah) GPO Horizontal Duration Register = 390d (186h) The control pulses are negative (bit [0] = 1) and the toggle circuitry is disabled (bit1 [1] = 0). GPO Control Register = 1 DS101356-24 FPD85308 www.national.com 28
APPENDIX A: GPO Programming Examples (Continued) GPO Programming Example #3: Generate a control signal which toggles during horizontal blanking and alternates polarity each frame. This control signal is used as the reversal signal. Horizontal time (clocks/line) = 1300 dot clocks Vertical period (lines/frame) = 850 lines Control is active beginning at line 1 and remains active for 769 lines. (Odd number programmed in Duration Register causes con- trol signal to alternate polarity each frame) GPO Vertical Start Register = 1 GPO Vertical Duration Register = 769d (301h) Positive going pulse causes output to toggle. Edge occurs 20 output clocks after end of each line (1024/2 + 20 = 532). Pulse duration is not critical since the output will be in toggle mode. (Dual Bus output clock = 32.5 MHz for 65 MHz XGA video, 1024 pixels/line, 768 lines/frame). Note:6 counts are added to the output start # because the GPO pixel count begins 6 clocks prior to the output data. GPO Horizontal Start Register = 538 (238h) GPO Horizontal Duration Register = 10d (0Ah) The control pulses are positive (bit [0] = 0) and the toggle circuitry is enabled (bit1 [1] = 1). GPO Control Register = 2 (For a second control signal of opposite polarity, program another GPO Control Register with same count values with GPO Control Register = 3.) DS101356-25 FPD85308 www.national.com29
TABLE 5. Register Values for GPO[0:8]’s Programming TABLE 6. Register Values for LCD Format Control
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