FPD03784

FPD03784 NSC | Alldatasheet

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Technical content

Features

n Supports both XGA and SXGA timing n Supports notebook and monitor applications n Charge Conservation for low power consumption n 64 Gray levels per color (18-bit color) n Externally programmable 2.2 gamma characteristic n Supports both Dot and N-Line inversion n Externally programmable gamma characteristic n Programmable drivability allows optimization for small or large panel applications n Very low offsets for artifact-free images n High voltage outputs for high contrast in a large range of display panel applications System Diagram DS200152-1 November 2001 FPD03784 Low Power, Low EMI, TFT-LCD Column Driver with Dual, TTL Bus Inputs, 64 Grayshades, and 384 Outputs for XGA/SXGA Applications © 2001 National Semiconductor Corporation DS200152 www.national.com

Absolute Maximum Ratings(Note 1) Analog Supply, (VDD2 ) (Note 2) −0.3V to +10.5V Logic Supply, (VDD1 ) (Note 2) −0.3V to +5.0V High Bias Supply, (VHBIAS ) (Note 2) −0.3V to +12.0V Low-Polarity RDAC Reference Voltages, (VGMA7 to VGMA12 ) (Note 2) −0.3V to 0.5V DD2 High-Polarity RDAC Reference Voltages, (VGMA1 to VGMA6 ) (Note 2) 0.5VDD2 − 1.0V to VDD2 + 0.3V RDAC Current (All Gamma Voltage Taps), (IGMA to IGMA12 ) −2.5mA to 2.5mA Input Voltage (Digital Logic), (VIN) (Note 2) −0.3V to V DD1 + 0.3V Output Voltage, (VOUT ) (Note 2) −0.3V to V DD2 + 0.3V Output Current (Analog), (IOUT ) −7mA to +7mA Input Current Source, (ISIN) −200µA to +200µA Output Current Source, (ISOUT ) −200µA to +200µA IREF Current, (IREF ) −1mA to +0.2mA Storage Temperature Range, (TS) −55˚C to +125˚C Note 1:“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2:Absolute voltages referenced to V SS1 =V SS2 = 0.0V. Recommended Operating Conditions Min Typ Max Units Logic Supply Voltage 3.0 3.3 3.6 V DD1 ) (3.3V OR 2.5V) 2.25 2.5 2.75 V Supply Voltage (VDD2 ) 7.5 9.5 V Operating Temperature Digital Electrical Characteristics Symbol Parameter Conditions Min Typ Max Units VIH Input High Voltage 0.7 V DD1 V VIL Input Low Voltage 0.3 VDD1 V VOH Output High Voltage I OH = −0.5mA V DD1 − 0.5 V VOL Output Low Voltage I OL = 0.5mA 0.5 V IDD1 Logic Current (Note 3) 0.6 mA IDD1 Logic Current (Note 4) 0.36 mA IIH Input Leakage V DD1 = 3.6V, VIN = 3.6V 1 µA IIL Input Leakage V DD1 = 3.6V, VIN =0 V 1 µ A C IN Input Capacitance 2 pF Analog Electrical Characteristics Symbol Parameter Conditions Min Typ Max Units IDD2 Supply Current Consumption (Note 5) 4.0 mA PD Power Dissipation (Note 5) 40 mW V GMA1 Upper RDAC High Side Input (Note 6) V DD2 /2 + 0.2 V DD2 − 0.2 V VGMA6 Upper RDAC Low Side Input (Note 6) V DD2 /2 + 0.2 V DD2 − 0.2 V VGMA7 Lower RDAC High Side Input VDD2 ≥ 8.5V(Note 6) 0.2 V DD2 /2 − 0.2 V VDD2 < 8.5V 0.2 V DD2 /2 − 0.4 V VGMA12 Lower RDAC Low Side Input (Note 6) 0.2 V DD2 /2 − 0.2 V VHBIAS Voltage of High Bias Current Supply: VHBIAS =V DD2 VDD2 VDD2 Separate VHBIAS Supply ≥ VGMA1 + 1.5V and≥ 8.5V VDD2 + 2.0 V VCS Charge Share Voltage The Greater of VDD1 or VGMA7 VGMA6 V C LOAD Output Capacitive Load 30 80 pF VOUT Output Voltage Range V SS2 + 0.2 V DD2 − 0.2 V AIREF IREF to IMAX Gain Factor (Note 7) 8 10 12 FPD03784 www.national.com 2

Analog Electrical Characteristics(Continued) Symbol Parameter Conditions Min Typ Max Units AIHBIAS ISIN to IHBIAS Gain Factor 22.5 R CSTIME CSTIME resistance 5 12 k Ω C CSTIME CSTIME capacitance 100 150 pF ISIN Input Current Source 16 40 100 µA IREF Amplifier Reference Current 10 75 µA R DAC RDAC References (VGMA1 to VGMA6 and VGMA7 to VGMA12 ) each 12.0 15.0 18.0 k Ω Vpperr Output Peak to Peak Error (gray levels 0 through 58) VGMA1 =V DD2 − 0.2V VGMA12 =V SS2 + 0.2V (Note 8) ±3 ±12 mV Output Peak to Peak Error (gray levels 59 through 63) ±5 ±25 mV Note 5:VDD2 = 9.5V, VHBIAS = 9.5V, RIREF = 220 kΩ ,R ISIN = 470 kΩ ,V DD1 = 3.3V, DCLK = 65 MHz, RLOAD =5k Ω ,C LOAD = 50 pF, charge share time = 1.5 µs, all other swinging between VGMA1 (= 8.0V) and VGMA12 (= 0.5V) with a line time = 22 µs. Note 6:The following relationship must be maintained between the reference voltages: VDD2 >VGMA1 >VGMA2 >VGMA3 >VGMA4 >VGMA5 >VGMA6 >VGMA7 >VGMA8 >VGMA9 >VGMA10 >VGMA11 >VGMA12 >VSS2 Note 7:IMAX is the current delivered into a potential of 0.2V when the output is commanded to a potential of VDD2 − 0.2V or the current into the output from a potential of VDD2 − 0.2V when the output is commanded to 0.2V (VSS2 = 0V). Note 8:This parameter reflects the error in peak-to-peak output voltage for each gray-level when the output swings from the gray-level high value, VHxx, to its low value, VLxx. This parameter applies to every output on the die. TheTypicalvalue represents one standard deviation from ideal based on tester data. TheMaximum value is a constraint of the test environment, not the performance of the part. Note 9:Current into device pins is defined as positive. Current out of device pins is defined as negative. Digital AC Characteristics (3.3V Logic) Symbol Parameter Conditions Min Typ Max Units CLK Data Clock Frequency SINGLE = 1 (Note 10) 65.0 MHz SINGLE = 0 (Note 10) 27.5 MHz tWDCP CLK Clock Pulse Width SINGLE = 1 (Note 10) 5 ns SINGLE = 0 (Note 10) 10 ns tDSU Data Setup DX[5:0], POL, INVTxxx 4n s tDHLD Data Hold DX[5:0], POL, INVTxxx 4 ns tTWP LOAD Pulse Width 50 ns tLDENSU LOAD to First ENIO Setup (Note 11) 200 ns tENDCSU ENIOx Input to CLK Setup 2.5 ns tWEN ENIOx Input Pulse Width 10 ns tENPR ENIOx Output Prop Delay Load = 20pF 12 ns tLDLY Delay to LOAD Pulse 3 CLKs Digital AC Characteristics (2.5V Logic) Symbol Parameter Conditions Min Typ Max Units CLK Data Clock Frequency SINGLE = 1 (Note 10) 40.0 MHz SINGLE = 0 (Note 10) 17.5 MHz tWDCP CLK Clock Pulse Width SINGLE = 1 (Note 10) 10 ns SINGLE = 0(Note 10) 25 ns tDSU Data Setup DX[5:0], POL, INVTxxx 4n s tDHLD Data Hold DX[5:0], POL, INVTxxx 6 ns tTWP LOAD Pulse Width 50 ns tLDENSU LOAD to First ENIO Setup (Note 11) 200 ns tENDCSU ENIOx Input to CLK Setup 4 ns FPD03784 www.national.com3

Digital AC Characteristics (2.5V Logic)(Continued) Symbol Parameter Conditions Min Typ Max Units tWEN ENIOx Input Pulse Width 12 ns tENPR ENIOx Output Prop Delay Load = 20pF 19 ns tLDLY Delay to LOAD Pulse 3 CLKs Note 10:Rise/Fall = 2.0ns max (10% to 90%) Note 11:Does not need to be synchronous to clock. Analog AC Characteristics Symbol Parameter Conditions Min Typ Max Units tsettle 90% Output Settling Time to 90% of Final Value R LOAD =5 kΩ ,C LOAD =4 0p F (Note 12) 2.4 µs tsettle 99% Output Settling Time to 99% of Final Value R LOAD =5 kΩ ,C LOAD =4 0p F (Note 12) 2.8 µs FPD03784 www.national.com 4

Note 13:LOAD pulse is asynchronous to CLK. It must meet minimum pulse-width, tLDENSU and tLDLY . Note 14:A minimum of 3 CLK cycles are required from the falling edge of CLK (on last data input to last chip) to the falling edge of the LOAD pulse. After these 3 CLK cycles, CLK may be disabled. DS200152-11 FPD03784 www.national.com5

The FPD03784 is a low power, low EMI, 384 output column driver with 64 gray level capability (6-bit). It provides direct drive for TFT-LCD displays, eliminating the need for V com modulation. Direct drive significantly reduces system power consumption and also reduces component count while pro- viding superior image quality and cross-talk margin. The FPD03784 utilizes National’s Charge Conservation Technol- ogy that recovers energy stored in the capacitance of the column lines to reduce power consumption further. The FPD03784 is designed for use in systems using dot inversion as the method of polarity inversion. Column inver- sion and N-line inversion are also supported. Other modes of polarity inversion including line inversion and frame inversion are not supported. Digital video data inputs to the FPD03784 are received on six, six bit wide busses (dual bank, RGB busses) using TTL signaling. The digital video commands one of 64 gray level voltages on each output. Output voltages are driven with individual high drive, low offset, programmable-slew-rate, operational amplifiers. Data loading and line buffering is accomplished by means of an internal, bi-directional shift register. GAMMA CORRECTION The FPD03784 is designed to offer compatibility with a wide range of panel gamma characteristics. The output voltage levels corresponding to each of the 64 gray level commands can be externally adjusted to match the desired gamma characteristics of the display by means of two internal resistor-string DACs (RDACs). One RDAC provides the high-polarity output voltages (voltages higher than V com ) and the other provides the low-polarity output voltages (voltages lower than V com ). The default RDAC resistance values have been carefully designed to provide a smooth 2.2 gamma characteristic in a twisted nematic (TN) display. This is especially useful for monitor applications. Consequently, most application de- signs will only need to provide references for each of the two ends of the two RDACs (four gamma references). Additional, intermediate taps to the RDAC are also provided for optional customization of the display gamma for contrast control as an example. CHARGE CONSERVATION TECHNOLOGY National Semiconductor’s proprietary charge conservation technology significantly reduces power consumption. Charge conservation works by briefly switching all of the columns at the start of each line to a common node. This has DS200152-6 FPD03784 www.national.com 6

Functional Description(Continued) the effect of redistributing the charge stored in the capaci- tance of the panel columns. Since half the columns are at voltages more positive than V com and half are more nega- tive, this redistribution of charge or “charge-sharing” has the effect of pulling all of the columns to a neutral voltage near the middle of the driver’s dynamic range. Thus, the voltages on all the columns are driven approximately halfway toward their next value with no power expended. This dramatically reduces panel power dissipation (up to a theoretical limit of 50%) compared to conventional drivers which must drive each column through the entire voltage swing every time polarity is reversed. PIN DESCRIPTIONS The pin order configuration for the FPD03784 is shown in fig. 3. Optional pins do not need to be carried off a custom TCP or COP package but may require a connection to a neigh- boring pad on the die by a tie on the tape. The following paragraphs describe the function of the FPD03784 pins. CSTIME — CHARGE SHARE TIME (INPUT) The input controls how long the outputs are in charge share mode following each LOAD signal. The CSTIME input from all of the column drivers should be tied together and con- nected to VSS1 through a parallel combination of RC. The charge time is determined by the equation: T charge share= 0.69 RC A typical capacitance of 100pF should be chosen to swamp parasitic board and I/O pin effects. SeeFigure 1. CLK — DATA CLOCK (INPUT) Clock input for data on Dx[0:5]. DX[5:0]— DATA BUS (INPUT) DA[5:0] — Data Input Pins for OUTPUTS 1, 7...379 DB[5:0] — Data Input Pins for OUTPUTS 2, 8...380 DC[5:0] — Data Input Pins for OUTPUTS 3, 9...381 DD[5:0] — Data Input Pins for OUTPUTS 4, 10...382 DE[5:0] — Data Input Pins for OUTPUTS 5, 11...383 DF[5:0] — Data Input Pins for OUTPUTS 6, 12...384 ENIO1/ENIO2 — DATA LOADING ENABLE 1 AND 2 (I/O) If UP = H, then the ENIO1 pin is configured as an input and the ENIO2 pin is configured as an output. If UP = L, then the ENIO2 pin is configured as an input and the ENIO1 pin is configured as an output. INVTABC — DIGITAL DATA INVERT (INPUT) When INVERT = L, input data from DA[0:5], DB[0:5] and DC[0:5] is inverted. The INVTABC pin can be tied to INVTDEF on the TCP to form a single INVERT pin, or operated independently from each other. INVTDEF — DIGITAL DATA INVERT (INPUT) When INVERT = H, input data from DD[0:5], DE[0:5] and DF[0:5] is inverted. The INVTABC pin can be tied to INVTDEF on the TCP to form a single INVERT pin, or operated independently from each other. I REF — REF ERENCE CURRENT FOR OUTPUT DRIVE (INPUT) The IREF input allows the designer to set the maximum output drive current (IMAX ) of the FPD03784 suitable for the column line, RC network load. Current flow out of the IREF pin is used to set the rise and fall slew rate of the output waveform. This current is supplied through an external re- sistor (R IREF) tied between the IREF pin (held by the FPD03784 at VDD1 ) and VSS1 . Each driver IC must have a separate RIREF resistor (seeFigure 1). ISIN — CURRENT SOURCE INPUT (INPUT) The ISIN current controls the bandwidth and settling perfor- mance of the FPD03784 output-stage amplifiers. Increasing I SIN increases the amplifier bandwidth and reduces settling time but also increases power consumption. Normally, ISIN is set to 40µA, which provides a good balance between power consumption and amplifier bandwidth. The flexibility to adjust I SIN accommodates very fast rise times (ISIN > 40µA) or applications where low power is of extreme interest (ISIN < 40µA). The ISIN current is supplied through an external resistor (RISIN) connected between the ISIN pin and VDD2 .R ISINcan be computed as follows: (ISIN normally = 40µA) One resistor (RISIN) is needed for the entire display. This resistor is connected to the ISIN input of the first driver, and the current going into this pin is copied to the ISOUT output pin for cascading to the next driver. SeeFigure 1. Note that IHBIAS varies linearly with ISIN. ISOUT — CURRENT SOURCE O UTPUT (OUTPUT) This output pin supplies the ISIN current to the ISIN input pin of the next driver in the row (seeFigure 1). The ISOUT pin of the last driver should be left floating. Optionally, this pin can be left floating on each driver if the designer wishes to provide a separate I SIN source to each driver. While this adds resistor component count, it reduces input lead count. LOAD — DATA LOAD (INPUT) The falling edge of LOAD copies the digital video buffered by the shift register into a second latch beginning the D to A conversion. Immediately following the fall of LOAD, the out- puts are forced into charge share mode for the time set by the CSTIME input. The outputs then drive the D to A con- verted voltages following the CSTIME. POL — POL ARITY (INPUT) When POL = L, odd numbered outputs (1, 3, 5, ...383) are controlled by VGMA7 through VGMA12 and even numbered outputs are controlled by VGMA1 through VGMA6. When POL = H, odd numbered outputs are controlled by VGMA1 through VGMA6 and even numbered outputs are controlled by VGMA7 through VGMA12. SINGLE — SINGLE /DUAL-EDGE CLOCK ENABLE (IN- PUT) This pin controls single/dual-edge clocking. When SINGLE is high, single-edge clocking is enabled, and input data is latched only on the falling edge of CLK. When SINGLE is low, dual-edge clocking is enabled, and input data is latched on both the rising and falling edges of CLK. Optional — The SINGLE die pad is bounded on each side by a logic High and a logic Low pad. This allows the state of SINGLE to be chosen on the TCP to eliminate an input pin. UP — DATA SHIFT DIRECTION — UP OR DOWN (INPUT) The UP pin controls the data shift direction. If UP is high then data is shifted “up” from output 1 to output 384, ENIO1 is configured as an input, and ENIO2 is an output. If UP is low then data is shifted “down” from output 384 to output 1, ENIO2 is an input, and ENIO1 is an output. FPD03784 www.national.com7

to be chosen on the TCP to eliminate an input pin. voltage during charge share time. Positive supply voltage for the analog functions of the driver. to control the inverse gamma transfer function of the driver. Digital ground reference voltage. Analog ground reference voltage. FIGURE 1. External Components and Connections for the IREF ,ISIN and ISOUT Pins

FIGURE 2. FPD03784 R-DAC Transfer Characteristic

FIGURE 3. FPD03784 R-DAC Transfer Characteristic (continued)

FPD03784 I/O Configuration INPUTS OUTPUTS POL FPD03784 384 VCS 383 optional SINGLE 382 optional UP 381 DF[5] 380 DF[4] 379 DF[3] . DF[2] . DF[1] . DF[0] . VSS1/2 . VDD2 . DE[0] . DE[1] . DE[2] . DE[3] . DE[4] . DE[5] . DD[5] . DD[4] . DD[3] . DD[2] . DD[1] . DD[0] . DC[0] . DC[1] . DC[2] . DC[3] . DC[4] . DC[5] . CLK . VDD1 . (Continued top of next column) (Continued) INPUTS OUTPUTS VGMA12 FPD03784 VGMA1 . VGMA6 . VGMA7 . optional VGMA2 . optional VGMA3 . optional VGMA4 . optional VGMA5 . optional VGMA8 . optional VGMA9 . optional VGMA10 . optional VGMA11 . DB[5] . DB[4] . DB[3] . DB[2] . DB[1] . DB[0] . DA[0] . DA[1] . DA[2] . DA[3] . DA[4] . DA[5] . VDD2 . VSS1/2 . VHBIAS . ENIO2 . ENIO1 . LOAD . CSTIME 6 IREF 5 ISIN 4 optional ISOUT 3 INVTABC 2 optional INVTDEF 1 Note:This figure represents an FPD03784 die oriented pad side up. Packaging The FPD03784 is available as singulated die. FPD03784 www.national.com11

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com FPD03784 Low Power, Low EMI, TFT-LCD Column Driver with Dual, TTL Bus Inputs, 64 Grayshades, and 384 Outputs for XGA/SXGA Applications National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.