FPAL10SH60

FPAL10SH60 FAIRCHILD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 17

Technical content

Features

• UL Certified No. E209204
• 600V-10A 3-phase IGBT inverter bridge including control ICs for gate driving and protection
• Single-grounded power supply due to built-in HVIC
• Typical switching frequency of 15kHz
• Built-in thermistor for over-temperature monitoring
• Inverter power rating of 0.4kW / 100~253 Vac
• Isolation rating of 2500Vrms/min.
• Very low leakage current due to using ceramic substrate
• Adjustable current protection level by varying series resistor value with sense-IGBTs

Applications

• AC 100V ~ 253V three-phase inverter drive for small power (0.4kW) ac motor drives
• Home appliances applications requiring high switching frequency operation like washing machines drive system
• Application ratings: - Power : 0.4 kW / 100~253 Vac - Switching frequency : Typical 15kHz (PWM Control) - 100% load current : 3.0A (Irms) - 150% load current : 4.5A (Irms) for 1 minute External View and Marking Information Fig. 1. 55 mm 57 mm Top View Bottom View Marking Device Name Version, Lot Code

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Integrated Power Functions

• 600V-10A IGBT inverter for three-phase DC/AC power conversion (Please refer to Fig. 3) Integrated Drive, Protection and System Control Functions
• For inverter high-side IGBTs: Gate drive circuit, High voltage isolated high-speed level shifting Control circuit under-voltage (UV) protection Note) Available bootstrap circuit example is given in Figs. 11, 16 and 17.
• For inverter low-side IGBTs: Gate drive circuit, Short circuit protection (SC) Control supply circuit under-voltage (UV) protection
• Temperature Monitoring: System over-temperature monitoring using built-in thermistor Note) Available temperature monitoring circuit is given in Fig. 17.
• Fault signaling: Corresponding to a SC fault (Low-side IGBTs) or a UV fault (Low-side supply)
• Input interface: 5V CMOS/LSTTL compatible, Schmitt trigger input Pin Configuration Fig. 2. Pin Descriptions Pin Number Pin Name Pin Description 1V CC(L) Low-side Common Bias Voltage for IC and IGBTs Driving 2C O M (L) Low-side Common Supply Ground 3I N (UL) Signal Input Terminal for Low-side U Phase 4I N (VL) Signal Input Terminal for Low-side V Phase 5I N (WL) Signal Input Terminal for Low-side W Phase 6V FO Fault Output Terminal 7C FOD Capacitor for Fault Output Duration Time Selection 8C SC Capacitor (Low-pass Filter) for Short-current Detection Input 9R SC Resistor for Short-circuit Current Detection

10 NC No Connection

11 V TH Thermistor Bias Voltage

12 R TH Series Resistor for the Use of Thermistor (Temperature Detection)

13 W Output Terminal for W Phase

14 V Output Terminal for V Phase

15 U Output Terminal for U Phase

VCC(L) COM(L) IN(UL) IN(VL) IN(WL) VFO CFOD CSC RSC NC VTH RTH WVUNP VS(U) VB(U) VCC(UH) IN(UH) VS(V) VB(V) VCC(VH) IN(VH) COM(H) VS(W) VB(W) VCC(WH) IN(WH) Top View

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Internal Equivalent Circuit and Input/Output Pins Note 1. Inverter low-side ( (1) - (12) pins) is composed of three sense-IGBTs including freewheeling diodes for each IGBT and one con trol IC which has gate driving, current sensing and protection functions. 2. Inverter power side ( (13) - (17) pins) is composed of two inverter dc-link input terminals and three inverter output termina ls. 3. Inverter high-side ( (18) - (30) pins) is composed of three normal-IGBTs including freewheeling diodes and three drive ICs fo r each IGBT. Fig. 3.

16 N Negative DC–Link Input

17 P Positive DC–Link Input

(WH) Signal Input Terminal for High-side W Phase

19 V CC(WH) High-side Bias Voltage for W Phase IC

20 V B(W) High-side Bias Voltage for W Phase IGBT Driving

21 V S(W) High-side Bias Voltage Ground for W Phase IGBT Driving

22 COM (H) High-side Common Supply Ground

23 IN (VH) Signal Input Terminal for High-side V Phase

24 V CC(VH) High-side Bias Voltage for V Phase IC

25 V B(V) High-side Bias Voltage for V Phase IGBT Driving

26 V S(V) High-side Bias Voltage Ground for V Phase IGBT Driving

27 IN (UH) Signal Input Terminal for High-side U Phase

28 V CC(UH) High-side Bias Voltage for U Phase IC

29 V B(U) High-side Bias Voltage for U Phase IGBT Driving

30 V S(U) High-side Bias Voltage Ground for U Phase IGBT Driving

Pin Descriptions (Continued) Pin Number Pin Name Pin Description WVUN P (1) VCC(L) (2) COM(L) (3) IN(UL) (4) IN(VL) (5) IN(WL) (6) VFO (7) CFOD (8) CSC (12) RTH (11) VTH (13) THERMISTOR (29) VB(U) (22) COM(H) (27) IN(UH) (30) VS(U) (28) VCC(UH) (25) VB(V) (23) IN(VH) (24) VCC(VH) (26) VS(V) (20) VB(W) (18) IN(WH) (19) VCC(WH) (21) VS(W) (10) NC (9) RSC VCC Wout Uout Vout C(SC) C(FOD) V(FO) IN(WL) IN(VL) IN(UL) COM(L) Vcc IN COM VB HO VS Vcc IN COM VB HO VS Vcc IN COM VB HO VS

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Absolute Maximum Ratings Inverter Part (TC = 25°C, Unless Otherwise Specified) Note 1. It would be recommended that the average junction temperature should be limited to T J ≤ 125°C (@TC ≤ 100°C) in order to guarantee safe operation. Control Part (TC = 25°C, Unless Otherwise Specified) Total System Item Symbol Condition Rating Unit Supply Voltage V DC Applied to DC - Link 450 V Supply Voltage (Surge) V PN(Surge) Applied between P- N 500 V Collector-Emitter Voltage V CES 600 V Each IGBT Collector Current ± I C TC = 25°C (Note Fig. 4) 10 A Each IGBT Collector Current (Peak) ± I CP TC = 25°C (Note Fig. 4) 20 A Collector Dissipation P C TC = 25°C per One Chip 43 W Operating Junction Temperature T J (Note 1) -55 ~ 150 °C Item Symbol Condition Rating Unit Control Supply Voltage V CC Applied between VCC(H) - COM(H), VCC(L) - COM(L) 18 V High-side Control Bias Voltage V BS Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) - VS(W) 20 V Input Signal Voltage V IN Applied between IN(UH), IN(VH), IN(WH) - COM(H) IN(UL), IN(VL), IN(WL) - COM(L) -0.3 ~ 6.0 V Fault Output Supply Voltage V FO Applied between VFO - COM(L) -0.3~VCC+0.5 V Fault Output Current I FO Sink Current at VFO Pin 5 mA Current Sensing Input Voltage V SC Applied between CSC - COM(L) -0.3~VCC+0.5 V Item Symbol Condition Rating Unit Self Protection Supply Voltage Limit (Short Circuit Protection Capability) VPN(PROT) Applied to DC - Link, VCC = VBS = 13.5 ~ 16.5V TJ = 125°C, Non-repetitive, less than 6 µs 400 V Module Case Operation Temperature T C Note Fig. 4 -20 ~ 100 °C Storage Temperature T STG -55 ~ 150 °C Isolation Voltage V ISO 60Hz, Sinusoidal, AC 1 minute, Connection Pins to Heat-sink Plate

2500 V rms

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Fig. 4. TC Measurement Point VCC(L) COM IN(UL) IN(VL) IN(WL) VFO CFOD CSC RSC NC VTH RTH WVUNP VS(U) VB(U) VCC(UH) IN(UH) VS(V) VB(V) VCC(VH) IN(VH) COM(H) VS(W) VB(W) VCC(WH) IN(WH) Case Temperature (TC) Detecting Point Ceramic Substate

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Absolute Maximum Ratings Thermal Resistance Note 2. For the measurement point of case temperature (T c), please refer to Fig. 4.

Electrical Characteristics

Inverter Part (Tj = 25°C, Unless Otherwise Specified) Note 3. t ON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given gate driving condition internally. For the detailed information, please see Fig. 5. Item Symbol Condition Min. Typ. Max. Unit Junction to Case Thermal Resistance Rth(j-c)Q Each IGBT under Inverter Operating Condition (Note 2) - - 2.89 °C/W Rth(j-c)F Each FWDi under Inverter Operating Condition (Note 2) - - 3.73 °C/W Contact Thermal Resistance Rth(c-f) Ceramic Substrate (per 1 Module) Thermal Grease Applied - - 0.06 °C/W Item Symbol Condition Min. Typ. Max. Unit Collector - Emitter Saturation Voltage VCE(SAT) VCC = VBS = 15V VIN = 0V IC = 10A, Tj = 25°C - - 2.8 V IC = 10A, Tj = 125°C - - 2.9 V FWDi Forward Voltage V FM VIN = 5V I C = 10A, Tj = 25°C - - 2.3 V IC = 10A, Tj = 125°C - - 2.1 V Switching Times t ON VPN = 300V, VCC = VBS = 15V IC = 10A, Tj = 25°C VIN = 5V ↔ 0V, Inductive Load (High-Low Side) (Note 3) -0 . 3 7- µs tC(ON) -0 . 1 2- µs tOFF -0 . 5 3- µs tC(OFF) -0 . 2- µs trr -0 . 1- µs Collector - Emitter Leakage Current ICES VCE = VCES, Tj = 25°C - - 250 µA

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Fig. 5. Switching Time Definition Fig. 6. Experimental Results of Switching Waveforms Test Condition: Vdc=300V, Vcc=15V, L=500uH (Inductive Load), TC=25°°°°C trr ICVCE VIN t ON t C(ON) VIN(ON) 10% IC 90% IC 10% VCE 100% IC (a) Turn-on trr ICVCE VIN t ON t C(ON) VIN(ON) 10% IC 90% IC 10% VCE 100% IC (a) Turn-on (b) Turn-off IC VCE VIN tOFF tC(OFF) 10% VCE 10% ICVIN(OFF) (b) Turn-off IC VCE VIN tOFF tC(OFF) 10% VCE 10% ICVIN(OFF) (a) Turn-on VCE : 100V/div. IC : 5A/div. time : 100ns/div. (b) Turn-off VCE : 100V/div. IC : 5A/div. time : 100ns/div. (a) Turn-on VCE : 100V/div. IC : 5A/div. time : 100ns/div. (b) Turn-off VCE : 100V/div. IC : 5A/div. time : 100ns/div.

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Control Part (Tj = 25°C, Unless Otherwise Specified) Note 4. Short-circuit current protection is functioning only at the low-sides. It would be recommended that the value of the external sensing resistor (R SC) should be selected around 56 Ω in order to make the SC trip-level of about 15A. Please refer to Fig. 8 which shows the current sensing characteristics according to sensing resistor RSC. 5. The fault-out pulse width t FOD depends on the capacitance value of CFOD according to the following approximate equation : CFOD = 18.3 x 10-6 x tFOD[F] Item Symbol Condition Min. Typ. Max. Unit Control Supply Voltage V CC Applied between VCC(H),VCC(L) - COM 13.5 15 16.5 V High-side Bias Voltage V BS Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) - VS(W) 13.5 15 16.5 V Quiescent VCC Supply Current IQCCL VCC = 15V IN(UL, VL, WL) = 5V VCC(L) - COM(L) -- 2 6 m A IQCCH VCC = 15V IN(UH, VH, WH) = 5V VCC(U), VCC(V), VCC(W) - COM(H) - - 130 uA Quiescent VBS Supply Current IQBS VBS = 15V IN(UH, VH, WH) = 5V VB(U) - VS(U), VB(V) -VS(V), VB(W) - VS(W) - - 420 uA Fault Output Voltage V FOH VSC = 0V, VFO Circuit: 4.7kΩ to 5V Pull-up 4.5 - - V VFOL VSC = 1V, VFO Circuit: 4.7kΩ to 5V Pull-up - - 1.1 V PWM Input Frequency f PWM TC ≤ 100°C, TJ ≤ 125°C - 15 - kHz Allowable Input Signal Blanking Time considering Leg Arm-short t dead -20°C ≤ TC ≤ 100°C 1 - - us Short Circuit Trip Level V SC(ref) TJ = 25°, VCC = 15V (Note 4) 0.45 0.51 0.56 V Sensing Voltage of IGBT Current VSEN -20°C ≤ TC ≤ 100°C, @ RSC = 82 Ω and IC = 10A (Note Fig. 8) 0.37 0.45 0.56 V Supply Circuit Under- Voltage Protection UVCCD TJ ≤ 125°C Detection Level 11.5 12 12.5 V UVCCR Reset Level 12 12.5 13 V UVBSD Detection Level 7.3 9.0 10.8 V UVBSR Reset Level 8.6 10.3 12 V Fault-out Pulse Width t FOD VCC = 15V, C(sc) = 1V CFOD = 33nF (Note 5) 1.4 1.8 2.0 ms ON Threshold Voltage V IN(ON) High-Side Applied between IN (UH), IN(VH), IN(WH) - COM(H) -- 0 . 8 V OFF Threshold Voltage V IN(OFF) 3.0 - - V ON Threshold Voltage V IN(ON) Low-Side Applied between IN (UL), IN(VL), IN(WL) - COM(L) -- 0 . 8 V OFF Threshold Voltage V IN(OFF) 3.0 - - V Resistance of Thermistor R TH @ TC = 25°C (Note Figs. 4 and 7) - 50 - k Ω @ TC = 80°C (Note Figs. 4 and 7) - 6.3 - k Ω

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Fig. 7. R-T Curve of The Built-in Thermistor Fig. 8. Relationship between Sensing Resistor and SC Trip Current for Short-Circuit Protection SC = 82 ×××× Rating Current(10A) / RSC) 20 30 40 50 60 70 80 90 100 110 120 130 R-T Curve Resistance [kΩ ] Temperature [℃] 10 20 30 40 50 60 70 80 90 SC Trip Current ISC [A] Sensing Resistor RSC [Ω ]

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Mechanical Characteristics and Ratings Fig. 9. Flatness Measurement Position of The Ceramic Substrate Note 6. Do not make over torque or mounting screws. Much mounting torque may cause ceramic cracks and bolts and Al heat-fin destructi on. 7. Avoid one side tightening stress. Fig.10 shows the recommended torque order for mounting screws. Uneven mounting can cause th e SPM ceramic substrate to be damaged. Fig. 10. Mounting Screws Torque Order (1 →→→→ 2 →→→→ 3 →→→→ 4) Item Condition Limits UnitsMin. Typ. Max. Mounting Torque Mounting Screw: M3 (Note 6 and 7) Recommended 10Kg•cm 8 10 12 Kg•cm Recommended 0.98N•m 0.78 0.98 1.17 N•m Ceramic Flatness (Note Fig. 9) 0 - +100 um Weight -5 6 - g 1 2222 1 2222

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Recommended Operating Conditions ICs Internal Structure and Input/Output Conditions Note 1. One LVIC drives three Sense-IGBTs and can do short-circuit current protection also. Three sense emitters are commonly connect ed to RSC terminal to detect short-circuit current. Low-side part of the inverter consists of three sense-IGBTs 2. One HVIC drives one normal-IGBT. High-side part of the inverter consists of three normal-IGBTs 3. Each IC has under voltage detection and protection function. 4. The logic input is compatible with standard CMOS or LSTTL outputs. 5. R PCP coupling at each input/output is recommended in order to prevent the gating input/output signals oscillation and it should be as close as possible to each SPM gating input pin. 6. It would be recommended that the bootstrap diode, D BS, has soft and fast recovery characteristics. Fig. 11. Item Symbol Condition Value UnitMin. Typ. Max. Supply Voltage V PN Applied between P - N - 300 400 V Control Supply Voltage V CC Applied between VCC(H) - COM(H), VCC(L) - COM(L) 13.5 15 16.5 V High-side Bias Voltage V BS Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) - VS(W) 13.5 15 16.5 V Blanking Time for Preventing Arm-short tdead For Each Input Signal 1 - - us PWM Input Signal f PWM TC ≤ 100°C, TJ ≤ 125°C - 15 - kHz Input ON Threshold Voltage V IN(ON) Applied between UIN,VIN, WIN - COM 0 ~ 0.65 V Input OFF Threshold Voltage V IN(OFF) Applied between UIN,VIN, WIN - COM 4 ~ 5.5 V LEVEL SHIFT HVICHVICHVICHVIC UV DETECT PULSE FILTER R R S Q ININININ(UH,VH,WH)(UH,VH,WH)(UH,VH,WH)(UH,VH,WH) COMCOMCOMCOM VSVSVSVS(UH,VH,WH)(UH,VH,WH)(UH,VH,WH)(UH,VH,WH) VCCVCCVCCVCC(UH,VH,WH)(UH,VH,WH)(UH,VH,WH)(UH,VH,WH) 15V Line15V Line15V Line15V Line UV PROTECTION SC PROTECTION TIME DELAY SC LATCH_UP ININININ(UL,VL,WL)(UL,VL,WL)(UL,VL,WL)(UL,VL,WL) PULSE GENERATOR (HYSTERISIS) BUFFER OUTPUT (UL,VL,WL) SOFT_OFF CONTROL VCCVCCVCCVCC(L)(L)(L)(L) UV DETECT TIME DELAY BANDGAP REFERENCE FAULT OUTPUT DURATION VVVVFOFOFOFO UV LATCH_UP CCCCFODFODFODFOD SC DETECTION LVICLVICLVICLVIC PPPPVBVBVBVB(UH,VH,WH)(UH,VH,WH)(UH,VH,WH)(UH,VH,WH) 5V Line5V Line5V Line5V Line 5V Line5V Line5V Line5V Line RP CPL CFOD RP CPH NNNN CBSCDBSRBS RSCCSC RF PULSE GENERATOR RPF CPF CBP15 CBS U,V,WU,V,WU,V,WU,V,W

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Time Charts of SPMs Protective Function P1 : Normal operation - IGBT ON and conducting current P2 : Under voltage detection P3 : IGBT gate interrupt P4 : Fault signal generation P5 : Under voltage reset P6 : Normal operation - IGBT ON and conducting current Fig. 12. Under-Voltage Protection (Low-side) P1 : Normal operation - IGBT ON and conducting current P2 : Under voltage detection P3 : IGBT gate interrupt P4 : No fault signal P5 : Under voltage reset P6 : Normal operation - IGBT ON and conducting current Fig. 13. Under-Voltage Protection (High-side) Internal IGBT Gate-Emitter Voltage Input Signal Output Current Fault Output Signal Control Supply Voltage UV detect UV reset Internal IGBT Gate-Emitter Voltage Input Signal Output Current Fault Output Signal Control Supply Voltage VBS UV detect UV reset

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 P1 : Normal operation - IGBT ON and conducting currents P2 : Short-circuit current detection P3 : IGBT gate interrupt / Fault signal generation P4 : IGBT is slowly turned off P5 : IGBT OFF signal P6 : IGBT ON signal - but IGBT cannot be turned on during the fault-output activation P7 : IGBT OFF state P8 : Fault-output reset and normal operation start Fig. 14. Short-circuit Current Protection (Low-side Operation only) Note It would be recommended that by-pass capacitors for the gating input signals, IN(XX) should be placed on the SPM pins and on the both sides of CPU and SPM for the fault output signal, VFO, as close as possible. Fig. 15. Recommended CPU I/O Interface Circuit Internal IGBT Gate-Emitter Voltage Input Signal Output Current Sensing Voltage Fault Output Signal SC Reference Voltage (0.5V) RC Filter Delay SC Detection CPU COM 5V-Line 1.2nF0.47nF1nF Ω4.7k Ω4.7kΩ4.7k ,,IN (UL) IN (VL) IN(WL) ,,IN(UH) IN(VH) IN(WH) VFO FPAL10SH60 Ω100 Ω100 Ω100 1nF

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Fig. 16. Recommended Bootstrap Operation Circuit and Parameters One-leg Diagram of FPAL10SH60 P N Inverter Output Vcc IN COM VB HO VS Vcc IN COM OUT 15V-Line 20Ω 1000uF 0.1uF 220uF 0.1uF One-leg Diagram of FPAL10SH60 P N Inverter Output Vcc IN COM VB HO VS Vcc IN COM OUT 15V-Line 20Ω 1000uF 0.1uF 220uF 0.1uF

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Note 1. R PCPL/RPCPH coupling at each SPM input is recommended in order to prevent input signals’ oscillation and it should be as close as possible to each SPM input pin. 2. By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto- coupler or transformer isolation is possible. 3. V FO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approxim ately 4.7kΩ resistance. Please refer to Fig. 15. 4. C SP15 of around 7 times larger than bootstrap capacitor CBS is recommended. 5. V FO output pulse width should be determined by connecting an external capacitor(C FOD) between CFOD(pin7) and COM(L)(pin2). (Example : if C FOD = 5.6 nF, then tFO = 300 µs (typ.)) Please refer to the note 5 for calculation method. 6. Each input signal line should be pulled up to the 5V power supply with approximately 4.7k Ω resistance (other RC coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedance of the system’s printed circuit board). Approximately a 0 .22~2nF by-pass capacitor should be used across each power supply connection terminals. 7. To prevent errors of the protection function, the wiring around R SC, RF and CSC should be as short as possible. 8. In the short-circuit protection circuit, please select the R FCSC time constant in the range 3~4 µs. RF should be at least 30 times larger than RSC. (Recommended Example: RSC = 56 Ω , RF = 3.9kΩ and CSC = 1nF) 9. Each capacitor should be mounted as close to the pins of the SPM as possible. 10.To prevent surge destruction, the wiring between the smoothing capacitor and the P&N pins should be as short as possible. T he use of a high frequency non- inductive capacitor of around 0.1~0.22 uF between the P&N pins is recommended. 11.Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the CPU and the relays. It is recommended that the distance be 5cm at least Fig. 17. Application Circuit M 15V line 5V line 5V line 5V line CPU Gating UH Gating VH Gating WH Gating UL Gating VL Gating WL Fault Vdc RBSDBS CBS CPH RP CPL RP CFOD CSC RF RSC RTH CSP15Temp. Monitoring CBPF RS CSPC15 CSP05 CSPC05 CBSC CBSCBSC CBSCBSC RBSDBS RBSDBS RPRP CPHCPH RS RS RSRSRSRS CDCS RPRPRP CPLCPLCPF (1) VCC(L) (2) COM(L) (3) IN(UL) (4) IN(VL) (5) IN(WL) (6) VFO (7) CFOD (8) CSC (12) RTH (11) VTH (13) THERMISTOR VB(U) (29) COM(H) (22) IN(UH) (27) VS(U) (30) VCC(UH) (28) VB(V) (25) IN(VH) (23) VCC(VH) (24) VS(V) (26) VB(W) (20) IN(WH) (18) VCC(WH) (19) VS(W) (21)(10) NC (9) RSC VCC Wout Uout Vout C(SC) C(FOD) V(FO) IN(WL) IN(VL) IN(UL) COM(L) Vcc IN COM VB HO VS Vcc IN COM VB HO VS Vcc IN COM VB HO VS

©2002 Fairchild Semiconductor Corporation FPAL10SH60 Rev. C, February 2002 Detailed Package Outline Drawings

ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E 2CMOS™ EnSigna™ FACT™ FACT Quiet Series™ FAST® FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench QFET™ QS™ QT Optoelectronics™ Quiet Series™ SLIENT SWITCHER SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TruTranslation™ TinyLogic™ UHC™ UltraFET VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: ©2002 Fairchild Semiconductor Corporation Rev. H4 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. STAR*POWER is used under license