FP6733 FITIPOWER | Alldatasheet
Document overview
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Technical content
Features
0.9V (Typ.) Low Start-up Input Voltage at 1mA Load High Switching Frequency at 550kHz Provide Flexibility for Using Internal and External Power Switches Automatic PFM Mode at Light Load Low Ripple and High Efficiency Excellent Line/Load Regulation Chip Enable Control Function Current Limit Protection Thermal Overload Protection Space Saving Packages: SOT-23-6 and TSOT-23-6
Applications
PDA MP3 DSC RF Tag Wireless Equipment Portable Equipment FP6733□□□ G: Green TR: Tape/Reel Package Type S6: SOT-23-6 S9: TSOT-23-6
fitipower integrated technology lnc. Figure 2. Typical Application Circuit of FP6733 EXT External switch transistor driver output. LX Internal switch MOS output. VDD IC internal power supply. FB Feedback input pin. Internal reference voltage for error amplifier is 1.25V.
fitipower integrated technology lnc. Figure 3. Block Diagram of FP6733 Note1：Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device.
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Electrical Characteristics
(TA=25C, unless otherwise specified.) Parameter Symbol Test Conditions Min Typ Max Units Operation Voltage VDD Normal Operation 2.9 5.5 V Start-Up Voltage VSTART VIN : 0→1V, IOUT=1mA 0.9 1.05 V No-Load Input Current INO_LOAD VIN=1.5V, VOUT=3.3V 75 µA Continuous Switching Current ISWITCH VDD=3.3V, VFB=0V 0.2 0.3 0.4 mA No Switch Current IQ VIN=6V 17 25 µA Shutdown Current ISD VDD=4.5V, CE pin=0V 0.1 1.0 µA Feedback Reference Voltage VFB Close loop, VDD=3.3V 1.225 1.25 1.275 V EXT ON Resistance to VDD VDD=3.3V 5 8.5 Ω EXT ON Resistance to GND VDD=3.3V 5 8.5 Ω LX ON Resistance (Note 2) RDS-ON VDD=3.3V 0.3 Ω Max. Duty Ratio DUTY VDD=3.3V 85 95 % Oscillator Frequency fOSC VDD=3.3V 450 550 650 kHz LX Leakage Current ILXL VLX=6V 0.1 1.0 µA Line Regulation ΔVLINE VIN=1.5 ~2.5V, IL=50mA 3 10 mV/V Load Regulation ΔVLOAD VIN=2.5V, IL=1~100mA 0.15 0.3 mV/mA Switch Current Limit (Note 2) ILIMIT VDD=3.3V 0.75 1 A CE “High” Voltage VCEH VDD=3.3V, switch ON 1.2 V CE “Low” Voltage VCEL VDD=3.3V, switch OFF 0.4 V CE “High” Current ICEH VDD =3.3V, VCE=VDD 0.1 µA CE “Low” Current ICEL VDD =3.3V, VCE=0V -0.1 µA Efficiency (Note 2) η 85 % Thermal Shutdown Threshold (Note 2) TSD 145 ºC TSD Hysteresis 30 ºC Note 2：Guarantee by design.
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Application Information
The FP6733 is designed in a current mode PFM/PWM scheme which features an automatic switch PFM/PWM mode to maintain the highest efficiency and extend battery life. The quiescent current is less than 25μA at no switching status. The control loop is internally compensated reducing the amount of external components. Chip Enable The FP6733 features a chip enable input pin that allows on/off control of the regulator. When CE=Low, shutdown of the chip occurs and at that time almost no quiescent current (<1μA) flows. The chip enable input is TTL/CMOS compatible. Connect CE to battery for normal operation. Current Limit Protection The FP6733 provides cycle -by-cycle over -current protection. Current limit is accomplished by sensing voltage drop across the dr ain to source of power switch. If the current sense amplifier output voltage is larger than current -limited threshold level (Typ. 1.0A), it will immediately turn off power MOS. Thermal Protection Thermal protection limits total power dissipation in the FP 6733. When the junction temperature exceeds Tj=145 C, the thermal sensor signals the shutdown logic and turns off most of the internal circuitry. The thermal sensor will turn internal circuitry on again after the IC’s junction temperature drops 30C. Adjustable Output Voltage The output voltage of FP6733 ranges from 1.25V to 5.0V which is set by the external feedback resistor. It can be calculated as: V 1. 1 R1 R Inductor Selection A 3.3 μH to 10 μH inductor is recommended for general use. The value of inductor depends on the operating frequency. Higher frequency allows smaller inductor and capacitor but increasing internal switching loss. Two inductor parameters should be considered, current rating and DCR. The DCR of inductor affects the efficiency of the converter. The inductor with lowest DCR is chosen for highest efficiency. The inductor value can be calculated as: L VI V VI f IL V IL: inductor ripple current, usually set 20% x I L, which defined as: IL V VI L f VI V The inductor should be rated for the maximum output current (I O(MAX)) plus the inductor ripple current ( IL) to avoid saturation. The maximum inductor current (IL(MAX)) is given by: IL MA I max IL Capacitor Selection The FP6733 is permissible to use ceramic capacitor for hand held instrument applications. The value of capacitor depends on acceptable voltage ripple. The input capacitor can reduce peak current and noise at power source. It should be 10μF at least and be increased for better input voltage filtering. Select the input capacitor to meet the input ripple current and voltage rating. When selecting an output capacitor, consider the output ripple voltage and the ripple current. The ESR of capacitor is a major factor to the output ripple. For best performance, a low ESR output capacitor is required. The ripple voltage is given by: V IL ESR 1 f C The common aluminum-electrolytic capacitors have high ESR and should be av oided. Ceramic capacitors have the low est ESR in general. It’s recommended to use 10μF ceramic output capacitors for the FP6733. Diode Selection For diode selection, both forward voltage and diode capacitance need to be considered. The output diode shou ld be rated to the output voltage and peak switch current. Schottky diodes, with low forward voltage drop and fast reverse recovery, are the ideal choices for FP6733 applications. Make sure the diode’s peak current rating is at least IPK and its breakdown voltage exceeds VOUT.
9 FP6733-1.6-JUN-2013 FP6733 fitipower integrated technology lnc. Application Information (Continued) Layout Consideration Careful PCB layout is extremely important to avoid causing parasitical capacitance and line inductance. The following layout guidelines are recommended to achieve optimum performance. Place the Boost converter diode and inductor close to the LX pin and no via. Place the ceramic bypass capacitors near the VDD and GND pin. Place COUT next to Schottky diode as possible. Use as wide and short traces as possible to the LX node. Keep the noise-sensitive feedback away from the switching node.
10 FP6733-1.6-JUN-2013 FP6733 fitipower integrated technology lnc. Outline Information SYMBOLS UNIT DIMENSION IN MILLIMETER MIN MAX A 0.90 1.45 A1 0.00 0.15 A2 0.90 1.30 B 0.30 0.50 D 2.80 3.00 E 2.60 3.00 E1 1.50 1.70 e 0.90 1.00 e1 1.80 2.00 L 0.30 0.60 Note：Followed From JEDEC MO-178-C. Carrier Dimensions
11 FP6733-1.6-JUN-2013 FP6733 fitipower integrated technology lnc. Outline Information (Continued) SYMBOLS UNIT DIMENSION IN MILLIMETER MIN MAX A 0.70 0.90 A1 0.00 0.10 A2 0.70 1.00 B 0.30 0.50 D 2.80 3.00 E 2.60 3.00 E1 1.50 1.70 e 0.90 1.00 e1 1.80 2.00 L 0.30 0.60 Carrier Dimensions Life Support Policy Fitipower’s products are not authorized for use as critical components i n life support devices or other medical systems.