FP6382

FP6382 FITIPOWER | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 13

Technical content

Features

 Low RDS(ON) for Internal Switch (Top/Bottom): 200/150mΩ  2.5V~5.5V Input Voltage Range  1A Output Current  1MHz/1.5MHz Switching Frequency Minimizes the External Components  Internal Soft-Start Limits the Inrush Current  Internal Compensation Function  100% Dropout Operation  Short Circuit Protection with Auto Recovery  RoHS Compliant and Halogen Free  TDFN-12 (3mm×3mm) Package

Applications

 Set Top Box  LCD TV  Notebook  Wireless LAN  Handheld Instrument  MP3 Portable Audio Player  Battery Operated Device Pin Assignments TOP VIEW VIN2 LX2 GND NC1 EN2 NC2 GND LX1 76EN1 VIN1 GND FB1 FB2 Figure 1. Pin Assignment of FP6382

Ordering Information

FP6382□□□ C: Green TR: Tape/Reel Package Type WD: TDFN-12 (3mm×3mm)

fitipower integrated technology lnc. Figure 2. Schematic Diagram VIN=5V, the recommended BOM list is as below. Table 1. Recommended Component Values

fitipower integrated technology lnc. GND 3, 9 Ground pin. This pin is connected to the exposed pad with copper. LX1 8 Power switching output. Connect an external inductor to this switching node. LX2 2 Power switching output. Connect an external inductor to this switching node. feedback voltage via FB1 and regulates it at 0.6V. feedback voltage via FB2 and regulates it at 0.6V. Figure 3. Block Diagram of FP6382

4 FP6382-0.3-DEC-2013 FP6382 /a85T fitipower integrated technology lnc. Absolute Maximum Ratings (Note 1)

• Package Thermal Resistance, (θJA)
• Package Thermal Resistance, (θJC) Note 1：Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device. Recommended Operating Conditions (Note 2) Note 2：The device is not guaranteed to function outside its operating conditions .

5 FP6382-0.3-DEC-2013 FP6382 /a85T fitipower integrated technology lnc.

Electrical Characteristics

(VIN=5V, VOUT =2.5V, TA=25°C, unless otherwise specified.) Parameter Symbol Conditions Min Typ Max Unit Shutdown Current ISHDN EN=0V 0.1 1 μA Quiescent Current Iq VFB=0.65V, IOUT=0A 80 μA Reference Voltage VREF 0.588 0.6 0.612 V FB Input Leakage Current IFB VFB=VIN 0.01 1 µA P-Channel MOSFET On-Resistance (Note 3) RDS(ON) 200 mΩ N-Channel MOSFET On-Resistance (Note 3) RDS(ON) 150 mΩ P-Channel Current Limit (Note 3) ILIM 1.5 A EN High-Level Input Voltage VIH 1.5 V EN Low-Level Input Voltage VIL 0.4 V Under Voltage Lockout Voltage UVLO 2.4 V UVLO Hysteresis VHYS 0.2 V Oscillation Frequency FOSC IOUT1=200mA (LX1) 1.2 1.5 1.8 MHz IOUT2=200mA (LX2) 0.8 1 1.2 Minimum On Time 50 ns Maximum Duty Cycle 100 % VOUT Discharge Resistance 100 Ω Thermal Shutdown Temperature (Note 3) TSD 150 °C Internal Soft Start Time TSS 1 ms Note 3：Guarantee by design.

9 FP6382-0.3-DEC-2013 FP6382 /a85T fitipower integrated technology lnc. Function Description The FP6382 is a dual channel, high efficiency, high frequency synchronous DC-DC step-down regulator. The 100% duty cycle feature provides low dropout operation, extending battery life in portable systems. At light load condition, the FP638 2 can operate at PSM mode to support high efficiency and reduce power lose. It has integrated high -side (200mΩ, typ.) and low -side ( 150mΩ, typ .) power switches , and provides 1A continuous load current. It regulates input voltage from 2.5V to 5.5V, and down to an output voltage as low as 0.6V. Control Loop Slope compensated current mode PWM control provides stable switching and cycle -by-cycle current limit for superior load, line response, protection of the internal main switch and synchronous rectifier. The FP6382 switches at a constant frequency ( 1MHz & 1.5MHz) and regulates the output voltage. During each cycle , the PWM comparator modulates the power transferred to the load by changing the inductor peak current based on the feedback error voltage. During normal operation, the main switch is turned on for a certain time to ramp the inductor current at each rising edge of the internal oscillator, and switched off when the peak inductor current is above the error voltage. When the main switch is off, the synchronous rectifier will be turned on immediately and stay on until next cycle starts. Enable The F P6382 EN pin provides digital control to turn on/off the regulator. When the voltage of EN exceeds the threshold voltage, the regulator will start the soft start function. If the EN pin voltage is below the shutdown threshold voltage, the regulator will turn into the shutdown mode and the shutdown current will be smaller than 1μA. For auto start-up operation, connect EN to VIN. Soft Start The FP6382 employs internal soft start function to reduce input in rush current during start up. The internal soft start time will be 1ms. Under Voltage Lockout When the FP6382 is power on, the internal circuits will be held inactive until V IN voltage exceeds the UVLO threshold voltage. And the regulator will be disabled when V IN is below the UVLO threshold voltage. The hysteretic of the UVLO comparator is 200mV (typ). Short Circuit Protection The FP638 2 provides short circuit protection function to prevent the device damaged from short condition. When the short condition occurs and the feedback voltage drops lower than 40% of the regulation level, this will activate the latch protection circuit. Then output will be forced shutdown to prevent the inductor current runaway and to reduce the power dissipation within the IC under true short circuit conditions. Once the short condition is removed, reset EN or VIN to restart IC. Over Current Protection The FP6382 over current protection function is implemented by using cycle -by-cycle current limit architecture. The inductor current is monitored by measuring the high -side MOSFET series sense resistor voltage. When the load current increases, the inductor current will also increase. When the peak inductor current reaches the current limit threshold, the output voltage will start to drop. When the over current condition is removed, the output voltage will return to the regulated value. Over Temperature Protection The FP6382 incorporates an over temperature protection circuit to protect itself from overheating. When the junction temperature exceeds the thermal shutdown threshold temperature, the regulator will be shutdown . And t he hysteretic of the over temperature protection is 30°C (typ).

10 FP6382-0.3-DEC-2013 FP6382 /a85T fitipower integrated technology lnc.

Application Information

The output voltage V OUT is set by using a resistive divider from the output to FB. The FB pin regulated voltage is 0.6V. Thus the output voltage is: T= . 1+R1 Table 2 lists recommended values of R1 and R2 for most used output voltage. Table 2 Recommended Resistance Values VOUT R1 R2 3.3V 453kΩ 100kΩ 2.5V 316kΩ 100kΩ 1.8V 200kΩ 100kΩ 1.5V 150kΩ 100kΩ 1.2V 100kΩ 100kΩ Place resistors R1 and R2 close to FB pin to prevent stray pickup. Input Capacitor Selection The use of the input capacitor is filtering the input voltage ripple and the MOSFETS switching spike voltage. Because the input current to the step-down converter is discontinuous, the input capacitor is required to supply the current to the converter to keep the DC input voltage. The capacitor voltage rating should be 1.25 to 1.5 times greater than the maximum input voltage. The input capacitor ripple current RMS value is calculated as: (RMS = T 1 = T Where D is the duty cycle of the power MOSFET . This function reaches the maximum value at D=0.5 and the equivalent RMS current is equal to I OUT/2. The following diagram is the graphical representation of above equation. A low ESR capacitor is required to keep the noise minimum. Ceramic capacitors are better, but tantalum or low ESR electrolytic capacitors may also suffice. Output Capacitor Selection The output capacitor is used to keep the DC output voltage and supply the load transient current. When operating in constant current mode, the output ripple is determined by four components: R PPL t = R PPL C t + R PPL SR t + R PPL ( SL t + S t The follow ing figures show the form of the ripple contributions. VRIPPLE(ESR)(t) VRIPPLE(ESL) (t) VRIPPLE(C) (t) VNOISE (t) VRIPPLE(t) 0.1 0.2 0.3 0.4 0.5 0.6 10 20 30 40 50 60 70 80 90 IIN(RMS) (A) D (%) (t) (t) (t) (t) 0.5A

11 FP6382-0.3-DEC-2013 FP6382 /a85T fitipower integrated technology lnc. Application Information (Continued) R PPL ( SR = T F SC L 1 T SR R PPL ( SL = SL L+ SL R PPL (C = T F SC2 L C T 1 T Where F OSC is the switching frequency, L is the inductance value, VIN is the input voltage, ESR is the equivalent series resistance value of the output capacitor, ESL is the equivalent series inductance value of the output capacitor and the C OUT is the output capacitor. Low ESR capacitors are preferred to use. Ceramic, tantalum or low ESR electrolytic capacitors can be used depending on the output ripple requirement s. When using the ceramic capacitors , the ESL component is usually negligible. It is important to use the proper method to eliminate high frequency noise when measuring the output ripple. The figure shows how to locate the probe across the capacitor when m easuring output ripple. Remove the scope probe plastic jacket in order to expose the ground at the tip of the probe. It gives a very short connection from the probe ground to the capacitor and eliminates noise. Inductor Selection The output inductor is used for storing energy and filtering output ripple current. But the trade -off condition often happens between maximum energy storage and the physical size of the inductor. The first consideration for selecting the output inductor is to make sure that the inductance is large enough to keep the converter in the continuous current mode. That will lower ripple current and result in lower output ripple voltage. The Δ L is inductor peak-to-peak ripple current: L= T F SC L 1 T The following diagram is an example to graphically represent Δ L equation. VOUT1=1.2V, FOSC1=1.5MHz A good compromise value between size and efficiency is to set the peak-to-peak inductor ripple current Δ L equal to 30% of the maximum load current. But setting the peak -to-peak inductor ripple current Δ L between 20%~50% of the maximum load current is also acceptable. Then the inductance can be calculated with the fol lowing equation: L= . T(MA T T F SC L To guarantee sufficient output current, peak inductor current must be lower than the FP6382 current limit. The peak inductor current is shown as below: P A = T(MA + L Time Load Current ∆IL IPEAK IOUT(MAX) 0.1 0.2 0.3 0.4 0.5 0.6 2.5 3 3.5 4 4.5 5 5.5 ΔIL (A) VIN (V) Ceramic Capacitor VOUT GND Probe Ground L=2.2μH L=1.5μH L=1.8μH

12 FP6382-0.3-DEC-2013 FP6382 /a85T fitipower integrated technology lnc. Application Information (Continued) Feedforward Capacitor Selection Internal compensation function allows users saving time in design and saving cost by reducing the number of external components. The use of a feedforward capacitor CF1 and CF2 in the feedback network is recommended to improve transient response or higher phase margin. FP6382 VOUT1 FB1 CF1 For optimizing the feedforward capacitor, knowing the cross frequency is the first thing . The cross frequency (or the converter bandwidth) can be determined by using a network analyzer. When getting the cross frequency with no feedforward capacitor identified, the value of feedforward capacitor CF1 and CF2 can be calculated with the following equation: CF1= 1

2 FCR SS

Where FCROSS is the cross frequency. To reduce transient ripple, the feedforward capacitor value can be increased to push the cross frequency to higher region. Although this can improve transient response, it also decrease s phase margin and causes more ringing. In the other hand, if more phase margin is desired, the feedforward capa citor value can be decreased to push the cross frequency to lower region. In general, the feedforward capacitor range is between 10pF to 330pF. PCB Layout Recommendation The device’s performance and stability are dramatically affected by PCB layout. It is recommended to follow these general guidelines shown as below: 1. Place the input capacitors and output capacitors as close to the device as possible. The traces which connect to these capacitors should be as short and wide as possible to minimize parasitic inductance and resistance. 2. Place feedback resistors close to the FB pin. 3. Keep the sensitive signal (FB) away from the switching signal (LX). 4. Multi-layer PCB design is recommended.

13 FP6382-0.3-DEC-2013 FP6382 /a85T fitipower integrated technology lnc. Outline Information TDFN-12 3 mm x 3mm (pitch 0.45mm) Package (Unit: mm) SYMBOLS UNIT DIMENSION IN MILLIMETER MIN MAX A 0.70 0.80 A1 0.00 0.05 A2 0.18 0.25 D 2.90 3.10 E 2.90 3.10 a 0.35 0.48 b 0.18 0.30 e 0.40 0.50 D1 2.30 2.55 E1 1.55 1.80 Carrier Dimensions Life Support Policy Fitipower’s products are not authorized for use as critical components in life support devices or other medical systems .