CDCM9102_1209 TI1 | Alldatasheet
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25 MHz
100 MHz
www.ti.com SCAS922 –FEBRUARY 2012 Low-NoiseTwo-Channel100-MHzClockGenerator Check forSamples: CDCM9102 1FEATURES 2• IntegratedLow-Noise Clock Generator • Output Enable Pin Shuts OffDevice and IncludingPLL, VCO, and Loop Filter Outputs.
- Two Low-Noise 100-MHz Clocks (LVPECL, • 5-mm × 5-mm QFN-32 Package LVDS, or pairofLVCMOS) • ESD ProtectionExceeds 2 kV HBM, 500 V CDM – Support forHCSL SignalingLevels • IndustrialTemperature Range (–40°C to85°C) (AC-Coupled) • 3.3-VPower Supply – TypicalPeriodJitter:21 ps pk-pk – TypicalRandom Jitter:510 fs APPLICATIONS – Output Type Set by Pins • ReferenceClock GenerationforPCI Express Gen 1,Gen2, and Gen3• Bonus Single-ended25-MHz Output
- General-PurposeClocking• IntegratedCrystalOscillatorInputAccepts 25-MHz Crystal
DESCRIPTION
The CDCM9102 is a low-jitterclockgeneratordesigned to providereferenceclocksforcommunications standardssuch as PCI Express™. The deviceiseasy to configureand use. The CDCM9102 providestwo 100-MHz differentialclockports.The outputtypessupportedfortheseportsincludeLVPECL, LVDS, ora pairof LVCMOS buffers.HCSL signalingissupportedusingan ac-couplednetwork.The user configuresthe output buffertypedesiredby strappingdevicepins.Additionally,a single-ended25-MHz clockoutputportisprovided. Uses forthisportincludegeneral-purposeclocking,clockingEthernetPHYs, or providinga referenceclockfor additionalclockgenerators.Allclocksgeneratedarederivedfroma singleexternal25-MHz crystal. Figure1. CDCM9102 TypicalApplicationExample Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2PCI Expressisa trademarkofPCI-SIG. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2012,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
(thermal pad) NC OS0 VDD2OUT1NOUT1P VDD1 OUT0NOUT0P OE NC NC OSCOUT GNDXIN VDD6REGCAP1VDD5REGCAP2 CDCM9102 SCAS922 –FEBRUARY 2012 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Figure2. CDCM9102 Block Diagram whitespace whitespace whitespace TOP VIEW Figure3. Pin Diagram
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www.ti.com SCAS922 –FEBRUARY 2012 PIN FUNCTIONS NAME QFN32 PIN NO. DESCRIPTION POWER SUPPLIES GND Thermalpad,14,22 Power supplygroundand thermalrelief VDD2 1 Power Supply,OUT1 clockport VDD1 4 Power Supply,OUT0 clockport VDD3 9 Power supply,low-noiseclockgenerator VDD4 16 Power supply,low-noiseclockgenerator VDD5 18 Power supply,low-noiseclockgenerator VDD6 20 Power supply,crystaloscillatorinput REGCAP1 19 Capacitorforinternalregulator,connect10-μF Y5V capacitortoGND REGCAP2 17 Capacitorforinternalregulator,connect10-μF Y5V capacitortoGND DEVICE CONFIGURATION AND CONTROL NC 8,13,15,24–32 No connectionpermitted OE 7 Outputenable/shutdowncontrolinput(seeTable1) OS1 10 Outputformatselectcontrolinputs(seeTable2) OS0 11 RESET 12 Deviceresetinput(active-low)(seeTable3)(1) CRYSTAL OSCILLATOR XIN 21 Parallelresonantcrystalinput(25MHz) DEVICE OUTPUTS OUT0P 6 Output0 – positiveterminal(100MHz) OUT0N 5 Output0 – negativeterminal(100MHz) OUT1P 3 Output1 – positiveterminal(100MHz) OUT1N 2 Output1 – negativeterminal(100MHz) OSCOUT 23 Oscillatoroutputport(25MHz) (1) Forproperdevicestartup,itisrecommended thata capacitorbe installedfrompin12 toGND. See STARTUP TIME ESTIMATION sectionformore details.
ORDERING INFORMATION
TA PACKAGED DEVICES FEATURES CDCM9102RHBT 32-pinQFN (RHB) package,smalltapeand reel –40°C to85°C CDCM9102RHBR 32-pinQFN (RHB) package,tapeand reel ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN TYP MAX UNIT VDDx Supplyvoltagerange(2) –0.5 4.6 V VIN Inputvoltagerange (3) –0.5 VDDx + 0.5 V VOUT Outputvoltagerange(3) –0.5 VDDx + 0.5 V IIN Inputcurrent 20 mA IOUT Outputcurrent 50 mA Tstg Storagetemperaturerange –65 150 °C (1) Stressesbeyond thoselistedunderAbsoluteMaximum Ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderRecommended Operating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Supplyvoltagesmust be appliedsimultaneously. (3) The inputand outputnegativevoltageratingsmay be exceeded iftheinputand outputclamp–currentratingsareobserved Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):CDCM9102
SCAS922 –FEBRUARY 2012 www.ti.com DISSIPATION RATINGS (1)(2) PARAMETER TEST CONDITIONS VALUE, 4 × 4 Viason Pad UNIT θJA Junction-to-ambientthermalresistance 0 LFM 35 ºC/W θJP (3) Junction-to-thermalpad (top)thermalresistance 4 ºC/W (1) The package thermalresistanceiscalculatedinaccordancewithJESD 51 and JEDEC 2S2P (high-Kboard). (2) ConnectedtoGND withsixteenthermalvias(0.3mm indiameter) (3) θJP (junction-to-pad)isused fortheQFN package,because theprimaryheatflowisfromthejunctiontotheGND pad oftheQFN package.
ELECTRICAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES VDDX DC power-supplyvoltage 3 3.3 3.6 V TEMPERATURE TA Ambienttemperature –40 85 °C DEVICE CURRENT CONSUMPTION TA = –40°C to85°C, VDDx = 3.3V,OE = 1,valuesrepresentcumulativecurrent/poweron allVDDx pins. EXTERNALCURRENT DEVICE POWERBLOCK CONDITION RESISTOR POWER(mA) (mW) (mW) Entiredevice,core 85 280current LVPECL 28 42.4 50 OutputBuffers LVDS 20 66 LVCMOS V × ƒout× (CL + 20 × 10–12)× 103 V2 × ƒout× (CL + 20 × 10–12)× 103 DIGITAL INPUT CHARACTERISTICS – RESET, OE, OS1, OS0 TA = –40°C to85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVCMOS INPUTS VIH Inputhighvoltage 0.6VDD V VIL Inputlowvoltage 0.4VDD V IIH Inputhighcurrent VDD = 3.6V,VIL= 0 V 200 µA IIL Inputlowcurrent VDD = 3 V,VIH = 3.6V –200 µA C IN Inputcapacitance 8 10 pF R PU Inputpullupresistor 150 kΩ
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www.ti.com SCAS922 –FEBRUARY 2012 CRYSTAL-OSCILLATOR INPUT-PORT CHARACTERISTICS (XIN) VDD = 3.3V,TA = –40°C to85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CRYSTAL CHARACTERISTICS (External25 MHz Crystal) fXTAL Crystalinputfrequency Fundamentalmode 25 MHz ESR Effectiveseriesresistanceofcrystal 50 Ω C IN On-chiploadcapacitance 8 10 pF XTAL DL Maximum drivelevel-XTAL 0.1 1 mW C SHUNT Maximum shuntcapacitance 7 pF CLOCK OUTPUT BUFFER CHARACTERISTICS (OUTPUT MODE = LVPECL) VDD1, VDD2 = 3.3V;TA = –40°C to85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH Outputhighvoltage VDD – 1.18 VDD – 0.73 V VOL Outputlowvoltage VDD – 2 VDD – 1.55 V |VOD | Differentialoutputvoltage 0.6 1.23 V tR /tF Outputrise/falltime 20% to80% 175 ps ODC Outputdutycycle 45% 55% tSKEW Skew between outputs 20 ps CLOCK OUTPUT BUFFER CHARACTERISTICS (OUTPUT MODE = LVDS) VDD1, VDD2 = 3.3V;TA = –40°C to85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT |VOD | Differentialoutputvoltage 0.247 0.454 V ΔVOD VOD magnitudechange 50 mV VOS Common-mode voltage 1.125 1.375 V ΔVOS VOS magnitudechange 50 mV tR /tF Outputrise/falltime 20% to80% 255 ps ODC Outputdutycycle 45% 55% tSKEW Skew between outputs 30 ps CLOCK OUTPUT BUFFER CHARACTERISTICS (OUTPUT MODE = LVCMOS) VDD1, VDD2 = 3.3V;TA = –40°C to85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH Outputhighvoltage VCC = 3 V to3.6V,IOH = –100 µA VDD – 0.5 V VOL Outputlowvoltage VCC = 3 V to3.6V,IOH = 100 µA 0.3 V tSLEW Outputrise/fallslewrate 20% to80% 2.4 V/ns ODC Outputdutycycle 45% 55% tSKEW Skew between outputs 50 ps OUTPUT JITTER PERFORMANCE fOUT = 100 MHz, VDD = 3.3V,TA = 25°C, jitterintegrationbandwidth10 kHz–20 MHz LVCMOS OUTPUT MODE LVPECL OUTPUT MODE LVDS OUTPUT MODE Random jitter Periodjitter Random jitter Periodjitter Random jitter Periodjitter (fs) (pspk-pk) (fs) (pspk-pk) (fs) (pspk-pk) 507 24.5 510 20.7 533 26.5 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):CDCM9102
50 (2)/c87 V - 2 VDD LVPECL 150 (2)/c87 Phase Noise Analyzer RF 50 /c87 50 /c87 CDCM9102 SCAS922 –FEBRUARY 2012 www.ti.com TEST CONFIGURATIONS Figure4. LVCMOS Output TestLoad Figure5. LVCMOS AC ConfigurationforDevice Test Figure6. LVPECL DC ConfigurationforDevice Test Figure7. LVPECL AC ConfigurationforDevice Test
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www.ti.com SCAS922 –FEBRUARY 2012 Figure8. LVDS DC ConfigurationforDevice Test Figure9. LVDS AC ConfigurationforDevice Test Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):CDCM9102
SCAS922 –FEBRUARY 2012 www.ti.com PERFORMANCE CHARACTERISTICS Figure10. CDCM9102 TypicalPhase Noise Performance (LVPECL Mode) FUNCTIONAL DESCRIPTION DEVICE CONFIGURATION Table1.CDCM9102 Pin ControlofOutput Enable OE (Pin7) MODE DEVICE CORE OUTPUT
0 Power down Power down Hi-Z
1 Normal Active Active
Table2.CDCM9102 Pin ConfigurationofOutput Type CONTROL PINS OUTPUT MODE OS1 (Pin10) OS0 (Pin11) 0 0 LVCMOS, OSCOUT = OFF 0 1 LVDS, OSCOUT = OFF 1 0 LVPECL, OSCOUT = OFF 1 1 LVPECL, OSCOUT = ON
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www.ti.com SCAS922 –FEBRUARY 2012 Table3.CDCM9102 Device Reset RESET (Pin12) OPERATING MODE DEVICE OUTPUTS
0 Devicereset Hi-Z
0 → 1 Clockgeneratorcalibration Hi-Z
1 Normal Active
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25 MHz CSTRAY CPARASITICCL CIN
(Pin 21) /c40 /c41 /c40 /c41 C CΔ S S= -
2 C + C 2 C + CLr La O O
f f CDCM9102 SCAS922 –FEBRUARY 2012 www.ti.com
APPLICATION INFORMATION
CRYSTAL INPUT (XIN)INTERFACE The CDCM9102 implementsa Colpittsoscillator;therefore,one sideofthecrystalconnectstotheXIN pinand theothercrystalterminalconnectstoground.The devicerequirestheuse ofa fundamental-modecrystal,and theoscillatoroperatesinparallelresonancemode. The correctloadcapacitanceisnecessarytoensurethatthe circuitoscillatesproperly.The loadcapacitancecomprisesallcapacitancesintheoscillatorfeedbackloop(the capacitancesseen between theterminalsofthecrystalinthecircuit).Itisimportanttoaccountforallsourcesof capacitancewhen calculatingthecorrectvaluefortheexternaldiscreteloadcapacitanceshown inFigure11. Figure11. ConfigurationofCircuitforCDCM9102 XIN Oscillator The CDCM9102 has been characterizedwith10-pF parallel-resonantcrystals.The inputstageof the crystal oscillatorintheCDCM9102 isdesignedtooscillateatthecorrectfrequencyforallparallel-resonantcrystalswith low-pullcapabilityand ratedwitha loadcapacitancethatisequaltothesum oftheon-chiploadcapacitanceat the XIN pin(CIN = 10 pF maximum), crystalstraycapacitance,and board parasiticcapacitancebetween the crystaland XIN pin.To minimizestrayand parasiticcapacitances,minimizethetracedistanceroutedfrom the crystalto the XIN pinand avoidotheractivetracesand/oractivecircuitryinthe area of the crystaloscillator circuit.Table4 listscrystaltypesthathave been evaluatedwiththeCDCM9102. Table4.CDCM9102 CrystalRecommendations MANUFACTURER PART NUMBER Vectron VXC1-1133 Fox 218-3 Saronix FP2650002 A mismatchoftheloadcapacitanceresultsina frequencyerroraccordingtoEquation1: (1) where: Δƒ isthefrequencyerrorrequiredby theapplication. fisthefundamentalfrequencyofthecrystal. C S isthemotionalcapacitanceofthecrystal.Thisisa parameterinthedatasheetofthecrystal. C 0 istheshuntcapacitanceofthecrystal.Thisisa parameterinthedatasheetofthecrystal. C Lr istheratedloadcapacitanceofthecrystal.Thisisa parameterinthedatasheetofthecrystal. C La istheactualloadcapacitanceimplementedon thePCB (CIN + straycapacitance+ parasiticcapacitance + C L). The differencebetween theratedloadcapacitance(fromthecrystaldatasheet)and theactualloadcapacitance (CLa = C IN + C L + C STRAY + C PARASITIC ) shouldbe minimized.A crystalwitha low pull-abilityrating(lowC S) is ideal. DesignExample: DesiredfrequencytoleranceΔf≤ ±80 ppm CrystalVendor Parameters: IntrinsicFrequencyTolerance= ±30 ppm
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1t = = 0.04 μ s f CDCM9102 www.ti.com SCAS922 –FEBRUARY 2012 C 0 = 7 pF (shuntcapacitance) C S = 10 fF(motionalcapacitance) C Lr = 12 pF (loadcapacitance) SubstitutingtheseparametersintoEquation1 yieldsa maximum valueofC La = 17 pF inordertoachievethe desiredΔf(±50 ppm). RecallthatC La = C IN + C L + C STRAY + C PARASITIC = 8 pF + (CL + C STRAY + C PARASITIC )(1) . Ideally,theloadpresentedtothiscrystalshouldbe 12 pF;thereforethesum of(CL + C STRAY + C PARASITIC )must be lessthan9 pF. Strayand parasiticcapacitancemust be controlled.Thisisbecause theColpittsoscillatoris particularlysensitivetocapacitanceinparallelwiththecrystal;therefore,good layoutpracticeisessential.Itis recommended thatthedesignerextractthestrayand parasiticcapacitancefromtheprintedcircuitboarddesign tooland adjustC L accordinglytoachieveC Lr = C La.Incommon scenarios,theexternalloadcapacitorisoften unnecessary;however,itisrecommended thatpads be implementedtoaccommodate an externalloadcapacitor so thattheppm errorcan be minimized. STARTUP TIME ESTIMATION The CDCM9102 containsa low-noiseclockgeneratorthatcalibratesto an optimaloperatingpointat device power up.Inordertoensureproperdeviceoperation,theoscillatormust be stablepriortothelow-noiseclock generatorcalibrationprocedure.Quartz-basedoscillatorscan take up to 2 ms to stabilize;thereforeitis recommended thattheapplicationensurethattheRESET pinisde-assertedatleast5 ms afterthepower supply has finishedramping.Thiscan be accomplishedby controllingtheRESET pindirectly,or by applyinga 47-nF capacitortogroundon theRESET pin(thisprovidesa delaybecause theRESET pinincludesa 150-kΩ pullup resistor. The CDCM9102 startuptimecan be estimatedbased on parametersdefinedinTable5 and graphicallyshown in Figure12. Table5.CDCM9102 StartupTime Dependencies Parameter Definition Description Formula /Method ofDetermination The reciprocaloftheappliedreferencetREF Referenceclockperiod frequencyinseconds Power-supplyrisetimetolowlimitoftpul Power-uptime(lowlimit) Time requiredforpower supplytoramp to2.27Vpower-on-resettrippoint Power supplyrisetimetohighlimitoftpuh Power-uptime(highlimit) Time requiredforpower supplytoramp to2.64Vpower-on-resettrippoint AfterPOR releases,theColpittsoscillatoris enabled.Thisstart-uptimeisrequiredforthe 500 μs bestcase and 800 μs worstcase (fora crystaltrsu Referencestart-uptime oscillatortogeneratetherequisitesignal input)levelsforthedelayblocktobe clockedby the referenceinput. Internaldelaytimegeneratedfromthe tdelay Delaytime referenceclock.Thisdelayprovidestimefor tdelay= 16,384× tREF = 655 µs thereferenceoscillatortostabilize. VCO calibrationtimegeneratedfromthe referenceclock.ThisprocessselectsthetVCO_CAL VCO calibrationtime tVCO_CAL = 550 × tREF = 22 µsoperatingpointfortheVCO based on thePLL settings. Time requriedforPLL tolockwithin±10 ppmtPLL_LOCK PLL locktime The PLL settlesin12.5μsoffREF (1) C IN = 8 pF (typical),10 pF (maximum).See theCrystalOscillatorInputPortCharacteristics(XIN)table. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):CDCM9102
2.64 2.27 Delay VCO Calibration PLL Lock Time - (S) tPLL_LOCKtVCO_CALtdelaytrsutpuh tpd Power Up Reference Start-Up 5.0 mm,min 2.1 mm, typ 0.33 mm, typ CDCM9102 SCAS922 –FEBRUARY 2012 www.ti.com Figure12. CDCM9102 Start-UpTime Dependencies The CDCM9102 startuptimelimits,tMAX and tMIN ,can now be calculatedas follows tMAX = tpuh + trsu + tdelay+ tVCO_CAL + tPLL_LOCK tMIN = tpul+ trsu + tdelay+ tVCO_CAL + tPLL_LOCK THERMAL MANAGEMENT To ensure optimalperformanceand reliability,good thermaldesignpracticesare importantwhen usingthe CDCM9102. Die temperatureshouldbe limitedto a maximum of 125°C. That is,as an estimate,TA (ambient temperature)plusdevicepower consumptiontimesθJA shouldnotexceed 125°C. The devicepackage has an exposed pad thatprovidestheprimaryheatremovalpathas wellas an electrical groundingto the printedcircuitboard (PCB).To maximize the removalof heat from the package,a thermal landingpatternincludingmultipleviastoa groundplanemust be incorporatedon thePCB withinthefootprintof thepackage.The exposed pad must be soldereddown toensureadequateheatconductionoutofthepackage. A recommended landand viapatternisshown inFigure13. Figure13. Recommended PCB Layout forCDCM9102 POWER SUPPLY FILTERING PLL-based frequencysynthesizersare very sensitiveto noiseon the power supply,which can dramatically increasethejitterofthePLL. Thisisespeciallytrueforanalog-basedPLLs.Thus,itisessentialtoreducenoise from the system power supply,especiallywhen jitter/phasenoiseisvery criticalto applications.A PLL has attenuatedjitterdue topower supplynoiseatfrequenciesbeyond thePLL bandwidthdue toattenuationby the loopresponse. Filtercapacitorsare used to eliminatethe low-frequencynoise from the power supply,where the bypass
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0.1 µF ( 3)/c180 0.1 µF ( 3)/c180 10 µF10 µF PCB Supply L VPECL L VPECL VDDOUT 130 (2)/c87 82 (2)/c87 CDCM9102 www.ti.com SCAS922 –FEBRUARY 2012 capacitorsprovidethe verylow-impedancepath forhigh-frequencynoiseand guard the power supplysystem againstinducedfluctuations.The bypass capacitorsalsoprovidea sourceofinstantaneouscurrentas required by the deviceoutputstages.Therefore,bypass capacitorsmust have low ESR. To properlyuse the bypass capacitors,theymust be placedverycloseto the power supplypinsand must be laidout withshortloopsto minimizeinductance. Figure14 shows a generalrecommendationfordecouplingthepower supply.The CDCXM9102 power supplies fallintoone of two categories:analogsupplies(VDD3, VDD4, and VDD5), and input/outputsupplies(VDD1, VDD2, and VDD6). Shortthe analog suppliestogetherto form the analog supplynode; likewise,shortthe input/outputsuppliestogethertoformtheI/Osupplynode.Isolatetheanalognode fromthePCB power supply and I/Onode by insertinga ferritebead.Thishelpsisolatethehigh-frequencyswitchingnoisesgeneratedby the clockdriversand I/Ofrom thesensitiveanalogsupplynode.Choosing an appropriateferritebead withlow dc resistanceisimportant,as itisimperativetomaintaina voltageatthepower-supplypinoftheCDCM9102 thatis overtheminimum voltageneeded foritsproperoperation. Figure14. CDCM9102 Power Supply Decoupling – Power Pin Bypass Concept OUTPUT TERMINATION The CDCM9102 isa 3.3-Vclockdriverwhichhas thefollowingoptionsfortheoutputtype:LVPECL, LVDS, and LVCMOS. LVPECL TERMINATION The CDCM9102 isan open emitterforLVPECL outputs.Therefore,properbiasingand terminationisrequiredto ensure correctoperationof the deviceand to optimizesignalintegrity.The properterminationforLVPECL is 50 Ω to(Vcc-2)V butthisdc voltageisnotreadilyavailableon a board.Thus a Thevenin’s equivalentcircuitis worked outfortheLVPECL terminationinbothdirect-coupled(dc)and ac-coupledcases,as shown inFigure15 and Figure16.Itisrecommended toplaceallresistivecomponents closetoeitherthedriverend orthereceiver end.Ifthesupplyvoltagesofthedriverand receiveraredifferent,ac couplingisrequired. Figure15. LVPECL Output Termination(DC-Coupled) Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):CDCM9102
150 (2)/c87 50 (2)/c87 L VDS L VDS100 /c87 L VDS 100 /c87 L VCMOS 22 /c87 L VCMOS CDCM9102 SCAS922 –FEBRUARY 2012 www.ti.com Figure16. LVPECL Output Termination(AC-Coupled) LVDS TERMINATION The properLVDS terminationforsignalintegrityover two 50-Ω linesis100 Ω between the outputson the receiverend.Eithera direct-coupled(dc)terminationor ac-coupledterminationcan be used forLVDS outputs, as shown inFigure17 and Figure18.Itisrecommended toplaceallresistivecomponents closetoeitherthe driverend or the receiverend. Ifthe supplyvoltagesof the driverand receiverare different,ac couplingis required. Figure17. LVDS Output Termination(DC Coupled) Figure18. LVDS Output Termination(AC Coupling) LVCMOS TERMINATION Seriesterminationisa common method tomaintainthesignalintegrityforLVCMOS drivers,ifconnectedtoa receiverwitha high-impedanceinput.For seriestermination,a seriesresistor,Rs, isplacedclosetothedriver, as shown in Figure19. The sum of the driverimpedance and Rs shouldbe closeto the transmission-line impedance,which isusually50 Ω.Because theLVCMOS driverintheCDCM9102 has an impedance of30 Ω, Rs isrecommended tobe 22 Ω tomaintainpropersignalintegrity. Figure19. LVCMOS Output Termination
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471 (2)/c87 VDDHCSL HCSL CDCM9102 www.ti.com SCAS922 –FEBRUARY 2012 INTERFACING BETWEEN LVPECL and HCSL (PCIExpress) CertainPCI ExpressapplicationsrequireHCSL signaling.Because thecommon-mode voltageforLVPECL and HCSL are different,applicationsrequiringHCSL signalingmust use ac couplingas shown inFigure20. The 150-Ω resistorsensure properbiasingof the CDCM9102 LVPECL outputstage.The 471-Ω and 56-Ω resistor networkbiasestheHCSL receiverinputstage. Figure20. InterfacingBetween LVPECL and HCSL Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):CDCM9102
www.ti.com 17-Mar-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CDCM9102RHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR CDCM9102RHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCM9102RHBR QFN RHB 32 3000 367.0 367.0 35.0 CDCM9102RHBT QFN RHB 32 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2
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Buyeracknowledgesand agreesthatitissolelyresponsibleforcompliancewithalllegal,regulatoryand safety-relatedrequirements concerningitsproducts,and any use ofTIcomponents initsapplications,notwithstandingany applications-relatedinformationorsupport thatmay be providedby TI.Buyerrepresentsand agreesthatithas allthenecessaryexpertisetocreateand implementsafeguardswhich anticipatedangerousconsequencesoffailures,monitorfailuresand theirconsequences,lessenthelikelihoodoffailuresthatmightcause harm and takeappropriateremedialactions.BuyerwillfullyindemnifyTIand itsrepresentativesagainstany damages arisingoutoftheuse ofany TIcomponents insafety-criticalapplications. Insome cases,TIcomponents may be promotedspecificallytofacilitatesafety-relatedapplications.Withsuch components,TI’s goalisto helpenablecustomerstodesignand createtheirown end-productsolutionsthatmeet applicablefunctionalsafetystandardsand requirements.Nonetheless,such components aresubjecttotheseterms. No TIcomponents areauthorizedforuse inFDA ClassIII(orsimilarlife-criticalmedicalequipment)unlessauthorizedofficersoftheparties have executeda specialagreementspecificallygoverningsuch use. OnlythoseTIcomponents whichTIhas specificallydesignatedas militarygradeor“enhanced plastic”aredesignedand intendedforuse in military/aerospaceapplicationsorenvironments.Buyeracknowledgesand agreesthatany militaryoraerospaceuse ofTIcomponents whichhave not been so designatedissolelyattheBuyer's risk,and thatBuyerissolelyresponsibleforcompliancewithalllegaland regulatoryrequirementsinconnectionwithsuch use. TIhas specificallydesignatedcertaincomponents whichmeet ISO/TS16949 requirements,mainlyforautomotiveuse.Components which have notbeen so designatedareneitherdesignednorintendedforautomotiveuse;and TIwillnotbe responsibleforany failureofsuch components tomeet such requirements. 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