FMS9874

FMS9874 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

• 3-channels
• 108 Ms/s conversion rate
• Programmable Clamps
• 500ps PLL clock jitter
• Adjustable Gain and offset
• Internal Reference V oltage C/SMBus compatible Serial Port
• 100-pin package

Applications

• Flat panel displays and projectors
• RGB Graphics Processing

Description

As a fully integrated analog interface, the FMS9874 can directly digitize RGB graphics with resolutions up to 1024 x 768/85Hz and 1280 x 1024/60Hz; or using alternate pixel sampling, 1600 x 1200/75Hz. ADC sampling clock can be derived from either an external source or incoming horizontal sync signal using the internal PLL. Output data is 24-bit RGB. Setup and control is via registers, accessible through an SMBus/I C com- patible serial port. Input amplitude range is 500–1000mV with either DC or AC coupling. Lower reference of AC coupled inputs is estab- lished with input clamps that are either internally generated or externally provided. Common to the three channels are clamp pulses, a bandgap reference voltage and clocks derived from a PLL or an external source. Digital data levels are 2.5–3.3 volt CMOS compliant. Power can be derived from a single +3.3 V olt power supply. Package is a 100-lead MQFP. Performance specifications are guaranteed over 0°C to 70°C range. Block Diagram Clamp A/D Converter A/D Converter A/D Converter Gain & Offset Clamp Gain & Offset Clamp Gain & Offset DR7-0 DG7-0 DB7-0 RIN GIN BIN Control SDA SCL PWRDN PLL SYNC STRIPPER Timing GeneratorHSIN ACSIN COAST XCK LPF PXCK HS DCSOUT DCK DCK HSOUT INVSCK VREFIN VREFOUTReference CLAMP ICLAMP SCK FMS9874 Graphics Digitizer 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps

Figure 1. Clamping to the back-porch RGB values individually to obtain the same output levels. 1.0 volt can be accommodated. LSB steps through the 6-bit OSR, OSG and OSB registers. Range of adjustment is equivalent to –31 to +32 LSB. the Master Clock source. Two clocks are generated. Sampling clock, SCK is supplied to all three A/D converters. increments using the 5-bit PHASE register. that aligns leading and trailing edges with the output data. picture, if COAST is not used. frames, even and odd pixels can be read on alternate frames. serial port. Four serial addresses are pin selectable.

FMS9874 PRODUCT SPECIFICATION REV. 1.5 11/10/00 Pin Assignments 100-Lead MQFP (KG) No. Name No. Name No. Name No. Name

1 GND 26 GND 51 DB

27 GND 52 DB

28 HSIN 53 DB

4 GND 29 COAST 54 DB

30 GND 55 DB

6 GND 31 V

32 XCK 57 DB

33 LPF 58 DB

34 NC 59 GND 84 GND

10 GND 35 GND 60 V

61 GND 86 DCK

12 GND 37 GND 62 V

87 DCK

39 GND 64 DG

89 DCS

15 GND 40 GND 65 DG

90 GND

41 GND 66 DG

17 GND 42 NC 67 DG

92 GND

18 INVSCK 43 NC 68 DG

93 GND

19 CLAMP 44 NC 69 DG

94 GND

20 SDA 45 NC 70 DG

21 SCL 46 NC 71 GND 96 PWRDN

47 NC 72 V

48 NC 73 NC 98 V

49 GND 74 NC 99 V

75 NC 100 V

PRODUCT SPECIFICATION FMS9874 REV. 1.5 11/10/00 Pin Descriptions Pin Name Pin No. Type/Value Pin Function Description Converter Channels R IN , G IN , B IN 2, 8, 13 Input Analog Inputs. DR 7-0 76–83 Output Red Channel A Data Output. DG 7-0 63–70 Output Green Channel A Data Output. DB 7-0 51–58 Output Blue Channel A Data Output. Timing Generator CLAMP 19 Input External Clamp Input. INVSCK 18 Input Invert Sampling Clock. Inverts SCK, the internal clock sampling the analog inputs. Supports Alternate Pixel Sampling mode for capture pixel rates up to 216Ms/s. XCK 32 Input External Clock input. Enabled if register bit, XCKSEL = H. Replaces PXCK clock generated by PLL. If unused, connect to ground through a 10k Ω resistor. DCK 86 Output Output Data Clock. Clock for strobing output data to external logic. DCK

87 Output

Output Data Clock Inverted. Inverted clock for strobing output data to external logic. HSOUT 88 Output Horizontal Sync Output. Reconstructed HSYNC delayed by FMS9874 latency and synchronized with DCK. Leading edge is synchronized to start of data output. Polarity is always active HIGH. Phase Locked Loop HSIN 28 Schmitt Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V source should be clamped at 3.3V or current limited to prevent overdriving ESD protection diodes. COAST 29 Input PLL Coast. Maintain frequency of PLL output clock PXCK, disregarding HSIN. If horizontal sync is missing during the vertical sync interval, PXCK clock frequency can be maintained by asserting COAST. LPF 33 Passive PLL Low Pass Filter. Connect recommended PLL filter to LPF pin. (see Figure 13.) Sync Stripper ACS IN Analog Composite Sync Input. Input to sync stripper with 150mV threshold. DCS OUT 89 Digital Composite Sync Output. Output from sync stripper. Control SDA 20 Bi-directional Serial Port Data. Bi-directional data. SCL 21 Input Serial Port Clock. Clock input. A0 22 Input Address bit 0. Lower bit of serial port address. A1 23 Input Address bit 1. Upper bit of serial port address. PWRDN 96 Input Power Down/Output Control. Powers down the FMS9874 and tri-states the outputs.

PRODUCT SPECIFICATION FMS9874 5 REV. 1.5 11/10/00 Pin Descriptions Addressable Memory Register Map Pin Name Pin No. Pin Function Description Power and Ground VDDA 3, 5, 9, 11, 14, 16, 95, 99, 100 ADC Supply Voltages. Provide a quiet noise free voltage. VDDP 24, 25, 31, 36, 38 PLL Supply Voltage. Most sensitive supply voltage. Provide a very quiet noise free voltage. VDDO 50, 60, 62, 72, 85, 91 Digital Output Supply Voltage. Decouple judiciously to avoid propagation of switching noise. GND 1, 4, 6, 10, 12, 15, 17, 26, 27, 61, 71, 84, 90, 92, 93, 94 Ground. Returns for all power supplies. Connect ground pins to a solid ground plane. VREFIN 98 Voltage Reference Input. Common reference input to RGB converters. Connect to VREFOUT, if internal reference is used. VREFOUT 97 Voltage Reference Output. Internal band-gap reference output. Tie to ground through a 0.1µF capacitor. Name Address Function Default (hex) PLLN11-4 00 PLL divide ratio, MSBs. PLLN + 1 = total number of pixels per horizontal line. 69 (1693) PLLN3-0 01 PLL divide ratio, LSBs. PLLN + 1 = total number of pixels per horizontal line. PLLN3-0 stored in the four upper register bits 7-4. D0 (1693) GR7-0 02 Gain, red channel. Adjustable from 70 to 140%. 80 GG7-0 03 Gain, green channel. Adjustable from 70 to 140%. 80 GB7-0 04 Gain, blue channel. Adjustable from 70 to 140%. 80 OSR5-0 05 Offset, red channel. OSR5-0 stored in the six upper register bits 7-2.Default value is decimal 32. OSG5-0 06 Offset, green channel. OSR5-0 stored in the six upper register bits 7-2. Default value is decimal 32. OSB5-0 07 Offset, blue channel. OSR5-0 stored in the six upper register bits 7-2. Default value is decimal 32. CD7-0 08 Clamp delay. Delay in pixels from trailing edge of horizontal sync. CW7-0 09 Clamp width. Width of clamp pulse in pixels. 80 CONFIG 1 0A Configuration Register No. 1 F4 PHASE7-0 0B Sampling clock phase. PHASE4-0 stored in upper register bits 7-3. PHASE sets the sampling clock phase in 11.25° increments. Default value is decimal 16. PLLN3–0 X X X XX OSR5–0 X X OSG5–0 X X OSB5–0 X X PHASE4–0 X X X

PRODUCT SPECIFICATION FMS9874 6 REV. 1.5 11/10/00 Register Definitions PLL Configuration Register (0C) PLLCTRL 0C PLL Control 24 CONFIG 2 0D Configuration Register No. 2 00 0E Reserved 0X 0F Reserved 00 Configuration Register 1 (0A) Bit no. Name Type Description 1 XCKSEL R/W External Clock Select. Select internal clock source. 0: Internal PLL 1: XCK input. 2 XCLAMPOL R/W External Clamp Polarity. Select clamp polarity. 0: Active L. 1: Active H. 3 XCLAMP R/W External Clamp Select. Select clamp source. 0: Internally generated by PLL referenced to HSIN. 1: External CLAMP input. 4 COASTPOL R/W Coast Polarity. Select COAST input polarity. 0: Active L. 1: Active H. 5 HSPOL R/W HSIN Polarity. Select horizontal sync input polarity. PLL is locked to selected edge: 0: Falling edge. 1: Rising edge. 6 — R/W 0: Default must be 0. 7 — R/W 0: Default must be 0. Bit no. Name Type Description 1-0 — 4-2 IPUMP 2-0 R/W Charge Pump Current. Selects Charge Pump current (µA). (see Table 5. Charge Pump Current Codes) 000: 50 001: 100 010: 150 011: 250 100: 350 101: 500 110: 750 111: 1500 6-5 FVCO 1-0 R/W VCO Frequency Range. Selects VCO frequency range (MHz). 00: 20–90 01: 20–90 10: 80–108 11: — 7 — R/W Reserved. 0: Run. 1: (reserved). Name Address Function Default (hex)

FMS9874 PRODUCT SPECIFICATION REV. 1.5 11/10/00 7 Configuration Register 2 (0D) Bit no. Name Type Description 0— — Reserved. Set to 0. 4 OUTPHASE W Output Data Phase. In the alternate pixel mode, selects either odd (1, 3, 5, …) or even (2, 4, 6 ….) samples following the HSYNC leading edge to be emitted from output data ports. 0: Even samples 1: Odd samples 7-5 - R/W Reserved. Set to 00. Functional Description There are two major sections within the FMS9874 Digitizer: 1. Analog-to-digital Converter Channels, one for each channel, RGB and the voltage reference. 2. Timing and Control comprising the PLL, Timing Generator, Sync Stripper and Serial Interface. A/D Converter Channels Each of the three RGB channels consists of: 1. A clamp to set the lower reference level of an AC coupled input. 2. Gain and offset stages to tune the converter to input signal levels. 3. An Analog-to-Digital Converter to digitize the analog input. Analog Inputs Input signal range is 500 to 1000mV to support conversion of single-ended signals with a typical amplitude of 700mV p-p. With the clamp active, each input accommodates a negative 300mV excursion. Inputs are optimized for a source resistance of 37.5 to 75Ω. To reduce noise sensitivity, the ultra-wide 500MHz input bandwidth may be reduced by adding a small series inductor prior to the 75Ω terminating resistor. See Applications Section. Clamps If the incoming signals are not ground referenced, a clamp must be used to set the incoming video range relative to ground. Prior to each A/D converter, each channel includes a clamp that allows a capacitively coupled input to be referenced to the A/D converter bottom reference voltage when the clamp pulse is active. Source of the clamp signal is deter- mined by the XCLAMP bit. Internal clamp timing is generated by the Timing and Con- trol Block. Position and width of the internal clamp pulse, ICLAMP are programmable through registers CD and CW. External clamp input is selected by register bit XCLAMP and the external clamp polarity selected through register bit XCLAMPOL. To disable the clamp for DC coupled inputs, set XCLAMP = 1 with either of these conditions: 1. XCLAMPOL = 0 with input CLAMP = H. 2. XCLAMPOL = 1 with input CLAMP = L. Best performance will be achieved with the clamp set active for most of the black signal level interval between the trailing edge of horizontal sync and the start of active video. Insufficient clamping can cause brightness changes at the top of the image and slow recovery from large changes in Average Picture Level (APL). Recommended value of CD is 0x10 to 0x20 for most standard video sources. Analog-to-Digital Converter Figure 2 is a block diagram of the ADC core with gain and offset functions. G 7-0, OS5-0, RGBIN and PD7-0 generically refer to the gain and offset register values, analog input and parallel data output of any RGB channel.

Figure 2. A/D Converter Architecture

1. Differential track and hold.
2. Differential analog-to-digital converter.

range is defined by the gain setting according to Table 1. Table 1. Gain Calibration voltage centered around A/D common mode bias voltage.

1. I BIAS to establish the A/D common mode voltage.
2. I OFFSET to set the offset from the common mode level.

Table 2. Offset Calibration Picture quality is strongly impacted by the PHASE4-0 value. sisting of vertical lines may exhibit tearing.

255 G 70–+

Figure 7. Output Timing if odd or even samples are directed to the data ports.

1. HSOUT is always active HIGH.
2. Only the leading edge of HSOUT is active or selected by
3. HSOUT is aligned with DCK.
4. Trailing edge is linked to HSIN.
5. If MSIN does not terminate before mid-line, HSOUT is

is the internal A/D converter sampling clock. before valid data is available. Figure 8. Normal Mode

5 PIPE DELAY

Figure 9. Alternate Pixel Sampling Mode, (Even Pixels) Figure 10. Alternate Pixel Sampling Mode, (Odd Pixels)

5.5 PIPE DELAY

1. The PLL is run at half rate. SCK, DCK and DCK are
2. CKINV is toggled between frames.

Figure 11. Odd and Even Pixels in a Frame Figure 12. Odd Pixels from Frame 1

Generator and Sync Stripper.

1. Data clocks DCK and DCK .
2. Internal sampling clock SCK.

with polarity selected by the HSPOL bit. grammed to match the incoming video source to be captured. video outputs does not comply with VESA recommendations. ceramic capacitors with X7R dielectric are recommended. Table 3. Recommended IPUMP and FVCO values for Standard Display Formats1

25.175 MHz

31.500 MHz

36.000 MHz

720 X 400

50 MHz

62.5 MHz

63 MHz

56.6 MHz

40.000 MHz

50.000 MHz

49.500 MHz

56.250 MHz

Figure 13. Even Pixels from Frame 2 Figure 14. Subsequent Output Figure 15. Combined Frames

1. VESA Monitor Timing Standards and Guidelines, September 17, 1998 and others.

65.000 MHz

75.000 MHz

78.750 MHz

85.500 MHz

94.500 MHz

Table 3. Recommended IPUMP and FVCO values for Standard Display Formats1 (continued) Figure 16. Schematic, PLL Filter.

1. VCO frequency range through FVCO 1-0. (see Table 4)
2. Charge Pump Current through IPUMP 2-0. (see Table 5)
3. External loop filter component values.

rises but can be reduced by over-sampling at a 2X clock rate. See Performance section for jitter specifications and plots.

1. HSOUT rising edge tracks HSIN delayed by a few pixels.
2. HSOUT falling edge tracks the trailing edge of HSIN

depends upon the state of HSIN. a.) HSOUT rising edge remains locked to the PLL. a.) HSOUT rising edge remains locked to the PLL.

1. If HSIN = L, then HSOUT = L

Table 4. VCO Frequency Bands Table 5. Charge Pump Current Levels

1. Internal sampling clock, SCK.
2. Output data clocks, DCK and DCK .
3. Output horizontal sync, HS OUT.
4. Internal clamp pulse, ICLAMP.

CD register. Width of ICLAMP is set by the CW register. Range of CD and CW values is 1–255 pixels. PWRDN = L minimizes FMS9874 power consumption. and the internal voltage reference function. resistors if SDA and SCL signals originate from 5V logic. Table 6. Serial Interface Address Codes while SCL = H is interpreted as a start or stop signal.

PRODUCT SPECIFICATION FMS9874 16 REV. 1.5 11/10/00 After each byte is read, the pointer auto-increments to allow multiple data byte transfers within one read cycle. Preceding each slave write, there must be a start cycle. Following the pointer byte there should be a stop cycle. After the last read, there must be a stop cycle comprising a LOW-to-HIGH transition of SDA while SCL is HIGH. (see Figure 18, right waveform) A repeated start signal occurs when the master device driv- ing the serial interface generates a start signal without first generating a stop signal to terminate the current communica- tion. This is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines. Serial Interface Read/Write Examples Examples below show how serial bus cycles can be linked together for multiple register read and write access cycles. For sequential register accesses, each ACK handshake ini- tiates further SCL clock cycles from the master to transfer the next data byte. Write to one register 1. Start signal 2. Slave Address byte (R/W bit = LOW) 3. Pointer byte 4. Data byte to base address 5. Stop signal Write to four consecutive registers 1. Start signal 2. Slave Address byte (R/W bit = LOW) 3. Pointer byte 4. Data byte to base address 5. Data byte to (base address + 1) 6. Data byte to (base address + 2) 7. Data byte to (base address + 3) 8. Stop signal Read from one register 1. Start signal 2. Slave Address byte (R/W bit = LOW) 3. Pointer byte (= base address) 4. Stop signal (optional) 5. Start signal 6. Slave Address byte (R/W bit = HIGH) 7. Data byte from base address 8. Stop signal Read from four registers 1. Start signal 2. Slave Address byte (R/W bit = LOW) 3. Pointer byte (= base address) 4. Stop signal (optional) 5. Start signal 6. Slave Address byte (R/W bit = HIGH) 7. Data byte from base address 8. Data byte from (base address + 1) 9. Data byte from (base address + 2) 10. Data byte from (base address + 3) 11. Stop signal

FMS9874 PRODUCT SPECIFICATION REV. 1.5 11/10/00 17 Absolute Maximum Ratings (beyond which the device may be damaged)1 Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. 5. EIAJ test method. Operating Conditions Parameter Min Typ Max Unit Power Supply Voltages V CC (Measured to GND) -0.5 4 V Digital Inputs Applied voltage (Measured to GND) 2 -0.3 V DDA V Forced current 3, 4 -5.0 5.0 mA Analog Inputs Applied Voltage (Measured to GND) 2 -0.5 V DDA V Forced current 3, 4 -10.0 10.0 mA Digital Outputs Applied voltage (Measured to GND) 2 -0.5 V Forced current 3, 4 -6.0 6.0 mA Forced current 3, 4 -8.0 8.0 mA Short circuit duration (single output in HIGH state to ground) 1 second Temperature Junction 150 °C Lead Soldering (10 seconds) 300 °C Vapor Phase Soldering (1 minute) 220 °C Storage -65 150 °C Electrostatic Discharge 5 ±150 V Parameter Min Nom Max Units VDDA ADC Power Supply Voltage 3.0 3.3 3.6 V VDDP PLL Power Supply Voltage 3.0 3.3 3.6 V VDDO Output Power Supply Voltage 2.2 3.3 3.6 V TA Ambient Temperature, Still Air 0 70 °C A/D analog input range, min. 500 mV p-p A/D analog input range, max. 1000 mV p-p

PRODUCT SPECIFICATION FMS9874 18 REV. 1.5 11/10/00 Electrical Characteristics1 Notes: 1. Unless otherwise stated, 0 to 70 °C 2. DCK, DCK load = 15 pF; data load = 5 pF. Parameter Conditions Min Typ Max Unit Power Supply Currents I DDA Supply current, ADC Operating, 25 °C 211 mA IDDD Supply current2, Digital Output Operating, 25 °C4 7 m A IDDP Supply current, PLL Operating, 25 °C3 0 m A PD Power dissipation 0 to 70 °C 800 mW IPD Power-down current 0 to 70 °C2 3 m A PDD Powered-down disspation 0 to 70 °C1 0 m W Digital Inputs/Outputs CI Input Capacitance 25 °C3 p F IIH Input Current, HIGH 0 to 70 °C- 1 µ A IIL Input Current, LOW 0 to 70 °C+ 1 µ A VIH Input Voltage, HIGH 0 to 70 °C 2.5 V VIL Input Voltage, LOW 0 to 70 °C 0.8 V IOHD Output Current, HIGH, data 0 to 70 °C4 m A IOHC Output Current, HIGH, clock 0 to 70 °C8 m A IOLD Output Current, LOW, data 0 to 70 °C4 m A IOLC Output Current, LOW, clock 0 to 70 °C8 m A VOH Output Voltage, HIGH I OH = max., 0 to 70°CV DDO–0.1 V VOL Output Voltage, LOW (VDD3)I OL = max., 0 to 70°C 0.1 V Serial Bus I/O V SMIH Input Voltage, HIGH 0 to 70 °C 2.5 V VSMIL Input Voltage, LOW 0 to 70 °C 0.8 V VSMOL Output Voltage, LOW I SMOL = max. 0.1 V ISMOH Output Current, HIGH 0 to 70 °Cµ A ISMOL Output Current, HIGH 0 to 70 °Cm A Analog Inputs I B Input bias current 0 to 70 °C1 µ A EOS Input Offset Voltage 0 to 70 °C 7 50 mV Reference Output Output Voltage 0 to 70 °C 1.20 1.25 1.30 V Temperature Coefficient 0 to 70 °C ±50 ppm/ °C

FMS9874 PRODUCT SPECIFICATION REV. 1.5 11/10/00 19 Switching Characteristics Notes: 1. FVCO = 10, IPUMP = 110, PLLN = 1375 10. Parameter Conditions Min. Typ. Max. Unit Analog-to-Digital Converters Conversion rate 0 to 70 °C 10 108 Ms/s tSKEW Data to clock skew 0 to 70 °C -0.5 2.0 ns Timing Generator HSIN input frequency 0 to 70 °C 15 110 kHz Maximum PLL clock rate 0 to 70 °C 108 MHz Minimum PLL clock rate 0 to 70 °C 20 MHz PLL Jitter1 25°C 1.8 µs p-p Sampling phase tempco 0 to 70 °C 15 ps/ °C Serial Bus Interface tDAL SCL Pulse Width, LOW 0 to 70 °C 4.7 µs tDAH SCL Pulse Width, HIGH 0 to 70 °C 4.0 µs tSTAH SDA Start Hold Time 0 to 70 °C 4.0 µs tSTASU SCL to SDA Setup Time (Stop) 0 to 70 °C 4.7 µs tSTOSU SCL to SDA Setup Time (Start) 0 to 70 °C 4.0 µs tBUFF SDA Stop Hold Time Setup 0 to 70 °C 4.7 µs tDSU SDA to SCL Data Setup Time 0 to 70 °C 250 ns tDHO SDA to SCL Data Hold Time 0 to 70 °C0 n s System Performace Characteristics Parameter Conditions Min Typ 1 Max Unit Analog to Digital Converter E LI Integral Linearity Error 25 °C -1.4 ±0.8 1.4 LSB 0 to 70°C -2.5 2.5 LSB ELD Differential Linearity Error 25 °C -1.0 ±0.5 1.15 LSB 0 to 70°C -1.0 1.25 LSB Missing Codes 0 to 70 °C0 Input full scale matching 0 to 70 °C 5 %FS Offset adjustment range 0 to 70 °C 25 %FS Gain tempco 25 °C 280 ppm/ °C BW Analog bandwidth, full power 25 °C 500 MHz Transient response 25 °C2 n s tOV Over-voltage recovery time 25 °C 1.5 ns SNR SNR without harmonics 45 dB

Figure 21. Pixel Clock Jitter vs. Frequency

be matched to the incoming analog signals. operates with 3.3V levels, these resistors are unnecessary. Figure 22. Schematic, VGA Digitizer, AC Coupled RGB

1 RED

1. Keep analog trace lengths short to minimize crosstalk.
2. Terminate analog inputs with 75 Ω resistors, placed
3. Layout traces as 75 Ω transmission lines.
4. Avoid running analog traces near digital traces. Due to

easily leak into analog inputs.

1. If necessary, limit bandwidth by adding a ferrite bead in
2. Locate the PLL filter clear of other signals.
3. Bypass the reference with a 0.1µF capacitor to ground.

Figure 23. RGB Input Filter Option

1. Route digital I/O signals clear of analog inputs.
2. Terminate clock lines to reduce reflections. Treat clock

lines as transmission lines.

1. Scale the HSIN input to 3.3V , using a resistor network
2. Limit Serial Port inputs SDA and SDL with 150 Ω resis-

tors connected directly to the pins.

1. If necessary terminate the HSIN input with 330/220 Ω.
2. If necessary, to reduce reflections, EMI or spikes add a

50–200Ω resistor at each data output pin.

1. To minimize noise within the FMS9884A, restrict the

capacitive load at the digital outputs to < 10pF.

1. Analog and digital circuits are layed out over a common
2. Each FMS9874 pin is decoupled with a 0.1µF capacitor.
3. A group of pins may be de-coupled through a common

capacitor if no pin is more than 5 mm from the capacitor.

1. A separate regulated supply is used for the phase-locked
2. Capacitors are attached to each PLL pin or pin-pair.

Figure 24. Recommended Power Distribution

1. All components should be placed in close proximity to
2. Routing through vias should be avoided, if possible.

use as many capacitor pairs as possible.

1. Set the value of PLLN equal to the number of pixels to

samples per horizontal line equals the number of pixels. pattern on a vertical grill pattern.

1. Calibrate Offset and Gain by first setting each input to

(same value), typically 240 decimal.

1. Clamp registers, CD and CW, should be programmed to
2. PHASE must be trimmed to minimize onscreen snow
3. FVCO must be set to encompass the incoming
4. IPUMP must be set to minimize intensity noise.

PRODUCT SPECIFICATION FMS9874 24 REV. 1.5 11/10/00 Mechanical Dimensions 100-Lead MQFP (KG) Package D D1/2 e A A1 B Base Plane Seating Plane See Lead Detail -C- ccc C LEAD COPLANARITY Notes: All dimensions and tolerances conform to ANSI Y14.5M-1994. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254mm per side. "N" is the number of terminals, 25 per side. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm in excess of the "b" dimension at the maximum material condition. A — 2.82 3.00 Symbol Millimeters Min. Typ. Max Notes A1 0.15 —— 2.67A2 2.62 2.77 D2 12.00 BSC L 0.73 0.88 1.03 100

0.50 BSC

3, 5 D N e D1 14.00 BSC

17.20 BSC

b 0.17 — 0.27 0–7° 0° Min. 1.60 Ref. Datum Plane Lead Detail L .40 Min. 0.13 R Min. .13/.30 R

PRODUCT SPECIFICATION FMS9874 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 11/10/00 0.0m 003 Stock#DS30009874  2000 Fairchild Semiconductor Corporation

Ordering Information

Product Number Temperature Range Screening Package Package Marking FMS9874KGC100 0 °C to 70°C Commercial 100 Lead MQFP 9874KGC100 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.