FMS7401

FMS7401 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

• 8-bit Microcontroller Core
• 1K bytes on-board code EEPROM
• 64 bytes data EEPROM
• 64 bytes SRAM
• W atchdog Reset
• Multi-input Wakeup on all general purpose I/O pins
• F ast 12-bit PWM timer with dead time control and half- bridge output drive – Input Capture Mode
• 5-Ch 8-bit Analog-to-Digital Converter – 20 µS conversion time – Sample and Hold – Internal V oltage Reference (1.21V) – Gated Auto-sampling Mode
• Auto-zero Amplifier (gain 16)
• Uncommitted Amplifier
• Internal Current Source Generator (1mA)
• On-chip Oscillator – No external components – 1µs instruction cycle time
• On-chip Power-on Reset
• Programmable read and write disable functions
• Memory Mapped I/O
• Programmable Comparator (63 Levels)
• Brown-out Reset
• Software selectable I/O option
• Push-pull outputs with tri-state option
• W eak pull-up or high impedance inputs
• Fully static CMOS – Power Saving Halt Mode – FMS7401L (< 1.3µA @ 3.3V) – Power Saving Idle Mode – FMS7401L (< 180µA @ 3.3V)
• Single supply operation – 10V – 13.5V (FMS7401)* – 2.7V – 3.6V (FMS7401L)
• 40 years data retention
• 100,000 data changes
• 8-/14-pin PDIP, SOIC, and TSSOP packages
• In-circuit programming – Fast Page-write Programming Mode FMS7401/7401L Digital Power Controller * Contact your local Fairchild Sales Representative for FMS7401 availability. Device Supply Voltage Program Memory (bytes) Data Memory (bytes) I/O Pin CountSRAM Data EEPROM FMS7401L 2.7V – 3.6V 1K 64 64 6 8 FMS7401L 2.7V – 3.6V 1K 64 64 8 14 FMS7401* 10V – 13.5V 1K 64 64 8 14

Figure 1. FMS7401/7401L Block and Connection Diagram

PRODUCT SPECIFICATION FMS7401/7401L REV. 1.0.2 6/23/04 FMS7401/7401L Pin Definitions Pin Number Pin Name Pin Function Description 8-Pin 14-Pin PDIP SOIC TSSOP PDIP SOIC TSSOP 13 1 G4/AIN0 General purpose I/O port (bit 4 of the I/O configuration registers). AIN0 analog input of the ADC (autozero amplifier’s positive terminal). Programmable Comparator non-inverting input, if COMPSEL=0. 24 3 GND Digital ground pin. 35 6 G2/AIN2 General purpose I/O port (bit 2 of the I/O configuration registers). AIN2 analog input of the ADC. Programmable Comparator non-inverting input, if COMPSEL=1. 46 7 G1/AIN3/ ADSTROBE General purpose I/O port (bit 1 of the I/O configuration registers). AIN3 analog input of the ADC. External digital clock input. PWM Timer 1’s ADSTROBE output. 57 9 G3/AIN1 General purpose I/O port (bit 3 of the I/O configuration registers). AIN1 analog input of the ADC. Internal current source generator pin. 68 1 0 G0/ T1HS1 General purpose I/O port (bit 0 of the I/O configuration registers). PWM Timer 1’s T1HS1 output. 71 1 2 G5/ T1HS2 General purpose I/O port (bit 5 of the I/O configuration registers). PWM Timer 1’s T1HS2 output. 82 14 VCC Supply voltage input for the FMS7401L. In the FMS7401, Vcc is the regulated output. –– 2 SR_GND AIN0 analog input of the ADC (autozero amplifier’s negative terminal). SR_GND is internally connected to GND in the 8-pin FMS7401L. –– 4 G6/-A IN General purpose I/O port (bit 6 of the I/O configuration registers). Uncommitted amplifier negative analog input. –– 5 G7/AIN4/ A OUT General purpose I/O port (bit 7 of the I/O configuration registers). AIN4 analog input of the ADC. Uncommitted amplifier analog output. –– 8A GND Analog ground for the FMS7401. In the FMS7401L, AGND is internally connected to GND. Externally, AGND should be left unconnected or connected to GND. –– 11 RESET Active low external reset input. –– 13 VDD High voltage supply input for the FMS7401. In the FMS7401L, VCC is internally connected to VDD. Externally, VDD should either be left unconnected or connected to VCC.

FMS7401/7401L PRODUCT SPECIFICATION REV. 1.0.2 6/23/04 Table of Contents FMS7401/7401L General Description

1 Reset Circuit

2 Clock Circuit

3 Power Saving Modes

4 ADC Circuit

5 Programmable Comparator Circuit

6 PWM Timer 1 Circuit

7 Timer 0 Circuit

8 I/O Ports

9 Multi-input Wakeup Circuit

PRODUCT SPECIFICATION FMS7401/7401L REV. 1.0.2 6/23/04 10 8-Bit Microcontroller Core

11 Device Memory

12 In-circuit Programming Specification

Ordering Information

Table 3. PLL Frequency Selection (F Table 9. Programmable Comparator Lower Voltage Reference V Table 10. Programmable Comparator Upper Voltage Reference V Table 13. PLL Divide Factor Selection Bits and the F

• P ower-on Reset (POR)
• External Reset
• Brown-out Reset (BOR)
• W atchdog Reset

Table 1. Default Register States

1.1 FMS7401L Power-on Reset Circuit

the Electrical Characteristics section of the datasheet. circuit and must be enabled by the BOREN bit of the Initialization Register 1.

1.2 FMS7401L External Reset

input tri-state configuration unless defaulted otherwise.

1.3 FMS7401L Brown-out Reset Circuit

BOREN bit of the Initialization Registers 1. operation executing the instruction program residing in the code EEPROM memory. All other memory mapped register not listed above.

POR circuit if Vcc does not fall below 0.7V . Figure 2. BOR and POR Circuit Relationship Diagram

1. Available only on the 14-pin package option.
2. Refer to the Timer 0 Circuit section of the datasheet for details regarding the Watchdog Reset.
3. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
4. Refer to the Device Memory section of the datasheet for details regarding the Initialization Register 1.
5. Refer to Table 28 and Table 29 of the Device Memory section of the datasheet for details.

h i g h f o r a r o u n d 1 µ s .

clock source is selectable by the CMODE bit of the Initialization Register 1. internal oscillator runs continuously unless entering Halt Mode or using an external clock source. Table 2. CMODE Bit Definition device should be provided through the AIN3/G1 input. (see Figure 3 and Figure 4).

2.1 PLL

quency keeping the total current consumption low. be enabled by setting the PLLEN bit of the PSCALE register. Once set, the PLL is turned on and begins the locking phase. quency and in phase. The PLLEN bit may not be changed while the PWM Timer 1 circuit is in run mode. to this bit during this condition will not change its value. to this bit during these conditions will not change its value.

0 Internal Oscillator (@ FOSC)

1 External digital clock (G1/AIN3)

ICLK’s source on-the-fly during normal instruction execution in order to speed-up a particular action. section of the datasheet for details. Figure 3. Internal Clock Scheme

Figure 4. External Clock Scheme

1. Refer to the Device Memory section of the datasheet for details regarding the Initialization Registers 1.
2. The upper FOSC frequency (4MHz) is not a standard feature offered on the FMS7401/7401L devices but is available upon request.
3. The ADCNTRL2 register is defined in the ADC Circuit section of the datasheet.
4. The PSCALE register is defined in the PWM Timer 1 Circuit section of the datasheet.
5. Software must always configure the device’s entire clocking structure (see Figure 3 and Figure 4) while the PWM Timer 1 circuit is off (T1C0=0) and configured in
6. The PLL’s F(FS=0) output is not affected by the FS[1:0] bit value of the PSCALE register and merely shares the FS[1:0]=00 divide factor.

3.1 Halt Mode

ulator circuit remains enabled while in Halt Mode. The device can exit Halt Mode only by the Multi-input Wakeup (MIW) circuit.

2 Therefore, prior to entering Halt Mode, soft-

Mode, software must clear the Power Mode Clear (PMC) register by using only the “LD M, #” instruction (see Figure 5). Table 4. HALT Register Definition Figure 5. Recommended Halt/Idle Flow

3.1.1 PLL Steps for Halt Mode

FMS7401/7401L PRODUCT SPECIFICATION 14 REV. 1.0.2 6/23/04 enabled, it must complete the lock phase before software may enable the use of the outputs to clock any of the device circuits. Therefore, upon exiting Halt Mode software must wait the TPLL_LOCK3 to ensure that the PLL is locked into its appropriate frequency and in phase. 1. Initially, the PLLEN bit of the PSCALE register must be set in order to enable the PLL circuit. 2. If the PLL outputs are to be used to clock any of the device circuits, FMODE and/or FSEL of the PSCALE register must be set after the appropriate TPLL_LOCK wait time.4 3. Prior to entering Halt Mode, software must clear both FMODE and FSEL (the PWM Timer 1 must be disabled in order to clear either bit) keeping the PLLEN bit 1. 4. Using a separate instruction (e.g. RBIT PLLEN, PSCALE) disable the PLL by clearing the PLLEN bit. 5. Software may then instruct the device to enter Halt Mode. 6. If all disabled circuits must be re-enabled after exiting from Halt Mode, repeat all initial steps enabling all circuits in the appropriate order as well as waiting T PLL_LOCK.

3.2 Idle Mode

In addition to the Halt Mode power saving feature, the device also supports an Idle Mode operation. The device is placed into Idle Mode by setting the Idle enable bit (EIDLE) of the HALT register through software using either the “LD M, #” or the “SBIT #, M” instructions. EIDLE is a write only bit and is automatically cleared upon exiting Idle Mode. The Idle Mode operation is similar to Halt Mode except the internal oscillator, PLL, and Timer 0 circuits remain active while the other on-chip systems including the Programmable Comparator (COMP) and Brown-out Reset (BOR) circuits are shut down. For the FMS7401, to maintain proper Vcc voltage regulation, the internal regulator circuit remains enabled while in Idle Mode. The device exits Idle Mode automatically by the Timer 0 Idle overflow every 8192 cycles and by the Multi-input Wakeup (MIW) circuit. 2 Software must first configure the MIW prior to entering Idle Mode in order to wake the device from Idle with- out waiting for the overflow to occur. Once a wake from Idle Mode is triggered, the normal device execution resumes by the next clock cycle. Immediately after exiting Idle Mode, software must clear the Power Mode Clear (PMC) register by using only the “LD M, #” instruction (see Figure 5

3.2.1 PLL Steps for Idle Mode

When using Idle Mode, the PLL does not need to be disabled prior to entering Idle as it does with Halt Mode. The PLL may remain enabled the entire time the device is in Idle; however, the device will consume additional current. If current consump- tion is important, consider using Halt instead of Idle Mode or at least disabling the PLL while in Idle. By keeping the PLL enabled while in Idle Mode, the PLL’s outputs remain ready for use at any moment. With the PLL’s out- puts available, software has the option to source the main system clock (F ICLK) by the PLL’s F(FS=0) output when the FMODE bit of the PSCALE register is set.4 In addition, if the PLL’s FPWMCLK output is clocking the PWM Timer 1 circuit,5 the timer may remain operational while in Idle Mode. However, the total current consumption will increase, hence the recommendation to disable the PWM Timer 1 before entering Idle Mode. In contrast, if F ICLK is clocking the PWM Timer 1, the timer circuit execution (like the main system controller) is stopped during Idle. Whether the PWM Timer 1 is operational or not during Idle Mode, the instruction execution is stopped therefore all pending flags, etc. cannot be serviced. If the PLL is to be disabled prior to entering Idle Mode, software must take the appropriate steps in order to keep the integrity of the clock structure. Once the PLL is disabled, all output frequencies are turned off. If the PLL is re-enabled, it must com- plete the lock phase before software may enable the use of the outputs to clock any of the device circuits. Therefore, upon exit- ing Idle Mode software must wait the T PLL_LOCK to ensure that the PLL is locked into its appropriate frequency and in phase.

PRODUCT SPECIFICATION FMS7401/7401L REV. 1.0.2 6/23/04 15 1. Initially, the PLLEN bit of the PSCALE register must be set in order to enable the PLL circuit. 2. If the PLL outputs are to be used to clock any of the device circuits, FMODE and/or FSEL of the PSCALE register must be set after the appropriate TPLL_LOCK wait time. 3. Prior to entering Idle Mode, software must clear both FMODE and FSEL (the timer must be disabled in order to clear either bit) keeping the PLLEN bit 1. 4. Using a separate instruction (e.g. RBIT PLLEN, PSCALE) disable the PLL by clearing the PLLEN bit. 5. Software may then instruct the device to enter Idle Mode. 6. If all disabled circuits must be re-enabled after exiting from Idle Mode, repeat all initial steps enabling all circuits in t he appropriate order as well as waiting T PLL_LOCK. 1. Contact your local Fairchild Sales Representative for FMS7401 availability. 2. The MIW and Timer 0 Circuits are described later in the datasheet. 3. Refer to the Electrical Characteristics section of the datasheet for details. 4. Refer to the Clock Circuit’s PLL section of the datasheet for details. 5. The FSEL bit in the PSCALE register must be set.

FMS7401/7401L PRODUCT SPECIFICATION 16 REV. 1.0.2 6/23/04 The Analog-to-Digital Converter (ADC) Circuit extends the features of the FMS7401/7401L by offering a 5-channel 8-bit ADC. The ADC may be programmed to convert voltages on any of the eight inputs of the analog mux, where five are multi- function input channels (ACH1-ACH5) and three are used for system calibration. The integrated ADC function offers a single cost-effective solution for applications requiring voltage, current and temperature sensing. The multifunction input channels may be configured to perform standard conversions on any of the analog input pins (G4/AIN0, G3/AIN1, G2/AIN2, G3/AIN3 or G7/AIN4). Three of the multifunction input channels may be programmed to perform ADC conversions through the internal Autozero Amplifier, Uncommitted Amplifier, and Current Source Generator for special control system and battery manage- ment applications (see Figure 6 The ADC Circuit’s eight analog inputs are software selectable where their analog input voltage is converted with respect to the internal ADC reference voltage (VAREF). VAREF may be programmed to use the internal bandgap reference voltage (VREF) or Vcc as its source. By default, the ADC circuit’s VAREF is configured to use the internal VREF as its source.1 The ADC performs conversions of 8-bit resolution with accuracy as defined in the Electrical Characteristics section of the datasheet. For a standard ADC conversion, the ADC circuit converts the analog input voltage in a total of 13 conversion clock cycles, and a total of 20 conversion clock cycles when performing an autozero ADC conversion. To yield a better ADC conver- sion accuracy, the ADC circuit may configure the ADC clock (F ADCLK) to a slower frequency, lengthening the total conversion time while improving its accuracy. As part of the total conversion time, the ADC circuit completes a sample and hold phase to measure fast changing analog signals before converting the voltage. An ADC conversion can be initiated by a software com- mand or automatically (using the gated auto-sampling mode) by the active (on) edge transition of the ADSTROBE PWM Timer 1 output. 2 If enabled, the ADC circuit offers the use of its microcontroller hardware interrupt (ADCI) triggered after each completed ADC conversion so that the microcontroller core is freed to perform other tasks.

4.1 ADC Circuit Configuration

Software must access the three memory mapped ADC registers to configure and control the ADC circuit.3 The ADC Control 1 (ADCNTRL1) register is used to select the analog input channel and ADC reference voltage (VAREF) for the conversion. In addition, it is used to initiate a conversion through software, monitor the ADC pending flag, and enable the ADC circuit’s microcontroller hardware interrupt (ADCI). The ADC Control 2 (ADCNTRL2) register is used to enable the internal Autozero Amplifier, Uncommitted Amplifier, Current Source Generator, and/or ADC Auto-sampling Mode. The ADCNTRL2 register is also used to divide the ADC F ADCLK clock to improve the conversion accuracy. Lastly, the ADC Data (ADATA) register is used by software to read the final converted 8-bit digital value. ADATA is a read only register and is updated automatically at the end of each ADC conversion.

Figure 6. ADC Block Diagram4

4.1.1 ADCNTRL1 Register

access to all bits of the register. the next converted value is latched in ADATA where the APND flag is set to 1.

FMS7401/7401L PRODUCT SPECIFICATION 18 REV. 1.0.2 6/23/04 Bit 6 of the ADCNTRL1 register is the ADC’s microcontroller hardware interrupt enabled (AINTEN) bit. If set, hardware interrupts (ADCI) are enabled and triggered by the APND pending flag.5 As long as the ADC pending flag is set, the hardware interrupt will continue to execute software’s ADC interrupt service routine until the pending flag is cleared.6 Bit 5 of the ADCNTRL1 register is the ADC Conversion Start/Busy (ASTART) bit. Software must set the ASTART bit to ini- tiate an ADC conversion when the ENDAS bit of the ADCNTRL2 register is set to 0. The ASTART bit will remain high as long as an ADC conversion is in progress (whether software or the ADSTROBE signal triggered the conversion). If software attempts to clear the ASTART bit while a conversion is in progress, the write command is ignored and the ASTART bit remains high until the conversion cycle completes. Software should monitor ASTART to determine when the conversion has completed instead of the APND bit. The APND bit may be triggered before the ASTART is automatically cleared. The ADC conversion completion delay may occur when the F ICLK clock is slower than an ADC conversion clock cycle. Bit 4 of the ADCNTRL1 register is the ADC V oltage Reference Selection (REFSEL) bit. If REFSEL=0, the ADC Reference Voltage (VAREF) becomes sourced by the internal bandgap voltage reference (VREF). If REFSEL=1, the ADC Reference V oltage (VAREF) becomes sourced by Vcc. If the ADC circuit is performing a conversion, software must avoid writing to the REFSEL bit. Bits 3-0 of the ADCNTRL1 register are the Analog Channel Selection (ACHSEL[3:0]) bits selecting one of the eight analog input channels to convert its voltage (see Table 6). Software may write to the ACHSEL bits at any time; however, the actual ACHSEL selection signals will not change while an ADC conversion is in progress. If a read command is issued while a con- version is in progress, the current value of the ACHSEL bits may not necessarily reflect the actual state of the ACHSEL selec- tion signals. The last value of the ACHSEL bits written by software at the time of the ADC conversion trigger, dictates the state of the ACHSEL selection signals for the triggered ADC conversion cycle. The SBIT or RBIT instructions may be used to either set or clear one of the ADCNTRL1 register bits, like the AINTEN bit. The SBIT and RBIT instructions both take two instruction clock cycles to complete their execution. In the first cycle, all regis- ter bits are automatically read to obtain their most current value. In the second cycle, the bit to be set/cleared is given its new value and all bits are then re-written to the register. Using the SBIT/RBIT instruction to set/clear an enable bit with a pending flag in the same register may cause a potential hazard. Software may inadvertently clear a recently triggered pending flag if the trigger happened during the second phase of the SBIT/RBIT instruction execution. To avoid this condition, the LD instruction must be used to set or clear the interrupt enable bit. The ADC circuit is designed such that software may not trigger a pending flag by writing a 1 to the APND bit, it may only be cleared. The action of writing a 1 to the APND register bit holds its current bit value. The action of writing a 0 to the APND register bit clears the bit value. Therefore, the “LD T1CNTRL, #0E0H” instruction will set the ASTART and AINTEN bits without clearing APND.

Table 5. ADCNTRL1 Register Bit Definitions Table 6. Analog Input Channel Selection (ACHSEL[3:0]) Bit Definitions

4.1.2 ADCNTRL2 Register

configure circuits directly related to the ADC circuit while the others are not related. ures the reference clock of the PLL and Programmable Comparator circuit to be sourced either by FRCLK1 or FRCLK1/2 clock. Refer to the Clock Circuit section of the datasheet for additional details. Comparator circuit, the selected analog input port pin must be configured as a tri-state input bypassing the I/O circuitry. Refer to the Programmable Comparator Circuit section of the datasheet for addition details. APND (0) ADC’s pending flag is cleared. (1) ADC’s pending flag is triggered. AINTEN (0) Disables ADC hardware interrupts. (1) Enables ADC hardware interrupts. ASTART (0) ADC conversion is not in progress. (1) Start an ADC conversion / ADC conversion in progress. ACHSEL[3:0] Analog Input Channel Selection Bits. Refer to Table 6 for details. ACHSEL[3] ACHSEL[2] ACHSEL[1] ACHSEL[0] Analog Channel I/O Equiv.

FMS7401/7401L PRODUCT SPECIFICATION 20 REV. 1.0.2 6/23/04 options must be prepared prior to setting the ENDAS bit. Refer to the following ADC Gated Auto-sampling Mode section for additional details. The ADSTROBE signal is generated by the PWM Timer 1 circuit and is configured using its T1CMPB and T1RA registers. Refer to the PWM Timer 1 Circuit section of the datasheet for details regarding its operation. If ENDAS=0, the ADC circuit is configured to accept only ADC start commands issued by software when setting the ASTART bit of the ADCNTRL1 register to 1. Refer to the following ADC Con version Modes section for additional details. Bits 3 and 2 (ASPEED[1:0]) of the ADCNTRL2 register selects the divide factor (1, 2, 4, or 8) to slow the FADCLK clock extending the ADC conversion cycle time. In most cases, the FADCLK clock division is performed to improve the ADC conversion accuracy. Refer to the following ADC Conversion Clock Configuration section for addition details. Bit 1 of the ADCNTRL2 register is the Current Source Generator Enable (ENIS) bit. If ENIS=0, the Current Source Generator circuit is disabled and its G3/AIN1 pin may be used as a normal I/O port or as a standard ADC conversion input through the analog ACH2 channel. If ENIS=1, the Current Source Generator circuit is enabled and its pin connection must be configured as a tri-state input bypassing the I/O circuitry.

9 If the ADC circuit is performing a conversion on the analog ACH2 input when

driven by the Current Source Generator, software must avoid clearing the ENIS bit. Refer to the following Current Source Generator section for additional details. Bit 0 (GAIN) of the ADCNTRL2 register is the autozero amplifier enable bit. If GAIN=0, the autozero amplifier with its gain 16 circuitry is disabled where its G4/AIN0 pin connections may be used as a normal I/O port. The G4/AIN0 pin may still be used as a standard ADC conversion input through the analog ACH1 channel. If GAIN =1, the autozero amplifier with its gain 16 circuitry is enabled and its G4/AIN0 pin connection must be configured as a tri-state input where G4/AIN0 is the non- inverting and SR_GND is the inverting input of the amplifier.

9 Software may write to the GAIN bit at any time; however, the

actual GAIN enable signal will not change while an ADC conversion is in progress. If a read command is issued while a con- version is in progress, the current value of the GAIN bit may not necessarily reflect the actual state of the GAIN enable signal. The last value of the GAIN bit written by software at the time of the ADC conversion trigger, dictates the state of the GAIN enable signal for the triggered ADC conversion cycle. Refer to the following Autozero Amplifier section for additional details.

Table 7. ADCNTRL2 Register Bit Definitions

4.2 ADC Conversion Modes

Auto-sampling Mode section for details. improve the ADC conversion accuracy. Circuit section of the datasheet for details. COMPSEL (0) G4 is connected to the Programmable Comparator’s non-inverting input. (1) G2 is connected to the Programmable Comparator’s non-inverting input. ENAMP (0) Disables the Uncommitted Amplifier (G6 and G7 are normal I/Os). amplifier output (AOUT) is also the ACH5 input to the ADC’s analog mux. bit of the ADCNTRL1 register. ENIS (0) Disable Current Source Generator (G3 is a normal I/O). (1) Enable Current Source Generator where G3/AIN1 sources the ISRC. GAIN (0) Disables the Autozero Amplifier (G4 is a normal I/O).

FMS7401/7401L PRODUCT SPECIFICATION 22 REV. 1.0.2 6/23/04 this information because the APND bit may be triggered before the ASTART is automatically cleared. The ADC conversion completion delay may occur when the FICLK clock is slower than an ADC conversion clock cycle.

4.2.1 Analog Input Voltage and its 8-bit Digital Result

The relationship between the 8-bit digital value stored in the ADATA register and the analog input voltage is as follows:

• V ADC is the 8-bit digital result of an ADC conversion.
• V ACH(x) is the analog voltage applied to the selected input channel.

4.2.2 ADC Gated Auto-sampling Mode

The ADC circuit may be configured in Gated Auto-sampling Mode by setting the ENDAS bit of the ADCNTRL2 register. When in Auto-sampling Mode, all ADC conversions are automatically triggered by the active (on) edge transition of the PWM Timer 1’s ADSTROBE output signal.

2 If the period of the PWM ADSTROBE signal is less than the total ADC conversion

time, any triggers issued while a conversion is in progress (ASTART=1) are ignored. Once the trigger is detected, the ASTART bit of the ADCNTRL1 register is set symbolizing that a conversion is in progress. The initial conversion phase, the sample and hold or autozero (if GAIN=1), begins after a 1µS cycle delay.

7 Once all eight digital bits are determined and stored in the

ADATA register, the APND flag is set to trigger a hardware interrupt (if enabled) flagging software that the ADATA register has been updated with the ADC conversion results. Once all phases of the ADC conversion cycle completes, the ASTART bit is then automatically cleared by the ADC circuit. Since software cannot change the ADC circuit configuration while an ADC con- version is in progress, the ASTART bit must be monitored to determine when the conversion cycle completes. Software cannot rely on the APND bit for this information because the APND bit may be triggered before the ASTART is automatically cleared. The ADC conversion completion delay may occur when the F ICLK clock is slower than an ADC conversion clock cycle.

4.2.3 ADC Conversion Clock Configuration

The ADC conversion clock (FADCLK) is sourced either by the device’s main system instruction clock (FICLK) or the PWM Timer 1’s clock (FT1CLK) depending on the ADC circuit’s operating mode. If the standard ADC conversion mode is selected, the ADC circuit is automatically configured to source the FADCLK clock by the FICLK clock. If the ADC Conversion Auto-sampling Mode is selected, the ADC circuit is automatically configured to source the FADCLK clock by the FT1CLK clock to synchronize the ADC conversions with the active (on) edge of the PWM Timer 1 ADSTROBE output signal.2 When in standard ADC conversion mode, the ASPEED[1:0] bits of the ADCNTRL2 register may be used to slow the total con- version time improving the ADC conversion accuracy. However, if the F ICLK clock is sourced by the PLL’s F(FS=0) output (when FMODE=1) the FADCLK will clock eight times faster than the proper conversion rate (1µS cycle time). The FADCLK clock must then be divided by setting the ASPEED[1:0]=3 divide factor to yield a FADCLK/8 conversion clock cycle. Otherwise, software may temporarily clear FMODE returning the conversion cycle to its proper frequency and free the ASPEED bits to be used to improve the conversion accuracy. In addition, if the internal oscillator is trimmed to its upper F OSC frequency and it is sourcing the FICLK clock, the ASPEED[1:0]=1 divided factor must be selected to yield a FADCLK/2 conversion clock cycle.8 A greater divide factor may still be selected by setting the ASPEED[1:0]>1. When in ADC Conversion Auto-sampling Mode, the ADC circuit automatically configures the FADCLK clock to be sourced by the FT1CLK clock so that the ADC conversions may be synchronized with the active (on) edge of the ADSTROBE signal. How- ever, the FT1CLK clock is first sent into a special divide circuit which evaluates its configuration to determine the divide factor needed to yield the proper FADCLK conversion rate (1µS cycle time). The FMODE, FSEL, and FS bits of the PSCALE register are evaluated so that the divide circuit applies the appropriate divide factor to the FT1CLK clock (the PS bits do not apply). The ASPEED[1:0] bits of the ADCNTRL2 register may be used to slow the total conversion time improving the ADC conversion VADC VACH x() VAREF

PRODUCT SPECIFICATION FMS7401/7401L REV. 1.0.2 6/23/04 23 accuracy. However, if the internal oscillator is trimmed to its upper FOSC frequency while FMODE and FSEL are zero, the ASPEED[1:0]=1 divided factor must be selected to yield a FADCLK/2 conversion clock cycle.8 A greater divide factor may still be selected by setting the ASPEED[1:0]>1.

4.3 Autozero Amplifier

The GAIN bit of the ADCNTRL2 register enables the Autozero Amplifier circuit. To perform a proper ADC conversion using the autozero amplifier, software must configure its non-inverting input (G4/AIN0) as a tri-state input bypassing the I/O circuitry. The autozero amplifier has a gain of 16, but is not defined as a true differential amplifier because the inverting SR_GND input must be connected as close to ground as possible (e.g. to act as a Kelvin connection) to reduce noise and improve the precision of the measurement. To perform an ADC conversion through the autozero amplifier, the ACH1 input channel of the analog mux must be selected. The autozero ADC conversion is divided in three phases lasting a total of 20 conversion clock cycles. In the first phase, occu- pying the first six conversion cycles, it calculates the offset voltage of the amplifier. The second phase, occupying the next five cycles, adds or subtracts the offset voltage to the amplified input voltage which now has a gain of 16. The final phase, occupy- ing the last nine cycles, converts the autozero input voltage to an 8-bit digital value and stores it in the ADATA register for easy access by software.

4.4 Uncommitted Amplifier

The Uncommitted Amplifier Enable (ENAMP) bit of the ADCNTRL2 register enables the Uncommitted Amplifier (AMP) circuit whose inverting input is connected to the G6/-A IN and output to the G7/AOUT port pins. Before enabling the AMP circuit, software must configure both the G6/-AIN and G7/AOUT pins as tri-state input ports bypassing all I/O circuitry. The AMP circuit may be used in any control or battery management applications. In control applications, the AMP circuit is used as the error amplifier in a hardware closed loop whose input connections are part of the external compensation loop circuit. The output of the amplifier (AOUT) is internally fed to the Programmable Comparator circuit to control the PWM T1HS1 and T1HS2 inputs of the control plant block. An ADC conversion may be triggered to monitor A OUT by selecting the ACH5 input channel of the analog mux. The AMP circuit may be configured as a general uncommitted amplifier whose non-inverting input is connected to VREF. Therefore, the AMP circuit may only amplify differences with respect to VREF. An ADC conversion may be triggered to con- vert the voltage at AOUT by selecting the ACH5 input channel of the analog mux. In battery management applications, the AMP circuit may be used to improve the resolution of the battery voltage measurement by adding a gain through the feedback loop. Voltage variation at a typical point will be amplified with a gain for better resolution, for example, to sense the Negative Delta V (NDV) to determine the end of change for a NiCD or NiMH battery.

4.5 Current Source Generator

The Current Source Enable (ENIS) bit of the ADCNTRL2 register enables the Current Source Generator (ISOURCE) circuit connected to the G3/AIN1 pin. Before enabling the ISOURCE circuit, software must configure the G3/AIN1 port as a tri-state input bypassing all I/O circuitry.

9 Once the ENIS bit is set, the ISOURCE circuit begins to generate ISRC of current typically

used to interface to an opto-coupler output.1 Figure 7 provides an example of a typical ISOURCE application where the voltage developed at the G3/AIN1 input can be converted by the ADC circuit if the ACH2 analog input channel is selected. The ISOURCE and ADC circuit combination may also be used to measure Capacitive Sensors or the resistance of a thermistor (NTC/PTC) to indirectly measure the temperature.

Figure 7. Current Generator Interface

1. Refer to the Electrical Characteristics section of the datasheet for details.
2. Refer to the PWM Timer 1 Circuit section of the datasheet for details regarding the ADSTROBE signal configuration.
3. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
4. On the FMS7401L 8-pin device, the SR_GND is internally bonded to the GND pin.
5. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the 8-Bit

Microcontroller Core section of the datasheet for details.

1. The ADC hardware interrupt will be executed in the defined priority order. Refer to the 8-Bit Microcontroller Core section of the datasheet for details.
2. Assuming the internal oscillator frequency is FOSC=2MHz as specified in the Electrical Characteristics section of the datasheet.
3. The upper FOSC frequency (4MHz) is not a standard feature offered on the FMS7401/7401L devices but is available upon request.
4. Refer to the I/O Ports section of the datasheet for details.

selectable by the COMPSEL bit of the ADCNTRL2 register.

1 If COMPSEL=0, the non-inverting input of the Programmable

as a tri-state input bypassing the I/O circuitry.

2 The inverting input of the comparator is controlled by the V oltage Loop

the comparator’s inverting input (see Figure 9). (DDELAY) register. Upon a system reset, the Programmable Comparator is disabled and the digital delay filter is enabled. instruction clock cycles before reading the COUT bit to ensure that the internal circuit has stabilized. Table 8. Programmable Comparator (COMP) Control Register Bit Definitions

5.1 Programmable Comparator’s Voltage Threshold Levels (VLOOP=0)

Delay Filter with PWMOFF Output section for addition details. circuit, the selected analog input port pin must be configured as a tri-state input bypassing the I/O circuitry. CL[5:0] Programmable Comparator Voltage Reference Level bits. Refer to Table 9 and Table 10 for details. VLOOP (0) Configures the inverting input of the analog comparator as one of the 63 programmable voltage levels (V THL, VTHU). connected to the inverting input. COUT (0) G2/AIN2 or G4/AIN0 non-inverting input is less than inverting input configured by VLOOP. (1) G2/AIN2 or G4/AIN0 non-inverting input is greater than inverting input configured by VLOOP.

able 9 and Table 10 for a detailed list of voltages. circuit is enabled and the COUT signal generated by the comparison of the two inputs. cannot cause a microcontroller hardware interrupt or perform any other action. Figure 8. Programmable Comparator Block Diagram (VLOOP = 0)

Table 9. Programmable Comparator Lower Voltage Reference VTHL (Levels 1 – 31)

Table 10. Programmable Comparator Upper Voltage Reference VTHU (Levels 32 – 63)

5.2 Hardware Voltage and Current Loop Control (VLOOP=1)

following Digital Delay Filter with PWMOFF Output section for addition details.

circuit, the selected analog input port pin must be configured as a tri-state input bypassing the I/O circuitry. circuit is enabled and the COUT signal generated by the comparison of the two inputs. any microcontroller hardware interrupt or any other actions. Figure 9. Programmable Comparator Block Diagram (VLOOP = 1)

FMS7401/7401L PRODUCT SPECIFICATION 30 REV. 1.0.2 6/23/04

5.3 Digital Delay Filter with PWMOFF Output

The Programmable Comparator’s output (COUT) is fed into the digital delay filter with a programmable delay time. The COUT signal toggles from 0 to 1 when the external input (G4/AIN0 or G2/AIN2) voltage is higher than the programmed voltage threshold or Uncommitted Amplifier output (A OUT), depending on the state of VLOOP. The COUT rising edge transition triggers the programmable digital delay counter to begin incrementing. With each digital delay count, its value is compared against the value stored in the DD[3:0] bits of the Digital Delay (DDELAY) control register. If C OUT remains high when the digital delay count equaling DD[3:0] completes, the PWMOFF signal transitions from 0 to 1. This rising edge transition of the PWMOFF signal is then used to either disable the PWM Timer 1 circuit completely or the current PWM cycle forcing the PWM output signals to their resting (off) state. The PWMOFF output signal may also be programmed as an input of the G6 port MIW circuit. Interrupts may be triggered if the G6 port MIW circuit is enabled and configured to trigger its microcontroller hardware interrupt (EDGEI). Refer to the Multi-input Wakeup Circuit section of the datasheet regarding for configuration details. Bit 7 of the DDELAY register is the Programmable Comparator circuit enable (COMPEN) bit. If COMPEN=0, the Program- mable Comparator circuit is disabled and the COUT signal is low. If COMPEN=1, the Programmable Comparator circuit is enabled and the COUT signal is generated by the comparison of the two inputs. Bit 6 (PWMINT) of the DDELAY register, if set to 1, selects the PWMOFF signal in place of its G6 input to the MIW circuit. Software must then enable the MIW PWMOFF/G6 circuit by setting the WKEN[6] bit. The WKEDG[6] bit must also be cleared to select the rising edge transitions on the PWMOFF signal as its WKPND[6] bit trigger. Software may monitor the WKPND[6] flag or enable the MIW hardware interrupt (EDGEI) to help detect when the PWMOFF signal is triggered. Bit 5 (EPWM) of the DDELAY register is the digital delay filter and PWMOFF signal enable bit. The EPWM bit is active low so that on power-up (after a system reset) the digital delay filter circuit is automatically enabled once the Programmable Comparator circuit is enabled. If the Programmable Comparator and PWM Timer 1 circuits are enabled, since the filter is defaulted enabled, the PWMOFF signal may disable the PWM Timer 1 upon a comparator transition. If the digital delay filter and PWMOFF circuit is not needed, software must set the EPWM bit to 1 disabling the filter before enabling the Programma- ble Comparator to prevent unwanted disables of the PWM Timer 1 circuit or its outputs. Bit 4 (OFFMODE) of the DDELAY register determines how the PWMOFF signal affects the PWM Timer 1 circuit. If OFF- MODE=0 and the Timer 1 circuit is configured in an enabled PWM Mode, Timer 1 is automatically disabled forcing the PWM T1HS1 and T1HS2 output signals to their resting (off) states with the rising edge of the PWMOFF signal. The T1C0 bit of the T1CNTRL2 register is cleared, reinitializing the 12-bit TMR1 counter to 0x000. Software must re-enable the Timer 1 circuit to reactivate the PWM output signals. If OFFMODE=1 and Timer 1 is configured in PWM Mode, the T1HS1 and T1HS2 output signals are forced to their resting (off) state until the current PWM cycle completes. Once the PWM cycle completes, the PWMOFF signal releases the T1HS1 and T1HS2 output signals and they resume with their normal operation even if the C OUT signal remains active (1). The next PWMOFF trigger will not occur until the next rising edge of COUT. Bits 3-0 (DD[3:0]) of the DDELAY register determine how long to delay the trigger of the PWMOFF signal once the rising edge of COUT has been detected. Once the digital delay counter is triggered, the delay count is compared against the value stored in the DD[3:0] bits. Once the delay counter completes its DD[3:0] count, if COUT remains high, the PWMOFF signal is triggered. The digital delay counters increment at the device reference clock rate (FRCLK2).4

Table 11. Digital Delay (DDELAY) Register Bit Definitions Figure 10. Digital Delay Timing

1. Refer to the ADC Circuit section of the datasheet for additional details.
2. Refer to the I/O Ports section of the datasheet for details.
3. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the 8-Bit

Microcontroller Core section of the datasheet for details.

1. Refer to the Clock Circuit section of the datasheet for details regarding the FRCLK2 clock.

COMPEN (0) Disable the Programmable Comparator circuit. (1) Enable the Programmable Comparator circuit. PWMINT (0) The input of the G6 MIW circuit network is the G6/-A IN device pin. (1) The input of the G6 MIW circuit network is the PWMOFF output signal (not the G6/-AIN device pin). EPWM (0) Enables the Digital Delay Filter circuit. The PWMOFF output is triggered by C OUT after the programmed delay (TDDELAY). (1) Disables the Digital Delay Filter circuit and the PWMOFF output signal. OFFMODE (0) PWM outputs switched off and Timer 1 stops after a comparator detection with delay. (1) PWM outputs switched off for the current PWM cycle only.

FMS7401/7401L PRODUCT SPECIFICATION 32 REV. 1.0.2 6/23/04 The Pulse Width Modulation (PWM) Timer 1 circuit, a programmable 12-bit PWM timer with a 3-bit prescaler can be config- ured to operate in both PWM and Input Capture Modes. In PWM Mode, the Timer 1 circuit may be configured to generate pulses of a specified duty cycle and period on the T1HS1 (G0), T1HS2 (G5), and/or ADSTROBE (G1) timer output ports. On the other hand, in Input Capture Mode, the Timer 1 circuit may be configured to capture and store the current timer value at the time of a trigger defined by the rising or falling edge of the T1HS2 (G5) input port. In addition, the T1HS1 and ADSTROBE PWM outputs may be generated as in the PWM Mode. The Timer 1 circuit backbone is a 12-bit programmable up-counter (TMR1) that is accessible by software, with read-only access, through the 4-bit TMR1HI and 8-bit TMR1LO memory mapped registers where TMR1={TMR1HI, TMR1LO}.

1 Upon

a system reset or once entering a new Timer 1 mode of operation, the 12-bit TMR1 counter is initialized to 0x000. Once a selected Timer 1 mode is enabled, the TMR1 counter will begin incrementing by the FT1CLK clock with the programmed divide factor defined by a 3-bit prescaler. Once the TMR1 overflows, TMR1 is reinitialized to 0x000 and resumes incrementing until software disables the mode. In PWM Mode, the TMR1 overflow value may be programmed by software where, in Input Capture Mode, the TMR1 will overflow once the 0xFFF count completes. The Timer 1 circuit may be programmed to generate microcontroller hardware interrupts with every TMR1 overflow and capture. The Timer 1 F T1CLK clock may be programmed to operate from high to low frequencies with the use of the programmable digital clock multiplier (PLL) and internal oscillator in order to provide the maximum flexibility for various PWM applica- tions.

6.1 PWM Timer 1 Configuration Registers

Software must access the six memory mapped PWM Timer 1 registers to configure and control the Timer 1 circuit.1 The 8-bit Prescale (PSCALE) register is used to configure the entire FMS7401/7401L clock structure including the Timer 1’s FT1CLK. The 12-bit Timer 1 Compare A (T1CMPA), Timer 1 Compare B (T1CMPB), and Timer 1 Reload (T1RA) registers are used to define the PWM output signal’s duty cycle and period. The 5-bit Dead Time (DTIME) register is used to define the time delay DT) between the PWM T1HS1 and T1HS2 edge transitions while in PWM Mode. The Timer 1 Control (T1CNTRL) register is used to select Timer 1’s operating mode, enable its PWM output signals, and control its hardware interrupt (TMRI1).

6.1.1 PSCALE Register and Timer 1 Clock Configuration

Although the PSCALE register is part of the PWM Timer 1 circuit, its register bits configure the clock structure for the entire FMS7401/7401L along with the Timer 1 clock (FT1CLK). Refer to the Clock Circuit section of the datasheet for details regard- ing the device’s clock structure. The FT1CLK source may be supplied by either the programmable FPWMCLK PLL output or the main instruction (FICLK) clock. Once the FT1CLK source is selected, it may not be changed while the Timer 1 circuit is in PWM mode and running or in Input Capture Mode (run mode). Upon a system reset, the PSCALE register is automatically initialized to 0x00. Bit 7 of the PSCALE register is the PLL circuit enable (PLLEN) bit. Before using any of the PLL outputs, software must enable the PLL circuit and wait the T PLL_LOCK to ensure that the PLL is locked into its appropriate frequency and in phase. The PLLEN bit may not be changed while the Timer 1 circuit is in run mode. Any attempts to write to PLLEN under this condition will be ignored and its value will remain unchanged. Bits 6 and 5 (FS[1:0]) of the PSCALE register are the bits used to select between the different output frequencies available to the PLL’s F PWMCLK output signal. FS selects between the four available PLL divide factors (divide-by-1/2/4/8) selecting an out- put frequency of 8/16/32/64MHz (see Table 13). The FS bits may be changed by software at any time; however, if the Timer 1 circuit is in run mode, the FS value will not change the FPWMCLK output frequency until after the TMR1 counter overflows end- ing the current PWM cycle. The last FS value at the TMR1 counter overflow will dictate the divide factor of the FPWMCLK out- put for the next PWM cycle. When reading FS, the value reported will be the last value written by software and may not necessarily reflect the divide factor for the current PWM cycle.

slow or high frequency options, ultimately selecting the FT1CLK to be sourced either by the FICLK or FPWMCLK (see Table 13). will be ignored and its value will remain unchanged. normal instruction execution in order to speed-up a particular action. necessarily reflect the divide factor for the current PWM cycle. Table 12. Prescale (PSCALE) Register Bit Definitions Table 13. PLL Divide Factor Selection Bits and the FT1CLK Resolution (FOSC=2 MHz) PLLEN (0) Disables the PLL circuit. (1) Enables the PLL circuit. FS[1:0] PLL Divide Factor Selection Bits. Refer to Table 13 for details. FSEL (0) Selects F ICLK as Timer 1’s clock (FT1CLK) source. (1) Selects FPWMCLK PLL output as Timer 1’s clock (FT1CLK) source. FMODE (0) Selects F CLK divided-by-2 output as the main system instruction clock (FICLK) source. (1) Selects F(FS=0) PLL output as the main system instruction clock (FICLK) source. PS[2:0] Timer 1 Prescale Selection Bits. Refer to Table 13 for details.

Table 14. Timer 1 Prescale Selection (PS) Bits

6.1.2 PWM Cycle Configuration Registers

value written by software and may not necessarily reflect the output signal’s attributes for the current PWM cycle. software through the 4-bit T1RAHI and 8-bit T1RALO memory mapped registers where T1RA= {T1RAHI, T1RALO}. value of the TMR1 count at the time of the trigger defined by the rising or falling edge of the T1HS2 input. registers where T1CMPA={T1CMPAHI, T1CMPALO}.

1 In PWM Mode, the TMR1 counter is compared against T1CMPA

to the total T1RA plus TDT times. ters where T1CMPB={T1CMPBHI, T1CMPBLO}.

1 The TMR1 counter is compared against T1CMPB to determine when the

(TMR1=T1CMPB) an Analog-to-Digital Converter (ADC) conversion may be initiated.

4 Software must ensure that the total

T1CMPB plus TDT time is not greater than or equal to the total T1RA plus TDT times. passed, the T1HS1 signal will then transition ending its active (on) state.

Table 15. Dead Time (DTIME) Register Bit Definitions

6.1.3 Timer 1 Control Register

able 16 and Table 17 for additional details regarding the T1CNTRL register bits. though T1C0=1. Software must clear T1C0 before re-enabling the Timer 1 circuit in any of the two operating modes. may not necessarily reflect the circuit’s attribute for the current PWM cycle. attribute for the current PWM cycle.

FMS7401/7401L PRODUCT SPECIFICATION 36 REV. 1.0.2 6/23/04 pletes, will dictate the device’s I/O attribute for the next PWM cycle. When reading the T1BOUT, the value reported will be the last value written by software and may not necessarily reflect the device’s I/O attribute for the current PWM cycle. Bit 4 (T1C0) of the T1CNTRL register has two functions depending on Timer 1’s selected operating mode. In PWM Mode, when T1C0=1, the TMR1 circuit becomes enabled and begins to increment from its initial 0x000 state; otherwise, the TMR1 counter is stopped and reinitialized. Software may disable the Timer 1 circuit at any time; however, the TMR1 counter and PWM outputs will not be disabled until the current PWM cycle completes. Software should monitor the T1C0 bit to determine when the PWM cycle ends and Timer 1 circuit actually disabled. In Input Capture Mode, the T1C0 bit is one of the TMR1 overflow (a transition from 0xFFF to 0x000) pending flags used to trigger the Timer 1 Circuit’s hardware interrupt if the inter- rupt is enabled. In order for software to properly monitor the TMR1 overflows, the T1C0 bit must be cleared before the next TMR1 overflow. Bit 3 (T1PND) of the T1CNTRL register has two functions depending on Timer 1’s selected operating mode. In either operat- ing modes, the T1PND bit is one of the Timer 1 Circuit’s hardware interrupt pending flags if the interrupt is enabled. In PWM Mode, the T1PND bit is triggered by a TMR1 overflow (a transition from the T1RA count to 0x000). However, in Input Cap- ture Mode, the T1PND bit is triggered by the capture of the current TMR1 value by the rising or falling edge of the T1HS2 (G5) input port. In order for software to properly monitor the pending flag, the T1PND bit must be cleared before the next TMR1 overflow or capture. Bit 2 of the T1CNTRL register is the Timer 1’s microcontroller hardware interrupt enable (T1EN) bit. If set, hardware inter- rupts are enabled and trigger by the T1PND and/or T1C0 pending flags depending on Timer 1’s operating mode.

6 If in PWM

Mode, the hardware interrupt is triggered only by the T1PND bit. If in Input Capture Mode, the T1PND and T1C0 bits are log- ically-ORed together. As long as a Timer 1 pending flag is set, the hardware interrupt will continue to execute software’s Timer 1 interrupt service routine until the pending flag is cleared. The SBIT or RBIT instructions may be used to either set or clear one of the T1CNTRL register bits, like the T1EN bit. The SBIT and RBIT instructions both take two instruction clock cycles to complete their execution. In the first cycle, all register bits are automatically read to obtain their most current value. In the second cycle, the bit to be set/cleared is given its new value and all bits are then re-written to the register. Using the SBIT/RBIT instruction to set/clear an enable bit with a pending flag in the same register may cause a potential hazard. Software may inadvertently clear a recently triggered pending flag if the trigger happened during the second phase of the SBIT/RBIT instruction execution. To avoid this condition, the LD instruction must be used to set or clear the interrupt enable bits. The Timer 1 circuit is designed such that software may not trigger a pending flag by writing a 1 to the T1PND and T1C0 (if in Input Capture Mode) bits, they may only be cleared. The action of writing a 1 to a T1PND and T1C0 register bits holds the current bit values. The action of writing a 0 to the T1PND and T1C0 register bits clears the bit values. Therefore, if Timer 1 is configured for a rising edge triggered input capture mode with outputs enabled and software is to enable interrupts without interrupting the pending flags, the “LD T1CNTRL, #0BDH” instruction should be used. The T1EN bit will be set to 1 without clearing T1PND and/or T1C0.

Table 16. Timer 1 Control (T1CNTRL) Register Bit Definitions Table 17. Timer 1 Mode Configuration Bits

6.2 Pulse Width Modulation (PWM) Mode

section of the datasheet for details. A PWM cycle begins with the TMR1 counter incrementing from 0x000 until it matches the value stored in the T1RA register. T1C3 Timer 1 Mode Configuration Bit. Refer to Table 17 for details. T1C2 Timer 1 Mode Configuration Bit. Refer to Table 17 for details. T1C1 Timer 1 Mode Configuration Bit. Refer to Table 17 for details. (0) Stop the PWM Timer 1 circuit. (1) Start the PWM Timer 1 circuit. (0) Timer 1’s TMR1 overflow pending flag is cleared. (1) Timer 1’s TMR1 overflow pending flag is triggered. (0) Timer 1’s TMR1 overflow pending flag is cleared. (1) Timer 1’s TMR1 overflow pending flag is triggered. (0) Timer 1 capture pending flag is cleared. (1) Timer 1 capture pending flag is triggered. T1EN (0) Disables Timer 1 hardware interrupts. (1) Enables Timer 1 hardware interrupts. T1BOUT (0) Retain normal I/O function of the G1/AIN3 pin. (1) Enables Timer 1’s ADSTROBE output to be sent to the G1 output port.

FMS7401/7401L PRODUCT SPECIFICATION 38 REV. 1.0.2 6/23/04 The PWM Timer 1 can be programmed to toggle one or both PWM output signals (T1HS1 and T1HS2) to support a variety of output configurations (half bridge, full bridge,8 low side or high side driving). These outputs may be used to drive an external half-bridge driver and are enabled by programming the T1C1 and T1C2 bits in the T1CNTRL register (see Table 16). The T1HS1 (G0) and T1HS2 (G5) output signals may be configured with opposite phases and dead time controlled edges (see Figure 12 ). The phases of the output signals are configured by the bits of the PORTGD I/O configuration register.9 Upon device power-up, the T1HS1 and T1HS2 signals may be programmed to default as active high/low outputs by the default I/O configu- ration register bits in the non-volatile Initialization Register 4.

10 Both G0/T1HS1 and G5/T1HS2 pins will configure to their

programmed default state after TDIO2 from the system reset trigger (e.g. from a POR). The G0/T1HS1 and G5/T1HS2 pins may both be configured as outputs with common or opposite phases. If configured as outputs, the PORTGD[0] and PORTGD[5] bits configure the T1HS1 and T1HS2 signals as active high or low. If the PORTGD bit is 0, the output signal is active high, other- wise it is active low. The PORTGD[1] bit also configures the G1/ADSTROBE pin as an active high/low signal once configured as an output. The Initialization Register 4 bits only default the G0/T1HS1 and G5/T1HS2 pins not the G1/ADSTROBE pin. From factory, the G0/T1HS1, G5/T1HS2 and G1/ADSTROBE device pins are defaulted as tri-stated inputs. The pins must be configured by the Initialization Register 4 bits or by software directly through the PORTGC and PORTGD register as an output port before enabling the TMR1 counter and its outputs. The dead time counter of the Timer 1 circuit controls the dead time (T DT) delay between the T1HS1 and T1HS2 output edge transitions through the DT[4:0] bits of the DTIME register. The dead time counter delay is first triggered after the TMR1 counter equals to the T1CMPA value and the T1HS1 signal transitions from its resting (off) to its active (on) state. Once the programmed T DT completes, the T1HS2 signal then transitions from its resting (off) to its active (on) state. The dead time counter delay is triggered for a second time after the TMR1 counter equals to the T1RA value and the T1HS2 signal transitions from its active (on) to its resting (off) state. Once the programmed T DT completes, the T1HS1 signal then transitions from its active (on) to its resting (off) state ending the PWM cycle. The PWM cycle is considered complete once the TMR1 counter completes the T1RA count plus T DT even in the T1HS1 and T1HS2 outputs are disabled. The T1HS1 and T1HS2 PWM output signals may be programmed to be automatically disabled by the output of the digital filter (PWMOFF) in Programmable Comparator circuit. The output may be programmed to disable the Timer 1 circuit completely or disable only the current PWM cycle. Refer to the Programmable Comparator Circuit section of the datasheet for details. The Timer 1’s ADSTROBE output signal may be configured as the G1/ADSTROBE device output if the T1BOUT bit of the T1CNTRL register is set. The ADSTROBE signal, however, is always generated by the Timer 1 circuit. Initially, the ADSTROBE begins its PWM cycle at its resting (off) state and transitions to its active (on) state once the TMR1 counter com- pletes its count equal to the T1CMPB value. The active (on) edge transition of the ADSTROBE output may be programmed to automatically trigger an ADC conversion cycle if the ENDAS bit of the ADCNTRL2 register is set. Refer to the ADC Circuit section of the datasheet for details. The T1PND bit of the T1CNTRL register is set once the TMR1 counter completes the count equal to the T1RA value (over- flows). Software may use the T1PND bit to monitor the PWM cycles and/or trigger microcontroller hardware interrupts (TMRI1) if the T1EN bit of the T1CNTRL register is set. Software must clear the T1PND bit in order to detect a new overflow condition and/or trigger a new interrupt.

6.3 Input Capture Mode

circuit instead of an output as in PWM Mode. The G5/T1HS2 device pin should be configured by software as an input port. imum of three FT1CLK cycle TMR1 capture delay will occur with each edge transition on the G5/T1HS2 device pin. (transitions from 0xFFF to 0x000) the T1C0 pending bit on through T1CNTRL register is set. Width Modulation (PWM) Mode section of the datasheet for details. Figure 13. Timer 1’s Input Capture Mode Block Diagram

1. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
2. Refer to the Electrical Characteristics section of the datasheet.
3. The PLL’s (F(FS=0)) output is not affected by the FS[1:0] bit value of the PSCALE register and merely shares the FS[1:0]=00 divide factor.
4. Refer to the ADC Circuit section of the datasheet for additional details.
5. The three PS bits have no affect on the dead time, only the TMR1 counter.
6. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the 8-Bit Micro-

controller Core section of the datasheet for details.

1. The Timer 1 hardware interrupt will be executed in the defined priority order. Refer to the 8-Bit Microcontroller Core section of the datasheet for details.
2. The full bridge requires two additional output ports to complete the bridge configuration.

section of the datasheet for additional details. 10.Refer to the Device Memory section of the datasheet for details regarding the initialization registers.

instruction clock. The 12-bit counter is not memory mapped; therefore, software cannot read or write to the counter registers. Timer 0 Control (T0CNTRL) memory mapped register.

1 The T0PND flag is automatically set with each counter overflow

2 As long as a Timer 0 pending flag is set, the hardware interrupt will continue to execute software’s

will set both interrupt enable bits without clearing T0PND. Table 18. Timer 0 Control (T0CNTRL) Register Definitions

7.1 Idle Timer

overflow flag is triggered, the device wakes from Idle Mode and starts its instruction execution with the next clock cycle. Mode, thereby reducing the overall current consumption.

7.2 Watchdog Timer

ming mode by clearing the WDEN bit as long as the memory write protect (WDIS) feature is not enabled. quently or not frequently enough where the servicing of the Watchdog Timer is controlled completely by software. software should service the Watchdog Timer prior to entering Idle Mode to prevent false resets. issued within software’s main program code. Table 19. Watchdog Service Register (WDSVR) Definition

1. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
2. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the 8-Bit Micro-

controller Core section of the datasheet for details.

1. The Timer 0 hardware interrupt will be executed in the defined priority order. Refer to the 8-Bit Microcontroller Core section of the datasheet for details.
2. After a system reset, the T0CNTRL register is defaulted to 0x00.
3. Refer to the Power Saving Modes

section of the datasheet for Idle Mode wakeup conditions.

1. Refer to the Device Memory section of the datasheet for details regarding the Initialization Registers.
2. The FMS7401/7401L must be placed in a special programming mode in order to have full write and read access of all of the device memories. Refer to the In-circuit

Programming Specification section of the datasheet for details.

1. Refer to the Electrical Characteristics section of the datasheet for details.

devices are supplied by the Vcc pin (see Figure 15). Figure 14. PORTGD Logic Diagram Figure 15. Output Port Configurations

8.1 I/O Registers

For the FMS7401L device, VDD and VCC are internally connected.

ports have Schmitt triggers. may be defaulted to the different I/O configurations defined by the default I/O configuration bits of the Initialization Register 4. able 29 in the Device Memory section of the datasheet for details. Table 20. I/O Register Bit Assignments Table 21. I/O Configuration Options

1. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
2. Available only on the 14-pin package option.
3. The G0/T1HS1 and G5/T1HS2 pins on the FMS7401 have special high voltage outputs. Refer to Figure 15

00 High-impedance input (tri-state input)

01 Input with pull-up (weak one input)

10 Push-pull zero output

11 Push-pull one output

PRODUCT SPECIFICATION FMS7401/7401L REV. 1.0.2 6/23/04 45 The Multi-input Wakeup (MIW) circuit may be used to wake the device from either Halt or Idle Mode1 with an external event, generate flags for software monitoring and microcontroller hardware interrupts by any one or all I/O ports (G0–G7). The MIW circuit is configured using the Wakeup Enable (WKEN), Wakeup Edge (WKEDG), Wakeup Pending (WKPND) and T0CNTRL memory mapped registers.

2 The WKEN, WKEDG and WKPND are 8-bit registers where each bit corresponds to

an I/O port pin (see Table 21). All four registers are initialized to 0x00 upon a system reset. The PWMOFF output signal may also be programmed as an input of the G6 port MIW circuit. Interrupts may be triggered if the PWMOFF/G6 input MIW circuit is enabled and configured to trigger its microcontroller hardware interrupt (EDGEI). Bit 6 (PWMINT) of the DDELAY register, if set to 1, selects the PWMOFF signal in place of its G6 input to the MIW circuit. Software must then enable the MIW PWMOFF/G6 circuit by setting the WKEN[6] bit. The WKEDG[6] bit must also be cleared to select the rising edge transitions on the PWMOFF signal as its WKPND[6] bit trigger. Software may monitor the WKPND[6] flag or enable the MIW hardware interrupt (EDGEI) to help detect when the PWMOFF signal is triggered. Refer to the Programmable Comparator Circuit sections of the datasheet for addition details.

9.1 MIW Configuration Registers

The Wakeup Enable (WKEN) register individually enables an I/O port’s edge transition to trigger a wakeup/interrupt pending flag. If the WKEN register bit is 1, the corresponding I/O port’s MIW circuitry (defined by its bit number) is enabled; other- wise, the port circuitry remains disabled and the pending flag may not be triggered. The Wakeup Edge (WKEDG) register bits are used to program an enabled I/O port’s pending flag to be triggered from either a rising-/falling-edge transition. If the WKEDG register bit is 1, a falling-edge transition of the enabled I/O port will trigger the pending flag. If zero, a rising-edge transition of the enabled I/O port will trigger the pending flag. The MIW circuit shares a single hardware interrupt (EDGEI) among all pending flags and is enabled by the Wakeup Interrupt enable (WKINTEN) bit of the T0CNTRL register.

2 The WKINTEN bit enables hardware interrupts for the MIW circuit if set

to 1.3 The Wakeup Pending (WKPND) register contains the pending flags corresponding to each of the I/O port pins. If a WKPND register bit is 1, the programmed I/O port edge transition has triggered its pending flag. If zero, the flag is not pending and n o transition has occurred from the last pending reset. A pending flag may only be triggered by enabled I/O ports (if its WKEN register bit is 1). Once a pending flag is triggered, all flags are logically-ORed together to trigger a W AKEOUT if in Halt/Idle Mode and/or hardware interrupts (if enabled). If software is to re-enter Halt/Idle Mode, all pending flags must be cleared, oth- erwise the command is ignored. Since all MIW pending flags share a single hardware interrupt, software must take care with the handling of the pending flags when more than one pending flag is enabled. As long as a MIW pending flag is set, the hard- ware interrupt will continue to execute software’s MIW interrupt service routine with highest priority until all pending flags are cleared. Upon exiting Halt/Idle Mode or before leaving software’s MIW interrupt service routine, the RBIT instruction may be used to clear a particular pending flag. The RBIT instruction takes two instruction clock cycles to complete its execution. In the first cycle, all eight register bits are automatically read to obtain their most current value. In the second cycle, the bit to be cleared is given its new value and all bits are then re-written to the register. Using the RBIT instruction to clear an individual pending flag causes no potential hazards if only one wakeup I/O port is enabled. However, if more than one I/O port is enabled software may inadvertently clear a recently triggered pending flag if the trigger happened during the second phase of the RBIT instruc- tion execution. To avoid this condition, the LD instruction must be used to clear a set pending flag. The MIW circuit is designed such that software may not trigger a pending flag by writing a 1 to a WKPND register bit, it may only be cleared. The action of writing a 1 to a WKPND register bit holds the current bit value. The action of writing a 0 to a WKPND register bit clears the bit value. Therefore, the “LD WKPND, #0F7H” instruction will clear the WKPND[3] while all others bits remain the same.

wakeup I/O port must be configured as an input, otherwise the device will never exit the mode. Table 22. Multi-input Wakeup (MIW) Register Bit Assignments Figure 16. Multi-input Wakeup (MIW) Block Diagram6

1. Refer to the Power Saving Modes section of the datasheet for detail regarding Halt and Idle Mode.
2. Refer to Table 30 of the Device Memory section of the datasheet for the detailed memory map.
3. Hardware interrupts are not executed by the microcontroller core unless the Global Interrupt enable (G) flag of the Status register is set. Refer to the 8-Bit

Microcontroller Core section of the datasheet for details.

1. No other hardware interrupts will be executed, aside from the software interrupt instruction, until the MIW hardware interrupt is no longer executed. Refer to the

8-Bit Microcontroller Core section of the datasheet for details.

1. Available only on the 14-pin package option.
2. The PWMOFF and PWMINT signals are the outputs from the Programmable Comparator’s Digital Filter circuit. Refer to Programmable Comparator Circuit

of the datasheet for details.

addressed separately from instruction data. mann architecture and stored program concept.

10.1 Core Registers

Figure 17. Core Program Model

00 N HCZGR

FMS7401/7401L PRODUCT SPECIFICATION 48 REV. 1.0.2 6/23/04

10.1.1 Accumulator (A)

The Accumulator is a general-purpose 8-bit register that is used to hold data and results of arithmetic calculations or data manipulations.

10.1.2 X-Pointer (X)

The X-Pointer register allows for an 11-bit indexing value to be added to an 8-bit offset creating an effective address used for reading and writing among the memory space. This provides software with the flexibility of storing lookup tables in the code EEPROM memory space for the core’s accessibility during normal operation. The microcontroller core allows software to access the entire 11-bit X-Pointer register using the special X-pointer instructions e.g. LD X, #040H (see Table 24). Software may also access the register through any of the memory mapped instructions using the XHI (X[10:8]) and XLO (X[7:0]) variables located at address 0xBE and 0xBF (see Table 30). The X register is divided into two sections. The most significant bit (MSB) is write only and selects between the data (0x000 to 0x0FF) or program (0xC00 to 0xFFF) memory space. The 10 least significant bits (LSBs) represent the specific address location within the data or program memory space. For example: If X[10] = 0, the LD A, [#0,X] instruction will take the data at address X[9:0] from the data memory space (0x000 to 0x0FF) and load it into A. However, if X[10] = 1 the LD A, [#0,X] instruction will take the data at address X[9:0] from the program memory space (0xC00 to 0xFFF) and load it into A. The X register can also serve as a counter or temporary storage register. However, this is true only for the 10-LSBs since the MSB is dedicated for memory space selection.

10.1.3 Program Counter (PC)

The 10-bit Program Counter (PC) register contains the address of the next instruction to be executed. After a system reset, PC is initialized to 0xC00 and the microcontroller core begins executing the instruction program residing in the code EEPROM memory at the initialized PC value.

10.1.4 Stack Pointer (SP)

The microcontroller core has an automatic program stack with a 4-bit stack pointer. The stack can be initialized to any location between addresses 0x30-0x3F in SRAM. Normally, the stack pointer is initialized by one of the first instructions in an applica- tion program. After a reset, the stack pointer is defaulted to 0xF pointing to the top of the stack at address 0x3F. The stack is configured as a data structure which decrements from high to low memory. Each time a new address is pushed onto the stack, the microcontroller core decrements the stack pointer by two. Each time an address is pulled from the stack, the microcontroller core increments the stack pointer is by two. At any given time, the stack pointer points to the next free location in the stack. When a subroutine is called by a jump-to-subroutine (JSR) instruction, the instruction’s address is automatically pushed onto the stack with the least significant byte first. When the subroutine is finished, a return-from-subroutine (RET) instruction is executed. The RET instruction pulls the previously stacked return address and loads it into the program counter. Instruction execution then continues at the pulled return address.

10.1.5 Status Register (SR)

The 8-bit Status Register (SR) contains four condition code indicators (C, H, Z, and N), a global interrupt (G) mask bit, and the data EEPROM write ready (R) flag. The condition codes are automatically updated by most instructions (see T able 25). All sta- tus register bits except for the global interrupt mask are read only when using direct, indirect, or indexed instructions. The carry and half carry bits may be written by using their special inherent (SC, RC, LDC, RRC and RLC) instructions. Software cannot restore SR using the traditional microcontroller methods. Refer to the Interrupt Handling section for additional details.

SC, INVC, LDC and STC (store carry) instructions facilitate direct bit manipulation using the carry flag. The half carry flag indicates whether an overflow has taken place on the boundary between the two nibbles in the accumulator. manipulation of the half carry flag. flag. Otherwise, the negative flag is cleared. set when an interrupt becomes pending the core will be interrupted and execute the appropriate interrupt service routine. understanding of latency and of the arbitration mechanism. Table 23. Interrupt Priority Sequence

5 Software (INTR)

4 MIW (EDGEI)

3 Timer 0 (TMRI0)

2 PWM Timer 1 (TMRI1)

1 ADC (ADCI)

10.1.6 Interrupt Handling

was not enabled prior to the software interrupt the RET instruction must be used. Figure 18. Basic Interrupt Structure

PRODUCT SPECIFICATION FMS7401/7401L REV. 1.0.2 6/23/04 51

10.2 Addressing Modes

The microcontroller core has seven instruction addressing modes: inherent, immediate, direct, indirect, indexed, absolute jump and relative jump (see Table 24). Inherent The inherent addressing mode instructions either have no operand associated or the contents of the operand are already known to the microcontroller core. The microcontroller core then inherently knows how to execute the instruction without needing any additional information provided by additional operands. Immediate The immediate addressing mode instructions contain a 3-bit,2 8-bit or 12-bit3 immediate field as an operand. Immediate addressing is so-named because the value needed to complete the instruction is provided immediately to the core within the instruction code. That is to say, the instruction itself dictates what the data value is to be e.g. stored in a register. Direct The direct addressing mode instructions contain an 8-bit address operand that directly points to a location within the data memory space. Direct addressing is so-named because the value needed to complete the instruction must be directly accessed by the core from the memory address provided by the instruction code. Indirect The indirect addressing mode instructions use the content in XLO, X[7:0], to address a specific location within the data mem- ory space (0x00 – 0xFF).

4 Indirect addressing is so-named because the value needed to complete the instruction must be

retrieved indirectly by the core from the address provided by the X-pointer. Indexed The indexed offset addressing mode instructions add an 8-bit unsigned offset value to the X-pointer yielding a new effective address to select a specific location anywhere within the memory map (both program and data memory space, 0x000-0xFFF). Indexed addressing expands the functions of indirect addressing by providing the only means to access the data stored within the program memory space. Absolute The absolute jump addressing mode instructions (e.g. JMP and JSR) replace the program counter with the value in the operand field. This allows jumping to any location within the program memory space. Relative The opcode instruction field for the relative jump addressing mode instruction, JP, is calculated from the distance to the abso- lute program memory location in the operand addressing the next instruction to be executed. The base opcode for JP is 0xC0 where bit 5 indicates the direction within memory to jump. Bits 4 to 0 indicate the number of bytes to jump where the maxi- mum distance is 31 bytes. If bit 5 is zero, the address for the next instruction executed is determined by subtracting the lower 5 bits of the opcode (0xC1-0xDF) from the program counter; otherwise, the lower 5 bits of the opcode (0xE0-0xFF) are added to the program counter.

Table 24. Instruction Addressing Modes

Table 25. Instruction Cycles and Bytes

FMS7401/7401L PRODUCT SPECIFICATION 54 REV. 1.0.2 6/23/04 1. The FMS7401/7401L’s normal mode operation begins after a system reset and is when the 8-bit microcontroller core begins executing the instruction program residing in the code EEPROM memory. During this time, the code EEPROM memory may only be read by software not written. Refer to the Device Memory section of the datasheet for additional memory addressing information. 2. A 3-bit value in cases like the IFBIT and IFNBIT instructions. 3. A 12-bit value in the case of instructions writing to X. 4. The content of XHI (X[10:8]) is ignored. 5. The program memory space for the FMS7401/7401L is 0xC00 to 0xFFF; however, the program counter will use only the 10 least significant bits of the address provided. 6. Although the JP instruction can jump forward 31 bytes, it can only jump backwards 30 bytes because the program counter is automatically incremented while the JP instruction is being executed.

PRODUCT SPECIFICATION FMS7401/7401L REV. 1.0.2 6/23/04 55 The FMS7401/7401L has 64 bytes of SRAM and 64 bytes of EEPROM (data EEPROM) available for data storage. It also has 1K Byte of EEPROM (code EEPROM) memory for program storage. During the device’s normal operation, software has both read and write access of SRAM and data EEPROM memories but has only read access of the code EEPROM.

1 That is, the code EEPROM is

protected from unauthorized writes that can corrupt its contents during normal operating conditions. The code EEPROM can only be written to when the device is in programming mode2 and if the write disable (WDIS) bit of Initialization Register 1 is set to 0 While in normal operating mode, the user can write to the data EEPROM array by polling the ready (R) flag of the status register then executing the appropriate instruction. If the R flag is 1, the data EEPROM block is ready to perform the next write. If the R flag is 0, the data EEPROM is busy performing a write operation. The data EEPROM array will set the R flag to 1 after completing the write operation. Attempts to read, write, or enter Halt/Idle Mode while the data EEPROM is busy (R=0) can affect the current data being written and cause the intruding read or write command to also fail. The SRAM, data EEPROM, code EEPROM, and all other data register are memory mapped for easy access by software (see T able 30). The microcontroller core has an 11-bit X-pointer register that may be used to address data bytes within the memory map.3 Bit 10 of the X-pointer (X[10] or XHI[1]) selects between the code and data memory space within the memory map. When X[10] is set to 1, the X-pointer selects the code memory space (addr. 0xC00 to 0xFFF) physically addresses a byte in the code EEPROM memory. Since the code EEPROM memory is 1K bytes, it requires only 10 address bits to physically address a byte of its memory. Bits 9-0 of the X-pointer (X[9:0] or {XHI[1:0],XLO[7:0]}) is the physical address of the code EEPROM used during a byte read instruction operation. When X[10] is set to 0, the X-pointer automatically addresses the data memory space (addr. 0x00 to 0xFF). Bits 9-0 of the X-pointer is the memory mapped (not physical) address for the entire data memory space (including the SRAM, data EEPROM, and all other data registers) used during a byte read/write instruction operation. In addition, when using X-pointer instructions with the "[X]" syntax, only the lower 8 bits of X are considered addressing the data memory space only. However, instructions with the "[#0,X]" syntax allow read access of the code memory space for look-up tables, etc. When using the X-pointer to address a byte in either the data or code memory space, software should load X with its 12-bit memory mapped address.

11.1 Initialization Registers

The FMS7401/7401L has four 8-bit wide non-volatile initialization registers that are only accessible by the user in program- ming mode (if the memory security bits are not enabled). Each register has a corresponding shadow volatile register that is automatically updated during a reset and is used to initialize specific on-chip peripherals. The Initialization Register 1 contains the three memory security bits, three feature enable bits, and the clock selection bit. T able 26 provides a detailed description of the Initialization Register 1. This register is defaulted to zero by the factory. The Initialization Register 2 contains the internal oscillator frequency trim setting, FOSC.4 Prior to leaving the factory, the inter- nal oscillator is trimmed to the appropriate frequency and the non-volatile register is pre-programmed. During a reset, the vol- atile shadow register (at address 0xBA) is updated with the factory programmed trim value. The shadow register associated with the Initialization Register 2 is accessibly by software during normal operation and may be written to in order to perform fine adjustments e.g. of the PWM timer outputs. If the software saved the original factory trim value, the software may restore the frequency to its original frequency. The Initialization Register 3 contains the factory calibration values for the two internal analog comparator circuits (Brown-out Reset and Programmable Comparator). The calibration is performed in order to configure the comparators to their proper lev- els (see T able 27). The non-volatile register is preprogrammed prior to leaving the factory. The Initialization Register 4 contains the factory calibration value for the internal current source generator as well as the default G0/T1HS1 and G5/T1HS2 port configuration. The factory calibrates the current source generator to ensure that, if enabled, G3 can source I SRC4 of current. During the initial clock cycles of the reset sequence, the shadow register is updated configuring the G0/T1HS1 and G5/T1HS2 I/O ports to their pre-determined initial states. This offers the capability of driving G0/T1HS1 and G5/T1HS2 high within the first T DIO4 after the device is powered. The non-volatile register is pre-programmed

value since writes to a single register must affect all bits. Table 26. Initialization Register 1 Bit Definitions Table 27. Initialization Register 3 Bit Definitions Table 28. Initialization Register 4 Bit Definitions accessed by the core in order to modify the internal clock frequency. (4) WDEN If set, the on-chip processor Watchdog Timer resets are enabled. (3) BOREN If set, the on-chip Brown-out Reset comparator circuit is enabled. programming and normal mode. (5:3) BOR_TRIM These three bits allow for the calibration of the Brown-out Reset comparator circuit. (2:0) COMP_TRIM These three bits allow for the calibration of the Programmable Comparator’s upper range circuit. (7) T1HS_DIR Initializes during reset, the T1HS1 (G0) and T1HS2 (G5) I/O ports both either inputs or outputs. This bit shadows directly to bits 0 and 5 of PORTGC. shadow directly to bits 0 and 5 of PORTGD. (4:0) ISOURCE_TRIM These five bits allow for the calibration of internal current source generator.

Table 29. T1HS1 (G0) and T1HS2 (G5) Default Configuration

11.2 Memory Map

Table 30. Memory Mapped Registers

Table 31. Memory Mapped Registers and their Register Bit Definitions

1. The FMS7401/7401L’s normal mode operation begins after a system reset and is when the 8-bit microcontroller core begins executing the instruction program

residing in the code EEPROM memory.

1. The FMS7401/7401L must be placed in a special programming mode of operation in order to have full write and read access of all of the device memories. Refer

to the In-circuit Programming Specification section of the datasheet for details.

1. Refer to the the 8-Bit Microcontroller Core section of the datasheet for additional details.
2. Refer to the Electrical Characteristics section of the datasheet.
3. The Initialization Register 2 shadow register will automatically be restored with its original factory setting during a system reset.
4. Once the read and/or write protection is enabled, the only possible external action of accessing the memory in programming mode is to issue a “Program Erase”

access to the user enabling new device memory programming for the single programming mode session (unless the non-volatile WDIS and RDIS bits are cleared). Refer to the In-circuit Programming Specification section of the datasheet for addition details.

1. The register can only be read.
2. The register cannot be access during normal operation only in programming mode.
3. All SR bits except for bit 7 (the global interrupt mask) are read only when using direct, indirect, or indexed instructions. Software cannot restore SR using the tradi-

section of the datasheet for additional details.

ure 19 and the timing rules defined by the parameters listed in Table 31 as shown in Figure 20 and Figure 21. Figure 19. Programming Mode Pin Configurations Table 32. Programming Interface Electrical Characteristics2

12.1 Programming Mode Interface

powered with a low pulse on the device RESET pin.

3 After power-up, the external programmer must shift in the 10-bit opcode

mode once the system reset sequence has completed.

PRODUCT SPECIFICATION FMS7401/7401L REV. 1.0.2 6/23/04 61 The opcode must be shifted in after Vcc settles to its nominal voltage level and before the system reset sequence (TRESET) com- pletes. Otherwise, the device will begin with its normal operation executing the instruction program residing in the code EEPROM memory. If an external reset is applied by bringing the RESET pin low, the 10-bit opcode may be shifted once RESET is released and before the system reset sequence completes.

12.2 Programming Protocol

Once the device is in programming mode, the programming protocol and commands may be issued. An externally controlled 4-wire interface consisting of a LOAD (G3) control, serial data SHIFT_IN (G4) input, serial data SHIFT_OUT (G2) output, and CLOCK (G1) pins are used to access the internal memory and registers. Communication between the external programmer and the FMS7401/7401L is performed through a 32-bit command and response word, as described in T able 23. The serial data timing for the 4-wire interface is shown in Figure 21 and the programming protocol is shown in Figure 20. In order to exit pro- gramming mode, the device must be powered down or an external reset must be applied.

12.2.1 Byte Write Sequence

After the external programmer puts the FMS7401/7401L into programming mode, the LOAD pin must be set to Vcc before serially shifting the first 32-bit command word using the SHIFT_IN and CLOCK signals. By definition, bit 31 of the command word must be shifted first followed by all other bits. With each bit of the 32-bit write command word shifted, the device shifts out a bit of the 32-bit response word from the previous command through the SHIFT_OUT pin. The external programmer may sample SHIFT_OUT after T ACCESS from the rising edge of CLOCK. The serial response word sent immediately after entering programming mode may contain indeterminate data. After all 32 bits of the command word are shifted, the external programmer must set the LOAD signal to 0V and apply two clock pulses to the CLOCK signal, as shown in Figure 20, to complete the program cycle. Once the LOAD signal is brought low, the SHIFT_OUT pin acts as the handshaking signal between the device and external programmer hardware. When execut- ing the write command, the device sets SHIFT_OUT low by the time the external programmer has issued the second rising edge of CLOCK informing the external programmer that the memory write is in progress. The external programmer must wait T READY for SHIFT_OUT to return high before returning the LOAD signal to Vcc to initiate the next command cycle.

12.2.2 Page Write Sequence

Page mode is a convenient and fast way to program the code EEPROM memory. In this mode, 16 bytes of data are written using a single write command followed by a stream of data bytes. Only full pages can be written in page mode where the address in the command word points to the beginning of a page.

4 After all 16 bytes of data has been shifted, the data will be

written at once speeding up the total write time by a factor of 16 compared to byte mode programming. Figure 22 shows the page mode programming protocol. Page mode’s 32-bit write command word is similar to a byte write command except that bit 31 must be set to 1 in order to enable page mode. The address in the page-write command word (bits 17 to 8) must select the page to program the 16 bytes of data (the page address is a multiple of the page size: 0x000, 0x010, 0x020, etc.). The first byte of the page to program must be placed in the last 8 bits of the page-write command word (bits 7 to 0). All other bytes in the page must immediately follow after the initial page-write command has been entered. The LOAD pin must be set to Vcc before serially shifting in the 32-bit page-write command word using the SHIFT_IN and CLOCK signals. By definition, bit 31 of the command word must be shifted first followed by all other bits. After all 32 bits of the command word are shifted, the external programmer must set the LOAD signal to 0V and apply two clock pulses to the CLOCK signal to latch the first byte of the page in its temporary data buffer. The LOAD signal must be returned to Vcc in order for the external programmer to shift the second byte of the page into the device (without repeating the command word). Once all 8 bits of the byte are shifted, the LOAD signal must again be set to 0V followed by two clocks pulses of the CLOCK signal in order to latch byte into its temporary data buffer. This process must be repeated until all 16 bytes are loaded into their data buffers. While the 16 th byte of data is being latched, the actual write to the code EEPROM page, selected by the address in the 32-bit page-write command word, occurs. Once the LOAD signal is brought low, the SHIFT_OUT pin acts as the handshaking signal

Vcc to initiate the next command cycle.

12.2.3 Byte Read Sequence

mand must be shifted to collect the last response word containing the last data byte read. Table 33. 32-Bit Command and Response Word Same as the input command word. Bit 30 Must be set to 0. Same as the input command word. initialization registers) otherwise 0. Same as the input command word. Bit 28 Set to 1 to access the code EEPROM otherwise 0. Same as the input command word. Bits 27 – 25 Must be set to 0. Same as the input command word. Bit 24 Set to 1 to perform a read or 0 to perform a write. Same as the input command word. Bit 22 Set to 1 to perform a program memory erase otherwise 0. Same as the input command word. Bits 23, 21 – 18 Must be set to 0. Same as the input command word. first byte of the page to write. Same as the input command word.

Figure 20. Programming Protocol Figure 21. Serial Data Timing1 Figure 22. Page Mode Protocol

32 Clock

8 Clock

FMS7401/7401L PRODUCT SPECIFICATION 64 REV. 1.0.2 6/23/04

12.2.4 Program Memory Erase

The external programmer may erase the entire code EEPROM memory array using two special program erase byte write commands. This special erase option may also be used to unlock memory protected (WDIS/RDIS=1) devices without compromising design secu- rity. The special program erase byte write command overrides the WDIS memory security bit if set. Once both special byte write commands are issued, the volatile Initialization Register 1 is automatically cleared to unprotect the current programming mode session and allow complete access of the device memories.

5 The external programmer may then re-program the code EEPROM with

a new pattern or permanently disable all security features by re-programming the non-volatile Initialization Register 1. All other memories, including the data EEPROM, are unaffected by the program erase commands. The special program erase protocol requires the external programmer to shift two 32-bit command words addressing two separate page addresses. The special program erase 32-bit command word is similar to a byte write command except that bit 22 must be set to 1 to enable the program erase mode. The code EEPROM memory must also be selected by setting bit 28 of the command word. The first command word must select all even pages of the memory by setting the address bits (bits 17 to 8) to 0x000. The second command word must select all odd pages by setting the address bits to 0x010 of the command word. Any data value (bits 7 to 0) shifted as part of the individual command word may be used to erase the pages of the code EEPROM. After each even/odd page program erase command is executed, the even/odd pages of the code EEPROM memory is filled with the data supplied in the command erasing their previous program code data values. If the external programmer issues only one of the (even/odd page) erase commands, only half the pages will be erased by the data selected and the volatile Initialization Register 1 will not be cleared. Therefore, the current programming mode session will remain protected if either the memory protection (WDIS/RDIS) bits are set. After the external programmer puts the FMS7401/7401L into programming mode, the LOAD pin must be set to Vcc before serially shifting the first 32-bit program erase command word using the SHIFT_IN and CLOCK signals. By definition, bit 31 of the command word must be shifted first and then followed by all other bits. With each bit of the 32-bit write command word shifted, the device shifts out a bit of the 32-bit response word from the previous command through the SHIFT_OUT pin. The external programmer may sample SHIFT_OUT after T ACCESS from the rising edge of CLOCK. The serial response word sent immediately after entering programming mode may contain indeterminate data. After all 32 bits of the command word are shifted, the external programmer must set the LOAD signal to 0V and apply two clock pulses to the CLOCK signal, as shown in Figure 20 , to complete the program cycle. Once the LOAD signal is brought low, the SHIFT_OUT pin acts as the handshak- ing signal between the device and external programmer hardware. When executing the write command, the device sets SHIFT_OUT low by the time the external programmer has issued the second rising edge of CLOCK informing the external programmer that the memory write is in progress. The external programmer must wait T READY for SHIFT_OUT to return high before returning the LOAD signal to Vcc to initiate the second program erase command cycle. The volatile Initialization Register 1 will only be cleared if both commands are successfully executed. All other memory accesses from this point forward are executed normally. 1. During in-circuit programming, G5 must be either not connected or driven high. 2. The following characteristics are guaranteed by design but are not 100% tested. 3. For addition detail regarding the device power-up and reset conditions refer the Reset Circuit section of the datasheet. 4. Each page in the code EEPROM has 16 bytes and starts at address 0xC00, 0xC10, 0xC20, etc. 5. For additional details regarding the WDIS, RDIS, and initialization registers, refer to the Device Memory section of the datasheet.

PRODUCT SPECIFICATION FMS7401/7401L REV. 1.0.2 6/23/04 65 Absolute Maximum Ratings Operating Conditions *. Contact your local Fairchild Sales Representative for FMS7401 availability. Parameter Min. Typ. Max. Unit Ambient Storage Temperature -65 +150 °C Input Voltage -0.3 Vcc + 0.3 V Vcc Input Voltage 4.0 V Lead Temperature (10s max) +300 °C Electrostatic Discharge on all pins 2000 V Internal Voltage Regulator output current 5 mA Relative Humidity (non-condensing) 95% EEPROM write limits See AC Electrical Characteristics

FMS7401/7401L PRODUCT SPECIFICATION 66 REV. 1.0.2 6/23/04 13.1 FMS7401L (2.7V to 3.6V) All measurements are valid for TA=+25°C unless otherwise stated. Symbol Parameter Conditions Min. Typ. Max. Units ICC1 Active Supply Current (without data EEPROM writes in progress) F ICLK=FOSC2 -40°C to 125°C 0.75 1.2 mA Active Supply Current (with data EEPROM writes in progress) FICLK=FOSC2 -40°C to 125°C 0.9 2.0 mA Active Supply Current (without data EEPROM writes in progress) FICLK=F(FS=0)2 -40°C to 125°C 6.5 13 mA ISTR3 Start-up Current 250 µA ICCH Halt Mode Current -40°C to 85°C 1.3 5 µA -40°C to 125°C 8.3 15 µA ICCL4 Idle Mode Current -40°C to 125°C 180 270 µA SVcc3 Power Supply Ramp Rate 1V/10mS 1V/1µs VIL Input Low with Schmitt Trigger buffer -40°C to 125°C 0.2Vcc V VIH Input High with Schmitt Trigger buffer -40°C to 125°C 0.8Vcc V ITL Tri-State Leakage -40°C to 125°C 0.01 1 µA IIP Input Pull-up Current V IN=0V 85 350 µA VOL Output Low Voltage (G1, G2, G3, G4, G6, G7) 5mA sink current -40°C to 125°C 0.3Vcc V Output Low Voltage (G0, G5) 2mA sink current -40°C to 125°C 0.3Vcc V VOH Output Low Voltage (G1, G2, G3, G4, G6, G7) 5mA source current -40°C to 125°C 0.7Vcc V Output Low Voltage (G0, G5) 2mA source current -40°C to 125°C 0.7Vcc V

PRODUCT SPECIFICATION FMS7401/7401L REV. 1.0.2 6/23/04 67 All measurements are valid for TA=+25°C unless otherwise stated. Brown-out Reset (BOR) Electrical Characteristics All measurements are valid for TA=+25°C unless otherwise stated. Programmable Comparator Electrical Characteristics All measurements are valid for TA=+25°C unless otherwise stated. Symbol Parameter Conditions Min. Typ. Max. Units FOSC5 Internal oscillator frequency (factory trim set-point) Vcc=3.3V 1.96 2.00 2.04 MHz ∆ckv Internal oscillator frequency voltage variation -0.5 +0.5 % ∆ckt Internal oscillator frequency temperature variation Vcc=3.3V -40°C to 85°C -3 +3 % Vcc=3.3V -40°C to 125°C -4 +4 % FPLL PLL input reference frequency 2.00 MHz TPLL_LOCK3 PLL Lock time -40°C to 125°C 60 µS TEEW EEPROM Writing time 3.7 5 mS TRESET3 System reset time -40°C to 125°C 2.5 3.7 4.7 mS TDIO3 T1HS1 and T1HS2 default I/O configuration settling time 40 µS THALT_REC3 Internal device start time after exiting from Halt where FICLK = FOSC2 -40°C to 125°C 5 7 µS Parameter Conditions Min. Typ. Max. Units BOR Trigger Vcc Threshold Level 2.64 2.71 2.78 V -40°C to +85°C 2.60 2.83 V -40°C to 125°C 2.59 2.83 V Parameter Conditions Min. Typ. Max. Units All 32 thresholds (V THU) -6% V THU +6% V Upper Range (0.45V to 2.0V) -40°C to 125°C -8% V THU +8% V All 31 thresholds (VTHL) V THU – 30mV V THL VTHU + 30mV V Lower Range (0.03V to 0.43V) -40°C to 125°C V THU – 35mV V THL V THU + 35mV V Comparator Response Time3 2mV overdrive 359 nS 5mV overdrive 173 nS 10mV overdrive 95 nS

FMS7401/7401L PRODUCT SPECIFICATION 68 REV. 1.0.2 6/23/04 All measurements are valid for TA=+25°C unless otherwise stated. Independent Amplifier Electrical Characteristics3 Parameter Conditions Min. Typ. Max. Units ADC Integral Non Linearity (INL) Best Fit3 VAREF=Vcc ASPEED=0 where (FICLK=FOSC)/12

1.5 LSB

VAREF=Internal Reference (VREF) ASPEED=0 where (FICLK=FOSC)/12 VAREF=Internal Reference (VREF) ASPEED=2 where (FICLK=FOSC)/42 -40°C to +125°C

0.5 LSB

Linearity (DNL)3 Vref=Vcc ASPEED=0 where (F ICLK=FOSC)/12

2.5 LSB

VAREF=Internal Reference (VREF) ASPEED=0 where (FICLK=FOSC)/12 VAREF=Internal Reference (VREF) ASPEED=2 where (FICLK=FOSC)/42 -40°C to +125°C

1 LSB

ADC Conversion Time3 ASPEED=0 where (FICLK=FOSC)/12 -40°C to +125°C 20 µS Internal Voltage Reference (VREF)3 1.215 V Amplifier x16 Gain Error3 -40°C to +125°C 2 2 % Current Source (ISRC) on G3/AIN1 0.9 1 1.1 mA Current Source (ISRC) on G3/AIN1 -40°C to +125°C 0.89 1 1.11 mA Parameter Conditions Min. Typ. Max. Units Input Bias Current -40°C to +125°C -1 +1 µA Input Offset Voltage -40°C to +125°C 4 mV Open Loop Voltage Gain -40°C to +125°C 97 dB Gain Bandwidth Product -40°C to +125°C 3.7 MHz Sink/Source Current -40°C to +125°C 0.5 4.5 mA

PRODUCT SPECIFICATION FMS7401/7401L REV. 1.0.2 6/23/04 77 1. ICC Active current is dependent on the program code and number of active circuits. The ICC Active current specified is measured with the microcontroller core, PWM Timer 1, Timer 0, ADC, Uncommitted Amplifier, and Programmable Comparator circuits all active. 2. Refer to the Clock Circuit section of the datasheet for details regarding the FMS7401/7401L ’s main system instruction clock (FICLK) and its clock sources (FOSC or F(FS=0)). 3. The parameter is guaranteed by design but is not 100% tested. 4. The I CC Idle current is based on a continuous Idle Mode looping program and is dependent on the program code. 5. The upper FOSC frequency (4MHz) device option is available upon request.

FMS7401/7401L PRODUCT SPECIFICATION 78 REV. 1.0.2 6/23/04 Ordering Information*,† *SOIC and TSSOP packages are available upon request. Contact your local Fairchild Sales Representative. †Contact your local Fairchild Sales Representative for FMS7401 availability. Packaging Option Method Qty FMS7401LEN PDIP8 2.7V to 3.6V -40°C to 85°C Rail 40 FMS7401LVN PDIP8 2.7V to 3.6V -40°C to 125°C Rail 40 FMS7401LEN14 PDIP14 2.7V to 3.6V -40°C to 85°C Rail 25 FMS7401LVN14 PDIP14 2.7V to 3.6V -40°C to 125°C Rail 25

PRODUCT SPECIFICATION FMS7401/7401L REV. 1.0.2 6/23/04 79 Physical Dimensions†† 8-Pin PDIP 14-Pin PDIP ††Dimensions are in inches (millimeters) unless otherwise noted. 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337)DIA 1234 8765 0.250 - 0.005 (6.35 ±0.127) 870.032 ±0.005 (0.813 ±0.127) Pin #1 Option 2 RAD 0.145 - 0.200 (3.683 - 5.080) 0.130 ±0.005 (3.302 ±0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) Min0.018 ±0.003 (0.457 ±0.076) 90° 4 ° Typ 0.100 ±0.010 (2.540 ±0.254) 0.040 (1.016) 0.039 (0.991) Typ. 20° ±1° 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) Pin #1 IDENT Option 1

0.280 MIN

0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762)MAX 0.125 (3.175) DIA NOM 0.009 - 0.015 (0.229 - 0.381) 0.045 ±0.015 (1.143 ±0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95° ±5 0.090 (2.286) (7.112) IDENT 8-Pin PDIP 14 13 12 123 14-Pin PDIP 14 13 12 0.740 – 0.770 (18.80 – 19.56) 11 10 9 8 1234567 0.145 – 0.200 (3.683 – 5.080) 0.125 – 0.150 (3.175 – 3.810) 0.014 – 0.023 (0.355 – 0.584) 0.135 ±0.005 (7.620 – 8.128) 0.008 – 0.016 (0.203 – 0.406) 0.250 – 0.010 (6.350 – 0.254) 0.090 (2.286) 0.060 (1.524) 0.092 (2.337) 0.280 (7.112) MIN 0.065 (1.651) 0.020 (0.508) MIN 0.030 (0.762)DIA MAX DEPTH 4° TYP OPTIONAL OPTION 1 TYP 0.325 8.255 TYP TYP 0.050 ± 0.010 (1.270 – 0.254) 0.075 ± 0.015 (1.905 ± 0.381) +0.040 –0.015 +1.016 –0.381 TYP 0.100 ± 0.010 (2.540 ± 0.254)TYP OPTION 02 PIN NO. 1 IDENT PIN NO. 1 IDENT INDEX AREA

FMS7401/7401L PRODUCT SPECIFICATION 6/23/04 0.0m 005 Stock#DS30007401  2004 Fairchild Semiconductor Corporation LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.