FMS6406CS

FMS6406 ONSEMI | Alldatasheet

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© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FMS6406 Rev. 4.0.4 August 2006 FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation

Features

7.6MHz 5th-order Y,C filters with composite summer 14dB notch at 4.425MHz to 4.6MHz for sound trap capable of handling stereo 50dB stopband attenuation at 27MHz on Y, C, and CV outputs Better than 0.5dB flatness to 4.2MHz on Y, C, and CV outputs Equalizer and notch filter for driving RF modulator with group delay of -180ns No external frequency selection components or clocks < 5ns group delay on Y, C, and CV outputs AC coupled inputs AC or DC coupled outputs Capable of PAL frequency for Y, C, CV Continuous Time Low Pass Filters <1.4% differential gain with 0.7° differential phase on Y, C, and CV channels Integrated DC restore circuitry with low tilt

Applications

Description

The FMS6406 is a dual Y/C 5th-order Butterworth lowpass video filter optimized for minimum overshoot and flat group delay. The device also contains a summing circuit to generate filtered composite video, an audio trap and group delay compensation circuit. The audio trap removes video information in the spectral location of the subsequent RF audio carrier. The group delay circuit predistorts the signal to compensate for the inherent receiver IF filter’s group delay distortion. In a typical application, the Y and C input signals from DACs are AC-coupled into the filters. Both channels have DC-restore circuitry to clamp the DC-input levels during video sync. The Y and C channels use separate feedback clamps. The clamp pulse is derived from the Y channel. All outputs are capable of driving 2Vpp, AC or DC-coupled, into either a single or dual video load. A single video load consists of a series 75 W impedance matching resistor connected to a terminated 75W line, this presents a total of 150W of loading to the part. A dual load would be two of these in parallel which would present a total of 75W to the part. The gain of the Y, C and CV signals is 6dB with 1Vpp input levels. All video channels are clamped during sync to establish the appropriate output voltage reference levels.

Ordering Information

Part Number Package Pb-Free Operating Temp Range Packaging Method FMS6406CS SOIC-8 Yes 0°C to +70°C Tube FMS6406CSX SOIC-8 Yes 0°C to +70°C Tape and Reel Block Diagram YIN CIN COUT EQ_NOTCH YOUT Sync Strip Reference and Timing CVOUT gM 250mV gM 250mV 6dB GND VCC 6dB Notch Group Delay

© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FMS6406 Rev. 4.0.4 FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation FMS6406 Pin Configuration FMS6406 8-pin SOIC YIN YOUT EQ_NOTCH GND CVOUT VCC COUTCIN 4 5 Pin Assignments Pin# Pin Type Description

1 YIN Input Luminance (Luma) Input: In a typical

system, this pin is connected to the Luma or composite video output pin from the external video encoder.

2 EQ_NOTCH Output Composite video output to RF

modulator/driver.

3 GND Input Ground

4 CIN Input Chrominance (Chroma) Input: In a

typical system, this pin is connected to the Chroma output pin from the external video encoder.

5 COUT Output Filtered Chrominance Video Output

from the CIN channel.

6 CVOUT Output Composite Video Output: This pin is

the sum of YOUT and COUT. 7 VCC Input +5V supply.

8 YOUT Output Filtered Luminance Video Output

from the YIN channel.

© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FMS6406 Rev. 4.0.4 FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation Absolute Maximum Ratings The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the conditi- ons for actual device operation. Parameter Min. Max. Unit VCC -0.3 6 V Analog and Digital I/O -0.3 VCC + 0.3 V Output Channel - Any One Channel (Do Not Exceed) 100 mA Notes: Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if operating conditions are not exceeded. Reliability Information Parameter Min. Typ. Max. Unit Junction Temperature 150 °C Storage Temperature Range -65 +150 °C Lead Temperature (Soldering, 10s) 300 °C Thermal Resistance (qJA), JEDEC Standard Multi-layer Test Boards, Still Air 115 °C/W Recommended Operating Conditions Parameter Min Typ Max Unit Operating Temperature Range 0 70 °C VCC Range +4.75 +5.0 +5.25 V GND 0 V

© 2006 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FMS6406 Rev. 4.0.4 FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation

Electrical Characteristics

Tc = 25°C, Vi = 1Vpp, VCC = 5V, all inputs AC-coupled with 0.1μF, all outputs are AC-coupled with 220μF into 150Ω, referenced to 400kHz; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units ICC Supply Current1 VCC no load 50 80 110 mA AVYCCV Low Frequency Gain (YOUT, COUT, CVOUT)1 at 400kHz 5.8 6.0 6.2 dB AVEQ Low Frequency Gain (EQ_NOTCH)1 at 400kHz 5.7 6.0 6.4 dB Csync COUT Output Level (during Sync)1 Sync present on YIN (after 6dB gain) 1.0 1.1 1.3 V Ysync YOUT Output Level (during Sync)1 Sync present on YIN (after 6dB gain) 0.35 0.5 V CVsync CVOUT Output Level (during Sync)1 Sync present on YIN (after 6dB gain) 0.35 0.5 V EQsync EQ_NOTCH Output Level (during Sync)1 Sync present on YIN (after 6dB gain) 0.35 0.5 V TCLAMP Clamp Response Time (Y Channel) Settled to within 10mV 5 ms fFLAT Gain Flatness to 4.2MHz2 (YOUT, COUT, CVOUT) -0.5 0 0.5 dB fC -3dB Bandwidth1 Y, C, CV Channels 6.7 7.6 MHz fSB Stopband Attenuation1 (YOUT, COUT, CVOUT) at 27MHz 40 50 dB Vi Input Signal Dynamic Range All Channels/AC coupled 1.4 Vpp ISC Output Short Circuit Current4 (Any One Channel) Y, C, CV, EQ_NOTCH to GND 85 mA dG Differential Gain2 Y, C, CV 1.4 3 % dq Differential Phase2 Y, C, CV 0.7 1.5 ° THD Output Distortion (All Channels) VOUT = 1.8Vpp at 3.58MHz 0.3 % XTALK Crosstalk (Channel-to-Channel) at 3.58MHz -50 dB PSRR PSRR (All Channels) DC 50 dB SNR SNR Y, C Channel2 NTC-7 weighting 4.2MHz lowpass 70 75 dB SNR CV Channel2 NTC-7 weighting 4.2MHz lowpass 70 75 dB SNR EQ_NOTCH Channel2 NTC-7 weighting 4.2MHz lowpass 65 70 dB tpd Propagation Delay (Y, C, CV) at 400kHz 112 ns GD Group Delay (Y, C, CV)2 at 3.58MHz (NTSC) -5 0 5 ns tSKEW Skew Between YOUT and COUT 2 at 1MHz -2 0 2 ns tCLGCV Chroma-Luma Gain CVOUT 1 f = 3.58MHz (ref to YIN at 400kHz) 98 100 102 % tCLDCV Chroma-Luma Delay CVOUT 1 f = 3.58MHz (ref to YIN at 400kHz) -10 0 10 ns GDEQ Group Delay EQ_NOTCH1 f = 3.58MHz (ref to YIN at 400kHz) -195 -180 -165 ns tCLGEQ Chroma-Luma Gain EQ_NOTCH1 f = 3.58MHz (ref to YIN at 400kHz) 95 100 105 % tCLDEQ Chroma-Luma Delay EQ_NOTCH1 f = 3.58MHz (ref to YIN at 400kHz) -195 -180 -165 ns dGEQ Differential Gain2 EQ_NOTCH Channel 0.3 1 % dqEQ Differential Phase2 EQ_NOTCH Channel 0.3 0.75 % MCF Modulator Channel Flatness1,3 EQ_NOTCH from 400kHz to 3.75MHz -0.5 0 0.5 dB AVPK Gain Peaking1 EQ_NOTCH from >3.75MHz to 4.2MHz -0.5 0 0.5 dB Atten1 Notch Attenuation 11 EQ_NOTCH at 4.425MHz 14 dB Atten2 Notch Attenuation 21 EQ_NOTCH at 4.5MHz 20 dB Atten3 Notch Attenuation 31 EQ_NOTCH at 4.6MHz 14 dB tPASS Passband Group Delay, EQ_NOTCH1 f = 400kHz to f = 3MHz -35 35 ns Notes: 100% tested at 25°C. Guaranteed by characterization. Tested down to 400kHz, but guaranteed by design to 200kHz. Sustained short circuit protection limited to 10 seconds.

© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FMS6406 Rev. 4.0.4 FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation Typical Performance Characteristics Tc = 25°C, Vi = 1Vpp, VCC = 5V, all inputs AC-coupled with 0.1μF, all outputs are AC-coupled with 220μF into 150Ω, referenced to 400kHz; unless otherwise noted. 140Delay (ns) 400kHz 5 10 15 25 20 30 Frequency (MHz) 120 100 -10 -20 -30 -40 -50 -60 Gain (dB) 400kHz 5 10 15 25 20 30 Frequency (MHz) Mkr Frequency Gain Ref 400kHz 6dB 1 6.53MHz -1dB BW 2 7.87MHz -3dB BW 3 27MHz -44.66dB fSB = Gain(ref) – Gain(3) = 50.66dB 1 2 1 = 8.2MHz (111.35ns) 140Delay (ns) 400kHz 5 10 15 25 20 30 Frequency (MHz) 120 100 -10 -20 -30 -40 -50 -60 Gain (dB) 400kHz 5 10 15 25 20 30 Frequency (MHz) Mkr Frequency Gain Ref 400kHz 6dB 1 6.68MHz -1dB BW 2 7.87MHz -3dB BW 3 27MHz -44.41dB fSB = Gain(ref) – Gain(3) = 50.41dB 1 2 1 = 8.2MHz (111.16ns) 140Delay (ns) 400kHz 5 10 15 25 20 30 Frequency (MHz) 120 100 -10 -20 -30 -40 -50 -60 Gain (dB) 400kHz 5 10 15 25 20 30 Frequency (MHz) Mkr Frequency Gain Ref 400kHz 6dB 1 6.53MHz -1dB BW 2 7.72MHz -3dB BW 3 27MHz -43.49dB fSB = Gain(ref) – Gain(3) = 49.49dB 1 = 8.2MHz (112.84ns) 1 2 Figure . Frequency Response CVOUT Figure 6. Group Delay vs. Frequency CVOUT Figure . Frequency Response COUT Figure 4. Group Delay vs. Frequency COUT Figure . Frequency Response YOUT Figure . Group Delay vs. Frequency YOUT

are AC-coupled with 220μF into 150Ω, referenced to 400kHz; unless otherwise noted. Figure 7. Differential Gain, CVOUT Figure 8. Differential Phase, CVOUT

are AC-coupled with 220μF into 150Ω, referenced to 400kHz; unless otherwise noted. Figure 9. Noise vs. Frequency YOUT Figure 0. Noise vs. Frequency COUT

© 2006 Fairchild Semiconductor Corporation 9 www.fairchildsemi.com FMS6406 Rev. 4.0.4 FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation Typical Application Diagrams Figure . AC-Coupled Application Diagram Figure . DC-Coupled Application Diagram YOUTYIN To TV CVOUT to VCR COUT Notch and Group Delay Video Modulator 5th-Order Filter CIN 5th-Order Filter FMS6406 To Channel 3 or 4 4.5MHz FM Sound YOUTYIN To TV CVOUT to VCR COUT Notch and Group Delay Video Modulator 5th-Order Filter CIN 5th-Order Filter FMS6406 To Channel 3 or 4 4.5MHz FM Sound

© 2006 Fairchild Semiconductor Corporation 0 www.fairchildsemi.com FMS6406 Rev. 4.0.4 FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation Functional Description Introduction This product is a two channel monolithic continuous time video filter designed for reconstructing the luminance and chrominance signals from an S-Video D/A source. Composite video output is generated by summing the Y and C outputs. The chip is designed to have AC coupled inputs and will work equally well with either AC or DC coupled outputs. The reconstruction filters provide a 5th-order Butterworth response with group delay equalization. This provides a maximally flat response in terms of delay and amplitude. Each of the four outputs is capable of driving 2V pp into a 75Ω load. All channels are clamped during the sync interval to set the appropriate minimum output DC level. With this operation the effective input time constant is greatly reduced, which allows for the use of small low cost coupling capacitors. The net effect is that the input will settle to 10mV in 5ms for any DC shifts present in the input video signal. In most applications the input coupling capacitors are 0.1μF. The Y and C inputs typically sink 1μA of current during active video, which normally tilts a horizontal line by 2mV at the Y output. During sync, the clamp restores this leakage current by sourcing an average of 20μA over the clamp interval. Any change in the coupling capacitor values will affect the amount of tilt per line. Any reduction in tilt will come with an increase in settling time. Luminance (Y) I/O The typical luma input is driven by either a low impedance source of 1V pp or the output of a 75Ω terminated line driven by the output of a current DAC. In either case, the input must be capacitively coupled to allow the sync- detect and DC restore circuitry to operate properly. All outputs are capable of driving 2Vpp, AC or DC-coupled, into either a single or dual video load. A single video load consists of a series 75Ω impedance matching resistor connected to a terminated 75Ω line, this presents a total of 150Ω of loading to the part. A dual load would be two of these in parallel which would present a total of 75Ω to the part. The gain of the Y, C and CV signals is 6dB with 1Vpp input levels. Even when two loads are present the driver will produce a full 2Vpp signal at its output pin. Chrominance (C) I/O The chrominance input can be driven in the same manner as the luminance input but is typically only a 0.7Vpp signal. Since the chrominance signal doesn’t contain any DC content, the output signal can be AC coupled using as small as a 0.1μF capacitor if DC-coupling is not desired. Composite Video (CV) Output The composite video output driver is same as the other outputs. When driving a dual load either output will still function if the other output connection is inadvertently shorted providing these loads are AC-coupled. Equalizer/Notch (EQ_NOTCH) Output This output is designed to drive a 600Ω load to 2V pp, which will meet its primary intention of driving a modulator load. Layout Considerations General layout and supply bypassing play major roles in high-frequency performance and thermal characteristics. The FMS6406DEMO is a 4-layer board with a full power and ground plane. Following this layout configuration will provide the optimum performance and thermal characte- ristics. For optimum results, follow the steps below as a basis for high frequency layout: Include 1μF and 0.1μF ceramic bypass capacitors Place the 1μF capacitor within 0.75 inches of the power pin Place the 0.1μF capacitor within 0.1 inches of the power pin For multi-layer boards, use a large ground plane to help dissipate heat For 2-layer boards, use a ground plane that extends beyond the device by at least 0.5” Minimize all trace lengths to reduce series inductances

© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FMS6406 Rev. 4.0.4 FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation Mechanical Dimensions 8-Lead Outline Package (SOIC)

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