FM93C86

FM93C86A FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

I Wide VCC 2.7V - 5.5V I User selectable organization x16 (ORG = 1) x8 (ORG = 0) I Typical active current of 200µA 10µA standby current typical 1µA standby current typical (L) 0.1µA standby current typical (LZ) I No Erase instruction required before Write instruction I Self timed write cycle I Device status during programming cycles I 40 year data retention I Endurance: 1,000,000 data changes I Packages available: 8-pin SO and 8-pin DIP INSTRUCTION DECODER CONTROL LOGIC AND CLOCK GENERATORS HIGH VOLTAGE GENERATOR AND PROGRAM TIMER INSTRUCTION REGISTER ADDRESS REGISTER EEPROM ARRAY READ/WRITE AMPS DATA IN/OUT REGISTER 16/8 BITS DECODER DATA OUT BUFFER CS SK DI ORG DO VSS VCC

FM93C86A 16K-Bit Serial CMOS EEPROM(MICROWIRE TM Synchronous Bus) www.fairchildsemi.com FM93C86A Rev. C.1 Connection Diagram Dual-In-Line Package (N) and 8–Pin SO (M8) Top View Package Number N08E and M08A Pin Names CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground ORG Organization NC No Connect VCC Power Supply NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation.

Ordering Information

NM 93 C XX A LZ E XXX Letter Description Package N 8-pin DIP M8 8-pin SO Temp. Range None 0 to 70 °C V -40 to +125 °C E -40 to +85 °C Voltage Operating Range Blank 4.5V to 5.5V L 2.7V to 5.5V LZ 2.7V to 5.5V and <1µA Standby Current A x8 or x16 configuration Density 86 16,384 bits C CMOS CS Data protect and sequential read Interface 93 MICROWIRE Fairchild Memory Prefix VCC ORG GND CS SK DI DO NC

FM93C86A 16K-Bit Serial CMOS EEPROM(MICROWIRE TM Synchronous Bus) www.fairchildsemi.com FM93C86A Rev. C.1 Absolute Maximum Ratings (Note 1) Ambient Storage Temperature -65 °C to +150°C All Input or Output Voltages +6.5V to -0.3V with Respect to Ground Lead Temperature (Soldering, 10 sec.) +300 °C ESD rating 2000V Operating Conditions Ambient Operating Temperature FM93C86A 0 °C to +70°C FM93C86AE -40 °C to +85°C FM93C86AV -40 °C to +125°C Power Supply (VCC) 4.5V to 5.5V DC and AC Electrical Characteristics VCC = 4.5V to 5.5V unless otherwise specified Symbol Parameter Conditions Min Max Units ICCA Operating Current CS = V IH, SK=1.0 MHz 1 mA ICCS Standby Current CS = V IL 50 µA IIL Input Leakage V IN = 0V to VCC ±-1 µA IOL Output Leakage (Note 2) IILO Input Leakage ORG Pin ORG tied to V CC -1 1 µA ORG tied to VSS (Note 3) -2.5 2.5 VIL Input Low Voltage -0.1 0.8 V VIH Input High Voltage 2 V CC +1 VOL1 Output Low Voltage I OL = 2.1 mA 0.4 V VOH1 Output High Voltage I OH = -400 µA 2.4 VOL2 Output Low Voltage I OL = 10 µA 0.2 V VOH2 Output High Voltage I OH = -10 µAV CC - 0.2 fSK SK Clock Frequency (Note 4) 1 MHz tSKH SK High Time 0 °C to +70°C 250 ns -40°C to +125°C 300 tSKL SK Low Time 250 ns tCS Minimum CS Low Time (Note 5) 250 ns tCSS CS Setup Time 50 ns tDH DO Hold Time 70 ns tDIS DI Setup Time 100 ns tCSH CS Hold Time 0 ns tDIH DI Hold Time 20 ns tPD Output Delay 500 ns tSV CS to Status Valid 500 ns tDF CS to DO in Hi-Z CS = V IL 100 ns tWP Write Cycle Time 10 ms

FM93C86A 16K-Bit Serial CMOS EEPROM(MICROWIRE TM Synchronous Bus) www.fairchildsemi.com FM93C86A Rev. C.1 Absolute Maximum Ratings (Note 1) Ambient Storage Temperature -65 °C to +150°C All Input or Output Voltages +6.5V to -0.3V with Respect to Ground Lead Temperature (Soldering, 10 sec.) +300 °C ESD rating 2000V Operating Conditions Ambient Operating Temperature FM93C86AL/LZ 0 °C to +70°C FM93C86ALE/LZE -40 °C to +85°C FM93C86ALV/LZV -40 °C to +125°C Power Supply (VCC) 2.7V to 5.5V DC and AC Electrical Characteristics VCC = 2.7V to 4.5V unless otherwise specified. Refer to page 3 for 4.5V to 5.5V VCC Symbol Parameter Conditions Min Max Units ICCA Operating Current CS = V IH, SK=250 KHz 1 mA ICCS Standby Current CS = V IL L 10 µA LZ (2.7V to 4.5V) 1 µA IIL Input Leakage V IN = 0V to VCC ±1 µA IOL Output Leakage (Note 2) IILO Input Leakage ORG Pin ORG tied to V CC -1 1 µA ORG tied to VSS (Note 3) -2.5 2.5 VIL Input Low Voltage -0.1 0.15V CC V VIH Input High Voltage 0.8V CC VCC +1 VOL Output Low Voltage I OL = 10µA 0.1V CC V VOH Output High Voltage I OH = -10µA 0.9V CC fSK SK Clock Frequency (Note 4) 0 250 KHz tSKH SK High Time 1 µs tSKL SK Low Time 1 µs tCS Minimum CS Low Time (Note 5) 1 µs tCSS CS Setup Time 0.2 µs tDH DO Hold Time 70 ns tDIS DI Setup Time 0.4 µs tCSH CS Hold Time 0 ns tDIH DI Hold Time 0.4 µs tPD Output Delay 2 µs tSV CS to Status Valid 1 µs tDF CS to DO in Hi-Z CS = V IL 0.4 µs tWP Write Cycle Time 15 ms Capacitance TA = 25°C, f = 1 MHz or

250 KHz (Note 6)

COUT Output Capacitance 5 pF CIN Input Capacitance 5 pF Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: Typical leakage values are in the 20nA range. Note 3: ORG pin may draw >1 µA when in x8 mode due to the internal pull-up transistor. Note 4: The shortest allowable SK clock period = 1/f SK (as shown under the fSK parameter). Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated in the datasheet. Within this SK period, both t SKH and tSKL limits must be observed. Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation. Note 5: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode diagram on the following page.) Note 6: This parameter is periodically sampled and not 100% tested. AC Test Conditions VCC Range V IL/VIH VIL/VIH VOL/VOH IOL/IOH Input Levels Timing Level Timing Level (Extended Voltage Levels) (TTL Levels) Output Load: 1 TTL Gate (CL = 100 pF)

DI and DO pins are ignored while CS is held low. of this clock input. This pin is gated by CS signal. rising edge of the SCK. This pin is gated by CS signal. active only when the device is selected. would default to 16-bit data format. (for 16-bit format) and Table 2 (for 8-bit format). device before clocking a “1”. This is a 2-bit field and should immediately follow the start bit. particular instruction to be executed. MSB 2 bits are used to decode instruction (along with Opcode bits). Table 1. Instruction set (16-bit organization)

Start bit (“1”) should be issued to properly recognize the cycle. 7 instructions is explained in detail in the following sections. enabled at the end of this cycle when the CS signal is brought low. device is write-enabled (Refer WEN instruction). Table 2. The self-timed programming cycle starts with the clocking ready for another instruction. memory locations with the data pattern specified in the instruction. Table 2. Instruction set (8-bit organization)

FM93C86A 16K-Bit Serial CMOS EEPROM(MICROWIRE TM Synchronous Bus) www.fairchildsemi.com FM93C86A Rev. C.1 5) Write Disable (WDS) Write Disable (WDS) instruction disables all programming opera- tions and should follow all programming operations. Executing this instruction after a valid write instruction would protect against accidental data disturb due to spurious noise, glitches, inadvert- ent writes etc. Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table 1 or Table 2. The device becomes write-disabled at the end of this cycle when the CS signal is brought low. Execution of a READ instruction is independent of WDS instruction. Refer Write Disable cycle diagram. 6) Erase (ERASE) The ERASE instruction will program all bits in the specified location to logical “1” state. Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table 1 or Table 2. The self-timed programming cycle starts with the clocking of the last data bit (DO). It takes tWP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recom- mended that no new instruction be issued. Refer Erase cycle diagram. 7) Erase All (ERAL) The Erase all instruction will program all locations to logical “1” state. Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table 1 or Table 2. The self-timed programming cycle starts with the clocking of the last data bit (DO). It takes tWP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruc- tion be issued. Refer Erase All cycle diagram. Note: The Fairchild CMOS EEPROMs do not require an “ERASE” or “ERASE ALL” instruction prior to the “WRITE” or “WRITE ALL” instruction, respectively. The “ERASE” and “ERASE ALL” instructions are included to maintain compatibility with earlier technology EEPROMs. Clearing of Ready/Busy status When programming is in progress, the Data-Out pin will display the programming status as either BUSY (low) or READY (high) when CS is brought high (DO output will be tri-stated when CS is low). To restate, during programming, the CS pin may be brought high and low any number of times to view the programming status without affecting the programming operation. Once programming is completed (Output in READY state), the output is ‘cleared’ (returned to normal tri-state condition) by clocking in a Start Bit. After the Start Bit is clocked in, the output will return to a tri-stated condition. When clocked in, this Start Bit can be the first bit in a command string, or CS can be brought low again to reset all internal circuits. Refer Clearing Ready Status diagram. Related Document PROM.

FM93C86A 16K-Bit Serial CMOS EEPROM(MICROWIRE TM Synchronous Bus) www.fairchildsemi.com FM93C86A Rev. C.1 tCSS SYNCHRONOUS DATA TIMING CS SK DI DO (Data Read) DO (Status Read) Valid Status tDIS tDIH tPD tDH tSV tSKH tSKL tCSH tDF tDF tPD Valid Input Valid Input Valid Output Valid Output CS SK DI DO High - Z Dummy Bit 1 1 0 A1 A0

0 D1 D0

/;/;/; /;/;/; READ CYCLE (READ) Address Bits(10/11) Start Bit Opcode Bits(2) 93C86A (ORG=1; An=A9; D n=D15 ): Address bits pattern -> A9-A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined 93C86A (ORG=0; An=A10; D n=D7 ): Address bits pattern -> A10-A9-A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined An An-1 Dn Timing Diagrams Address Bits(10/11) CS SK DI DO High - Z WRITE ENABLE CYCLE (WEN) Start Bit Opcode Bits(2) 1 0 0 A1 A0 tCS An An-1 93C86A (ORG=1; An=A9 ): Address bits pattern -> 1-1-x-x-x-x-x-x-x-x; (x -> Don ’t Care, can be 0 or 1) 93C86A (ORG=0; An=A10 ): Address bits pattern -> 1-1-x-x-x-x-x-x-x-x-x; (x -> Don ’t Care, can be 0 or 1)

FM93C86A 16K-Bit Serial CMOS EEPROM(MICROWIRE TM Synchronous Bus) www.fairchildsemi.com FM93C86A Rev. C.1 Timing Diagrams (Continued) Address Bits(10/11) CS SK DI DO High - Z WRITE DISABLE CYCLE (WDS) Start Bit Opcode Bits(2) 1 0 0 A1 A0 tCS 93C86A (ORG=1; An=A9 ): Address bits pattern -> 0-0-x-x-x-x-x-x-x-x; (x -> Don ’t Care, can be 0 or 1) 93C86A (ORG=0; An=A10 ): Address bits pattern -> 0-0-x-x-x-x-x-x-x-x-x; (x -> Don ’t Care, can be 0 or 1) An An-1 Address Bits(10/11) Data Bits(16/8) CS SK DI DO High - Z WRITE CYCLE (WRITE) Start Bit 93C86A (ORG=1; An=A9; D n=D15 ): Address bits pattern -> A9-A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined Data bits pattern -> D15-to-D0; User defined 93C86A (ORG=0; An=A10; D n=D7 ): Address bits pattern -> A10-A9-A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined Data bits pattern -> D7-to-D0; User defined Opcode Bits(2) 1 0 1 An An-1 A1 A0 Dn Dn-1 D1 Busy Ready tWP Address Bits(10/11) Data Bits(16/8) CS SK DI DO High - Z WRITE ALL CYCLE (WRALL) Start Bit Opcode Bits(2) 1 0 0 A1 A0 D1 Busy Ready tWP 93C86A (ORG=1; An=A9; D n=D15 ): Address bits pattern -> 0-1-x-x-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1) Data bits pattern -> D15-to-D0; User defined 93C86A (ORG=0; An=A10; D n=D7 ): Address bits pattern -> 0-1-x-x-x-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1) Data bits pattern -> D7-to-D0; User defined An An-1 Dn Dn-1 D0

FM93C86A 16K-Bit Serial CMOS EEPROM(MICROWIRE TM Synchronous Bus) www.fairchildsemi.com FM93C86A Rev. C.1 Timing Diagrams (Continued) CS SK DI DO High - Z High - Z CLEARING READY STATUS Start Bit Note: This Start bit can also be part of a next instruction. Hence the cycle can be continued(instead of getting terminated, as shown) as if a new instruction is being issued. Busy Ready Address Bits(10/11) CS SK DI DO High - Z ERASE CYCLE (ERASE) Start Bit Opcode Bits(2) 1 1 1 A1 A0 Busy Ready tWP An An-1 93C86A (ORG=1; An=A9): Address bits pattern -> A9-A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined 93C86A (ORG=0; An=A10 ): Address bits pattern -> A10-A9-A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined Address Bits(10/11) CS SK DI DO High - Z ERASE ALL CYCLE (ERAL) Start Bit Opcode Bits(2) 1 0 0 A1 A0 Busy Ready tWP 93C86A (ORG=1; An=A9 ): Address bits pattern -> 1-0-x-x-x-x-x-x-x-x; (x -> Don ’t Care, can be 0 or 1) 93C86A (ORG=0; An=A10 ): Address bits pattern -> 1-0-x-x-x-x-x-x-x-x-x; (x -> Don ’t Care, can be 0 or 1) An An-1

FM93C86A 16K-Bit Serial CMOS EEPROM(MICROWIRE TM Synchronous Bus) www.fairchildsemi.com FM93C86A Rev. C.1 Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8) Package Number M08A Physical Dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) Lead #1 IDENT Seating Plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) Typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) Typ 0.016 - 0.050 (0.406 - 1.270) Typ. All Leads 8¡ Max, Typ. All leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads 0.004 (0.102) All lead tips 0.010 - 0.020

FM93C86A 16K-Bit Serial CMOS EEPROM(MICROWIRE TM Synchronous Bus) www.fairchildsemi.com FM93C86A Rev. C.1 Physical Dimensions inches (millimeters) unless otherwise noted Molded Dual-In-Line Package (N) Package Number N08E 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337)DIA 1234 8765 0.250 - 0.005 (6.35 ± 0.127) 870.032 ± 0.005 (0.813 ± 0.127) Pin #1 Option 2 RAD 0.145 - 0.200 (3.683 - 5.080) 0.130 ± 0.005 (3.302 ± 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) Min0.018 ± 0.003 (0.457 ± 0.076) 90° ± 4° Typ 0.100 ± 0.010 (2.540 ± 0.254) 0.040 (1.016) 0.039 (0.991) Typ. 20° ± 1° 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) Pin #1 IDENT Option 1

0.280 MIN

0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762)MAX 0.125 (3.175) DIA NOM 0.009 - 0.015 (0.229 - 0.381) 0.045 ± 0.015 (1.143 ± 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95° ± 5° 0.090 (2.286) (7.112) IDENT Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Americas Europe Hong Kong Japan Ltd. Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg. Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan Franç ais Tel: +33 (0) 1-6930-3696 Tel; +852-2722-8338 Tel: 81-3-3818-8840 Italiano Tel: +39 (0) 2-249111-1 Fax: +852-2722-8383 Fax: 81-3-3818-8841