FM27C512QE120

FM27C512_01 FAIRCHILD | Alldatasheet

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— 90, 120, 150 ns access time I Fast turn-off for microprocessor compatibility I Manufacturers identification code I JEDEC standard pin configuration — 32-pin PLCC package — 28-pin CERDIP package DS800035-1 AMG is a trademark of WSI, Inc. © 2001 Fairchild Semiconductor Corporation Output Enable and Chip Enable Logic Y Decoder X Decoder Output Buffers 524,288-Bit Cell Matrix Data Outputs O0 - O7VCC GND VPP OE CE/PGM A0 - A15 Address Inputs

2 www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C512 Rev. A Connection Diagrams Compatible EPROM pin configurations are shown in the blocks adjacement to the FM27C512 pins. Commercial Temp Range (0°C to +70°C) Parameter/Order Number Access Time (ns) FM27C512 Q, V 90 90 FM27C512 Q, V 120 120 FM27C512 Q, V 150 150 Industrial Temp Range (-40°C to +85°C) Parameter/Order Number Access Time (ns) FM27C512 QE, VE 90 90 FM27C512 QE, VE 120 120 FM27C512 QE, VE 150 150 Q = Quartz-Windowed Ceramic DIP Package V = PLCC Package

• All packages conform to the JEDEC standard.
• All versions are guaranteed to function for slower speeds. Pin Names A0–A15 Addresses CE/PGM Chip Enable/Program OE Output Enable O0–O7 Outputs NC Don ’t Care (During Read) PLCC DIP FM27C512 A11 NC OE/VPP A10 CE/PGM NC A12 A15 NC VCC A14 A13 GND NC 14 15 16 17 18 19 20 4 3 2 1 32 31 30 DS800035-2 DS800035-3 A15 A12 GND VCC A14 A13 A11 OE/VPP A10 CE/PGM VCC XX/PGM XX A14 A13 A11 OE A10 CE VCC A14 A13 A11 OE A10 CE/PGM 27C256 27C010 27C040 VCC A18 A17 A14 A13 A11 OE A10 CE/PGM 27C040 27C010 27C256 XX/VPP A16 A15 A12 GND XX/VPP A16 A15 A12 GND VPP A12 GND

3 www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C512 Rev. A Absolute Maximum Ratings (Note 1) Storage Temperature -65 °C to +150°C All Input Voltages Except A9 with Respect to Ground -0.6V to +7V VPP and A9 with Respect to Ground -0.7V to +14V VCC Supply Voltage with Respect to Ground -0.6V to +7V ESD Protection (MIL Std. 883, Method 3015.2) >2000V All Output Voltages with Respect to Ground V CC + 1.0V to GND -0.6V Operating Range Range Temperature V CC Tolerance Commercial 0 °C to +70°C +5V ±10% Industrial -40 °C to +85°C +5V ±10% Read Operation Symbol Parameter Test Conditions Min Max Units VIL Input Low Level -0.5 0.8 V VIH Input High Level 2.0 V CC +1 V VOL Output Low Voltage I OL = 2.1 mA 0.4 V VOH Output High Voltage I OH = -2.5 mA 3.5 V ISB1 VCC Standby Current (CMOS) CE = V CC ±0.3V 100 µA ISB2 VCC Standby Current CE = V IH 1m A ICC1 VCC Active Current CE = OE = V IL f = 5 MHz 40 mA ICC2 VCC Active Current CE = GND, f = 5 MHz CMOS Inputs Inputs = V CC or GND, I/O = 0 mA 35 mA C, E Temp Ranges IPP VPP Supply Current V PP = VCC 10 µA VPP VPP Read Voltage V CC - 0.7 V CC V ILI Input Load Current V IN = 5.5V or GND -1 1 µA ILO Output Leakage Current V OUT = 5.5V or GND -10 10 µA Symbol Parameter 90 120 150 Units Min Max Min Max Min Max tACC Address to Output Delay 90 120 150 ns tCE CE to Output Delay 90 120 150 tOE OE to Output Delay 40 50 50 tDF Output Disable to 35 25 45 Output Float tOH Output Hold from Addresses, CE or OE, 0 0 0 Whichever Occurred First

4 www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C512 Rev. A Capacitance TA = +25°C, f = 1 MHz (Note 2) Symbol Parameter Conditions Typ Max Units CIN1 Input Capacitance V IN = 0V 6 12 pF except OE/VPP COUT Output Capacitance V OUT = 0V 9 12 pF CIN2 OE/VPP Input V IN = 0V 20 25 pF Capacitance AC Test Conditions Output Load 1 TTL Gate and C L = 100 pF (Note 8) Input Rise and Fall Times ≤5 ns Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level (Note 9) Inputs 0.8V and 2V Outputs 0.8V and 2V AC Waveforms (Notes 6, 7) Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tACC –tOE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE, the measured VOH1 (DC) - 0.10V; Low to TRI-STATE, the measured VOL1 (DC) + 0.10V. Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA. CL: 100 pF includes fixture capacitance. Note 9: Inputs and outputs can undershoot to -2.0V for 20 ns Max. Address Valid Valid OutputHi-Z 0.8V 0.8V 0.8V ADDRESS OUTPUT CE OE tCE2V 0.8V (Note 3) (Note 3) tDF (Note 4, 5) (Note 4, 5) tOH Hi-Z tOE ACCt CFt DS800035-4

5 www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C512 Rev. A Programming Characteristics (Note 10) and (Note 11) Symbol Parameter Conditions Min Typ Max Units tAS Address Setup Time 1 µs tOES OE Setup Time 1 µs tDS Data Setup Time 1 µs tVCS VCC Setup Time 1 µs tAH Address Hold Time 0 µs tDH Data Hold Time 1 µs tCF Chip Enable to Output Float Delay OE = V IL 06 0 n s tPW Program Pulse Width 45 50 105 µs tOEH OE Hold Time 1 µs tDV Data Valid from CE OE = V IL 250 ns tPRT OE Pulse Rise Time 50 ns during Programming tVR VPP Recovery Time 1 µs IPP VPP Supply Current during CE = V IL 30 mA Programming Pulse OE = V PP ICC VCC Supply Current 50 mA TR Temperature Ambient 20 25 30 °C VCC Power Supply Voltage 6.25 6.5 6.75 V VPP Programming Supply Voltage 12.5 12.75 13 V tFR Input Rise, Fall Time 5 ns VIL Input Low Voltage 0 0.45 V VIH Input High Voltage 2.4 4 V tIN Input Timing Reference Voltage 0.8 2 V tOUT Output Timing Reference Voltage 0.8 2 V Programming Waveforms Note 10:Fairchild’s standard product warranty applies to devices programmed to specifications described herein. Note 11:VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC. Note 12:The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VCC to GND to suppress spurious voltage transients which may damage the device. t AS Program Program Verify Address N t CF Hi-Z t DS t DH t VPS t PW t OEH t AH 2.0V 0.8V 2.0V 0.8V 6.25V Addresses Data OE/VPP VCC 0.8V t OES Data Out Valid ADD N Data In Stable ADD N 2.0V 0.8V t DV t PRT 12.75V t VCS t VR CE/PGM DS800035-5

6 www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C512 Rev. A Turbo Programming Algorithm Flow Chart FIGURE 1. VCC = 6.5V VPP = 12.75V n = 0 ADDRESS = FIRST LOCATION CHECK ALL BYTES 1ST: VCC = VPP = 6.0V 2ND: VCC = VPP = 4.3V PROGRAM ONE 50µs PULSE INCREMENT n ADDRESS = FIRST LOCATION VERIFY BYTE n = 10?DEVICE FAILED LAST ADDRESS INCREMENT ADDRESS n = 0 PROGRAM ONE 50 µs PULSE INCREMENT ADDRESS VERIFY BYTE LAST ADDRESS PASS NO FAIL YES YES PASS NO FAIL NO YES DS800035-6Note: The standard National Semiconductor algorithm may also be used but it will take longer programming time.

7 www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C512 Rev. A Functional Description DEVICE OPERATION The six modes of operation of the EPROM are listed in Table1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are V CC and OE/VPP. The OE/VPP power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The V CC power supply must be at 6.5V during the three programming modes, and at 5V in the other three modes. Read Mode The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE/V PP) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (t ACC) is equal to the delay from CE to output (t CE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC – tOE. Standby Mode The EPROM has a standby mode which reduces the active power dissipation by over 99%, from 220 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE/PGM input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Output Disable The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI- STATE). Output OR-Typing Because the EPROM is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommo- dates this use of multiple memory connections. The 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE/PGM be decoded and used as the primary device select- ing function, while OE/V PP be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. Programming CAUTION: Exceeding 14V on pin 22 (OE/V PP) will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the “1’s” state. Data is introduced by selectively programming “0’s” into the desired bit locations. Although only “0’s” will be pro- grammed, both “1’s” and “0’s” can be presented in the data word. The only way to change a “0” to a “1” is by ultraviolet light erasure. The EPROM is in the programming mode when the OE/VPP is at 12.75V. It is required that at least a 0.1 µF capacitor be placed across VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active low, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the Turbo Programming Algo- rithm shown in Figure 1. Each Address is programmed with a series of 50 µs pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 µs pulse. (The standard National Semiconductor Algorithm may also be used but it will have longer programming time.) The EPROM must not be programmed with a DC signal applied to the CE/PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the parallel EPROM may be con- nected together when they are programmed with the same data. A low level TTL pulse applied to the CE/PGM input programs the paralleled EPROM. Program Inhibit Programming multiple EPROMs in parallel with different data is also easily accomplished. Except for CE/PGM all like inputs (including OE/V PP) of the parallel EPROMs may be common. A TTL low level program pulse applied to an EPROM ’s CE/PGM input with OE/VPP at 12.75V will program that EPROM. A TTL high level CE/PGM input inhibits the other EPROMs from being pro- grammed. Program Verify A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify is accom- plished with OE/V PP and CE at V IL. Data should be verified T DV after the falling edge of CE. AFTER PROGRAMMING Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents. MANUFACTURER’S IDENTIFICATION CODE The EPROM has a manufacturer ’s identification code to aid in programming. When the device is inserted in an EPROM pro- grammer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. The Manufacturer’s Identification code, shown in Table 2, specifi- cally identifies the manufacturer and device type. The code for FM27C512 is “8F85”, where “8F” designates that it is made by Fairchild Semiconductor, and “85” designates a 512K part. The code is accessed by applying 12V ±0.5V to address pin A9. Addresses A1–A8, A10–A16, and all control pins

erasure should be minimum of 15W-sec/cm2. distance is doubled the erasure time increases by factor of 4). ously suspected when incomplete erasure was the problem. levels excepts for VPP and A9 for device signature. TABLE 1. Mode Selection Note 13: X can be VIL or VIH. TABLE 2. Manufacturer’s Identification Code

9 www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C512 Rev. A UV Window Cavity Dual-In-Line Cerdip Package (JQ) Order Number FM27C512Q Package Number J28CQ Physical Dimensions inches (millimeters) unless otherwise noted 0.008-0.012 [0.203-0.305] TYP 0.090-0.110 [2.286-2.794] TYP 0.060-0.100 [1.524-2.540] TYP 0.015-0.021 [0.381-0.533] TYP 0.033-0.045 [0.838-1.143] TYP 0.225 [5.715] MAX TYP 0.125 [3.175] MIN TYP GLASS SEALANT R 0.025 [0.635] 0.290-0.310 [7.366-7.874] U.V. WINDOW R 0.030-0.055 [0.762-1.397] TYP 0.515-0.530 [13.081-13.462]

1.465 MAX

[37.211] 0.050-0.060 [1.270-1.524] TYP 0.180 [4.572] MAX 0.010 [0.254] MAX 0.015-0.060 [0.381-1.524] TYP 86°-94° TYP 0.590-0.620 [14.99-15.75] 0.685 +0.025 -0.060 [17.399 ] +0.635 -1.524 90°-100° TYP

10 www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C512 Rev. A Physical Dimensions inches (millimeters) unless otherwise noted 32-Lead Plastic Leaded Chip Carrier (PLCC) Order Number FM27C512V 0.007[0.18] AS SF-G 0.007[0.18] B SD-E 0.449-0.453 [11.40-11.51] S 0.045 [1.143] 0.000-0.010 [0.00-0.25] Polished Optional 0.585-0.595 [14.86-15.11] 0.549-0.553 [13.94-14.05] -B- -F- -E- -G- 0.050 3014 2014 -D- 0.007[0.18] B SD-ES 0.002[0.05] B S -A- 0.485-0.495 [12.32-12.57] 0.007[0.18] AS SF-G A0.002[0.05] S 0.007[0.18] HS SD-E, F-G 0.010[0.25] B A SD-E, F-G 0.118-0.129 [3.00-3.28] L B B 45°X 0.042-0.048 [1.07-1.22] 0.026-0.032 [0.66-0.81] Typ 0.0100 [0.254] 0.030-0.040 [0.76-1.02]R 0.005 [0.13] Max 0.020 [0.51] 0.045 [1.14] Detail A Typical Rotated 90° 0.027-0.033 [0.69-0.84] 0.025 [0.64] Min 0.025 [0.64] Min 0.031-0.037 [0.79-0.94] 0.053-0.059 [1.65-1.80] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64] 0.065-0.071 [1.65-1.80] 0.021-0.027 [0.53-0.69] Section B-B Typical S 0.007[0.18] CM SD-E, F-G 0.490-0530 [12.45-13.46] 0.078-0.095 [1.98-2.41] 0.013-0.021 [0.33-0.53] 0.004[0.10] 0.123-0.140 [3.12-3.56] See detail A -J- -C- 0.400 [10.16]( ) TYP 0.541-0.545 [13.74-13-84] 0.023-0.029 [0.58-0.74] 0.106-0.112 [2.69-2.84] 0.015 [0.38] Base Plane -H- Min Typ S Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Americas Europe Hong Kong Japan Ltd. Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg. Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan Franç ais Tel: +33 (0) 1-6930-3696 Tel; +852-2722-8338 Tel: 81-3-3818-8840 Italiano Tel: +39 (0) 2-249111-1 Fax: +852-2722-8383 Fax: 81-3-3818-8841 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.