FM27C010 FAIRCHILD | Alldatasheet
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—70 ns access time I Fast turn-off for microprocessor compatibility I Simplified upgrade path —V PP and PGM are “Don’t Care” during normal read operation I Manufacturers identification code I Fast programming I JEDEC standard pin configurations —32-pin PDIP package —32-pin PLCC package —32-pin CERDIP package DS800032-1 © 2000 Fairchild Semiconductor Corporation Output Enable, Chip Enable, and Program Logic Y Decoder X Decoder Output Buffers 1,048,576-Bit Cell Matrix Data Outputs O0 - O7 VCC GND VPP OE PGM CE A0 - A16 Address Inputs
2 www.fairchildsemi.com FM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C010 Connection Diagrams DIP PIN CONFIGURATIONS Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the FM27C010 pins. Commercial Temperature Range (0°C to +70°C) VCC = 5V ±10% Parameter/Order Number Access Time (ns) FM27C010 Q, V, N 90 90 FM27C010 Q, V, N 120 120 FM27C010 Q, V, N 150 150 Extended Temperature Range (-40°C to +85°C) VCC = 5V ±10% Parameter/Order Number Access Time (ns) FM27C010 QE, VE, NE 90 90 FM27C010 QE, VE, NE 120 120 FM27C010 QE, VE, NE 150 150 Q = Quartz-Windowed Ceramic DIP package V = PLCC package N = Plastic DIP package
- All packages conform to JEDEC standard.
- All versions are guaranteed to function at slower speeds. Pin Names A0–A16 Addresses CE Chip Enable OE Output Enable O0–O7 Outputs PGM Program XX Don ’t Care (During Read) PLCC Pin Configuration Top View DS800032-10 XX/VPP A16 A15 A12 GND XX/VPP A16 A15 A12 GND 27C040 DIP FM27C010 VCC XX/PGM XX A A13 A11 OE A CE O VPP A12 GND 27C256 A15 A12 GND 27C512 27C040 VCC A18 A17 A14 A13 A11 OE A10 CE/PGM VCC A14 A13 A11 OE/VPP A10 CE/PGM VCC A14 A13 A11 OE A10 CE/PGM 27C256 27C512 A14 A13 A11 OE A10 CE O A12 A15 A16 XX/VPP VCC XX/PGM XX O GND 14 15 16 17 18 19 20 4 3 2 1 32 31 30 DS800032-3
3 www.fairchildsemi.com FM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C010 Absolute Maximum Ratings (Note 1) Storage Temperature -65 °C to +150°C All Input Voltages Except A9 with Respect to Ground (Note 10) -0.6V to +7V VPP and A9 with Respect to Ground -0.6V to +14V VCC Supply Voltage with Respect to Ground -0.6V to +7V ESD Protection >2000V All Output Voltages with Respect to Ground (Note 10) V CC + 1.0V to GND - 0.6V Operating Range Range Temperature V CC Tolerance Commercial 0 °C to +70°C +5V ±10% Extended -40 °C to +85°C +5V ±10% DC Read Characteristics Over Operating Range with VPP = VCC Symbol Parameter Test Conditions Min Max Units VIL Input Low Level -0.5 0.8 V VIH Input High Level 2.0 V CC +1 V VOL Output Low Voltage I OL = 2.1 mA 0.4 V VOH Output High Voltage I OH = -2.5 mA 3.5 V ISB1 VCC Standby Current CE = V CC ± 0.3V 100 µA (CMOS) ISB2 VCC Standby Current (TTL) CE = V IH 1m A ICC VCC Active Current CE = OE = V IL f = 5 MHz 30 mA I/O = 0 mA IPP VPP Supply Current V PP = VCC 10 µA VPP VPP Read Voltage V CC - 0.7 V CC V ILI Input Load Current V IN = 5.5 or GND -1 1 µA ILO Output Leakage Current V OUT = 5.5V or GND -10 10 µA AC Read Characteristics Over Operating Range with VPP = VCC Symbol Parameter 70 90 120 150 Units MinMax MinMax MinMax Min Max tACC Address to Output Delay 70 90 120 150 tCE CE to Output Delay 70 90 120 150 tOE OE to Output Delay 35 40 50 50 tDF Output Disable to Output 30 35 35 45 ns (Note 2) Float tOH Output Hold from (Note 2) Addresses, CE or OE , 0 0 0 0 Whichever Occurred First Capacitance TA = +25°C, f = 1 MHz (Note 2) Symbol Parameter Conditions Typ Max Units CIN Input Capacitance V IN = 0V 6 15 pF COUT Output Capacitance V OUT = 0V 10 15 pF
4 www.fairchildsemi.com FM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C010 AC Test Conditions Output Load 1 TTL Gate and C L = 100 pF (Note 8) Input Rise and Fall Times ≤5 ns Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level Inputs 0.8V and 2V Outputs 0.8V and 2V AC Waveforms (Note 6), (Note 7), and (Note 9) Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE® , the measured VOH1 (DC) - 0.10V; Low to TRI-STATE, the measured VOL1 (DC) + 0.10V. Note 5: TRI-STATE may be attained using OE or CE. Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA. CL: 100 pF includes fixture capacitance. Note 9: VPP may be connected to VCC except during programming. Note 10:Inputs and outputs can undershoot to -2.0V for 20 ns Max. Programming Characteristics (Note 11), (Note 12), (Note 13), and (Note 14) Symbol Parameter Conditions Min Typ Max Units tAS Address Setup Time 1 µs tOES OE Setup Time 1 µs tCES CE Setup Time OE = V IH 1 µs tDS Data Setup Time 1 µs tVPS VPP Setup Time 1 µs tVCS VCC Setup Time 1 µs tAH Address Hold Time 0 µs tDH Data Hold Time 1 µs tDF Output Enable to Output Float Delay CE = V IL 06 0 n s tPW Program Pulse Width 45 50 105 µs Address Valid Valid OutputHi-Z 0.8V 0.8V 0.8V ADDRESS OUTPUT CE OE tCE 0.8V (Note 3) (Note 3) tDF (Note 4, 5) (Note 4, 5) tOH Hi-Z tOE tACC tCF DS800032-4
5 www.fairchildsemi.com FM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C010 Programming Characteristics (Note 11), (Note 12), (Note 13), and (Note 14) (Continued) Symbol Parameter Conditions Min Typ Max Units tOE Data Valid from OE CE = V IL 100 ns IPP VPP Supply Current during CE = V IL 15 mA Programming Pulse PGM = V IL ICC VCC Supply Current 20 mA TA Temperature Ambient 20 25 30 °C VCC Power Supply Voltage 6.2 6.5 6.75 V VPP Programming Supply Voltage 12.5 12.75 13.0 V tFR Input Rise, Fall Time 5 ns VIL Input Low Voltage 0.0 0.45 V VIH Input High Voltage 2.4 4.0 V tIN Input Timing Reference Voltage 0.8 2.0 V tOUT Output Timing Reference Voltage 0.8 2.0 V Programming Waveforms (Note 13) Note 11:Fairchild’s standard product warranty applies only to devices programmed to specifications described herein. Note 12:VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC. Note 13:The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device. Note 14:During power up the PGM pin must be brought high (≥VIH) either coincident with or before power is applied to VPP. tAS tAH Program Program Verify Address N tDF Data Out Valid ADD N Data In Stable ADD N Hi-Z tDS tDH tVCS tVPS tCES tPW tOES tOE 0.8V 0.8V 6.25V 12.75V 0.8V 0.8V 0.8V ADDRESS DATA VCC CE PGM OE VPP DS800032-5
6 www.fairchildsemi.com FM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C010 Turbo Programming Algorithm Flow Chart FIGURE 1. DS800032-6 VCC = 6.5V VPP = 12.75V n = 0 ADDRESS = FIRST LOCATION CHECK ALL BYTES 1ST: VCC = VPP = 6.0V 2ND: VCC = VPP = 4.3V PROGRAM ONE 50µs PULSE INCREMENT n ADDRESS = FIRST LOCATION VERIFY BYTE n = 10?DEVICE FAILED LAST ADDRESS INCREMENT ADDRESS n = 0 PROGRAM ONE 50 µs PULSE INCREMENT ADDRESS VERIFY BYTE LAST ADDRESS PASS NO FAIL YES YES PASS NO FAIL NO YES Note: The standard National Semiconductor Algorithm may also be used but it will have longer programming time.
should be noted that all inputs for the six modes are at TTL levels. (CE) is the power control and should be used for device selection. gate data to the output pins, independent of device selection. impedance state, independent of the OE input.
- the lowest possible memory power dissipation, and
- complete assurance that output bus contention will not
active only when data is desired from a particular memory device. grammed, both “1’s” and “0’s” can be presented in the data word. The only way to change a “0” to a “1” is by ultraviolet light erasure. Figure 1. Each Address is programmed with a series of 50 µs memory cells will program with a single 50 µs pulse. nected together when they are programmed with the same data. CE input inhibits the other EPROM’s from being programmed. programming and program verify. programmers which have the capability of reading the code. The code is accessed by applying 12V ±0.5V to address pin A9. O0–07. Proper code access is only guaranteed at 25°C ± 5°C.
should be removed before erasure. distance is doubled the erasure time increases by factor of 4). ously suspected when incomplete erasure was the problem. levels except for VPP and A9 for device signature. TABLE 1. Modes Selection Note 15:X can be VIL or VIH. TABLE 2. Manufacturer’s Identification Code
9 www.fairchildsemi.com FM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C010 32-Lead EPROM Ceramic Dual-In-Line Package (Q) Order Number FM27C010QXXX Package Number J32AQ 32-Lead Molded Dual-In-Line Package (N) Order Number FM27C010NXXX Package Number 1.660 (42.16) 0.025 (0.64) R 0.030-0.055 (0.76 - 1.40) TYP UV WINDOW SIZE AND CONFIGURATION DETERMINED BY DEVICE SIZE 0.175 (4.45) MAX 0.060-0.100 (1.52 - 2.54) TYP 0.050-0.060 (1.27 - 1.52) TYP 0.015-0.021 (0.38 - 0.53) TYP 86°-94° TYP Glass Sealant 0.150 (3.81) 0.015 -0.060 (0.25 - 1.52) TYP 0.10 (2.54) MAX 0.090-0.110 (2.29 - 2.79) TYP 0.005 (0.127) MAX TYP 0.125 (3.18) 0.585 (14.86) MAX MAX R MIN TYP MIN TYP MIN TYP 0.225 (5.72) 0.590-0.620 (15.03 - 15.79) 90° - 100° TYP 0.685 (17.40) +0.025 (0.64) -0.060 (-1.523) 0.008-0.012 (0.20 - 0.30) TYP 1.64 – 1.66 (41.66 – 42.164) 0.062 (1.575) RAD Pin No. 1 IDENT 0.580 (14.73) MIN 0.600 – 0.620 (15.240 – 15.748) 0.145 – 0.210 (3.683 – 5.334) 0.040 - 0.090 (1.016 – 2.286) 0.050 (1.270) TYP TYP 0.125 – 0.165 (3.175 – 4.191) 0.018 ±0.003 (0.457 ±0.078) 0.035 – 0.07 (0.889 – 1.778) 86°- 94° TYP 0.120 – 0.150 (3.048 – 3.81) 0.015 (0.381) 0.100 ±0.010 (2.540 ±0.254) 90°–105° 0.008 - 0.015 (0.203 – 0.381) 0.490 – 0.550 (12.446 – 13.97) Physical Dimensions inches (millimeters) unless otherwise noted
10 www.fairchildsemi.com FM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM www.fairchildsemi.com FM27C010 Physical Dimensions inches (millimeters) unless otherwise noted 32-Lead PLCC Package Order Number FM27C010VXXX 0.007[0.18] AS SF-G 0.007[0.18] B SD-E 0.449-0.453 [11.40-11.51] S 0.045 [1.143] 0.000-0.010 [0.00-0.25] Polished Optional 0.585-0.595 [14.86-15.11] 0.549-0.553 [13.94-14.05] -B- -F- -E- -G- 0.050 3014 2014 -D- 0.007[0.18] B SD-ES 0.002[0.05] B S -A- 0.485-0.495 [12.32-12.57] 0.007[0.18] AS SF-G A0.002[0.05] S 0.007[0.18] HS SD-E, F-G 0.010[0.25] B A SD-E, F-G 0.118-0.129 [3.00-3.28] L B B 45°X 0.042-0.048 [1.07-1.22] 0.026-0.032 [0.66-0.81] Typ 0.0100 [0.254] 0.030-0.040 [0.76-1.02]R 0.005 [0.13] Max 0.020 [0.51] 0.045 [1.14] Detail A Typical Rotated 90° 0.027-0.033 [0.69-0.84] 0.025 [0.64] Min 0.025 [0.64] Min 0.031-0.037 [0.79-0.94] 0.053-0.059 [1.65-1.80] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64] 0.065-0.071 [1.65-1.80] 0.021-0.027 [0.53-0.69] Section B-B Typical S 0.007[0.18] CM SD-E, F-G 0.490-0530 [12.45-13.46] 0.078-0.095 [1.98-2.41] 0.013-0.021 [0.33-0.53] 0.004[0.10] 0.123-0.140 [3.12-3.56] See detail A -J- -C- 0.400 [10.16]( ) TYP 0.541-0.545 [13.74-13-84] 0.023-0.029 [0.58-0.74] 0.106-0.112 [2.69-2.84] 0.015 [0.38] Base Plane -H- Min Typ S Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Americas Europe Hong Kong Japan Ltd. Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg. Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan Franç ais Tel: +33 (0) 1-6930-3696 Tel; +852-2722-8338 Tel: 81-3-3818-8840 Italiano Tel: +39 (0) 2-249111-1 Fax: +852-2722-8383 Fax: 81-3-3818-8841 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.