FM25L04 ETC | Alldatasheet

Document overview

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Technical content

Features

4K bit Ferroelectric Nonvolatile RAM

  • Organized as 512 x 8 bits
  • Unlimited Read/Write Cycles
  • 45 Year Data Retention
  • NoDelay™ Writes
  • Advanced High-Reliability Ferroelectric Process Very Fast Serial Peripheral Interface - SPI
  • Up to 14 MHz Frequency
  • Direct Hardware Replacement for EEPROM
  • SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Write Protection Scheme
  • Hardware Protection
  • Software Protection Low Power Consumption
  • Low Voltage Operation 2.7-3.6V
  • 1 µA Standby Current Industry Standard Configuration
  • Industrial Temperature -40°C to +85°C
  • 8-pin SOIC
  • “Green” 8-pin SOIC

Description

The FM25L04 is a 4-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 45 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM25L04 performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. The next bus cycle may start immediately. In addition, the product offers virtually unlimited write endurance. Also, FRAM exhibits much lower power consumption than EEPROM. These capabilities make the FM25L04 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The FM25L04 provides substantial benefits to users of serial EEPROM as a hardware drop-in replacement. The FM25L04 uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration Pin Name Function /CS Chip Select /WP Write Protect /HOLD Hold SCK Serial Clock SI Serial Data Input SO Serial Data Output VDD Supply Voltage VSS Ground

Ordering Information

FM25L04-G “Green” 8-pin SOIC CS SO WP VSS VDD HOLD SCK SI

Figure 1. Block Diagram the status register. A complete explanation of write protection is provided below. logic level to meet IDD specifications.

  • SI may be connected to SO for a single pin data interface.

the falling edge of the serial clock.

  • SO may be connected to SI for a single pin data interface.

Rev. 2.0 May 2005 Page 3 of 12 Overview The FM25L04 is a serial FRAM memory. The memory array is logically organized as 512 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25L04 and a serial EEPROM with the same pinout is the FRAM’s superior write performance and power consumption. Memory Architecture When accessing the FM25L04, the user addresses 512 locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and an address. The upper address bit is included in the op- code. The complete address of 9-bits specifies each byte address uniquely. Most functions of the FM25L04 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25L04 due to its fast write cycle and high endurance as compared with EEPROM. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25L04 contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that V DD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip enable active. Serial Peripheral Interface – SPI Bus The FM25L04 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 14 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25L04 operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25L04 devices with a microcontroller that has a dedicated SPI port, as Figure 2 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25L04 device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off (high) the /HOLD pin. Figure 3 shows a configuration that uses only three pins. Protocol Overview The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25L04 will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25L04 supports Modes 0 and 3. Figure 4 shows the required signal relationships for Modes 0 and 3. For both modes, data is clocked into the FM25L04 on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer. Important: The /CS must go inactive (high) after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select.

Table 4. Write Protection

0 X Protected Protected Protected

any number of sequential writes may be performed. op-code. The next op-code is the WRITE instruction. first. A write operation is shown in Figure 9. until the byte being written has completed. master issues 8 clocks, with one bit read out for each. operation is shown in Figure 10. Figure 9. Memory Write Figure 10. Memory Read

Rev. 2.0 May 2005 Page 8 of 12 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +5.0V VIN Voltage on any pin with respect to V SS -1.0V to +5.0V and VIN < VDD+1.0V TSTG Storage Temperature -55°C to + 125°C TLEAD Lead Temperature (Soldering, 10 seconds) 300° C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply Voltage 2.7 3.3 3.6 V IDD VDD Supply Current @ SCK = 100 kHz @ SCK = 1.0 MHz @ SCK = 5.0 MHz @ SCK = 14.0 MHz 0.02 0.1 0.5 0.03 0.17 0.75 3.0 mA ISB Standby Current - 1 µA 2 ILI Input Leakage Current - ±1 µA 3 ILO Output Leakage Current - ±1 µA 3 VIH Input High Voltage 0.7 V DD V DD + 0.5 V VIL Input Low Voltage -0.3 0.3 V DD V VOH Output High Voltage @ IOH = -2 mA VDD – 0.8 - V VOL Output Low Voltage @ IOL = 2 mA - 0.4 V VHYS Input Hysteresis 0.05 V DD - V 4 Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD. 4. This parameter is characterized but not 100% tested.

Rev. 2.0 May 2005 Page 9 of 12 AC Parameters (TA = -40° C to + 85° C, CL = 30pF, unless otherwise specified) V DD 2.7 to 3.0V V DD 3.0 to 3.6V Symbol Parameter Min Max Min Max Units Notes fCK SCK Clock Frequency 0 10 0 14 MHz tCH Clock High Time 40 30 ns 1, 2 tCL Clock Low Time 40 30 ns 1 tCSU Chip Select Setup 10 10 ns tCSH Chip Select Hold 10 10 ns tOD Output Disable Time 30 25 ns 3 tODV Output Data Valid Time 40 30 ns 2 tOH Output Hold Time 0 0 ns tD Deselect Time 100 80 ns tR Data In Rise Time 50 50 ns 4 tF Data In Fall Time 50 50 ns 4 tSU Data Setup Time 5 5 ns tH Data Hold Time 5 5 ns tHS /Hold Setup Time 10 10 ns tHH /Hold Hold Time 10 10 ns tHZ /Hold Low to Hi-Z 30 25 ns 3 tLZ /Hold High to Data Active 30 25 ns 3 Notes 1. tCH + tCL = 1/fCK. 2. For Clock High Time tCH ≤ 35 ns, the parameter tODV is extended such that tCH + tODV ≤ 65 ns. 3. This parameter is characterized but not 100% tested. 4. Rise and fall times measured between 10% and 90% of waveform. Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V) Symbol Parameter Min Max Units Notes tPU Power Up (V DD min) to First Access (/CS low) 10 - ms tPD Last Access (/CS high) to Power Down (V DD min) 0 - µs tVR V DD Rise Time 50 - µs/V 1,2 tVF V DD Fall Time 100 - µs/V 1,2 Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V) Symbol Parameter Min Max Units Notes CO Output Capacitance (SO) - 8 pF 1 CI Input Capacitance - 6 pF 1 Notes 1. This parameter is characterized but not 100% tested. 2. Slope measured at any point on VDD waveform. AC Test Conditions Input Pulse Levels 10% and 90% of V DD Input rise and fall times 5 ns Input and output timing levels 0.5 V DD Output Load Capacitance 30 pF

Rev. 2.0 May 2005 Page 10 of 12 Serial Data Bus Timing CS SCK SI SO 1/tCK tCL tCH tCSH tODV tOH tOD tCSU tSU tH tD tRtF /Hold Timing CS SCK SO HOLD tHS tHH tHZ tLZ tHS tHH Power Cycle Timing Data Retention (VDD = 2.7V to 3.6V, + 85° C) Parameter Min Max Units Notes Data Retention 45 - Years

Rev. 2.0 May 2005 Page 11 of 12 Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45° 0.40 1.27 0.19 0.25 0°- 8° Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXX= part number, P= package type LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM25L04, Standard SOIC package, Year 2005, Work Week 16 FM25L04-S A40003S RIC0516 XXXXXXX-P LLLLLLL RICYYWW

Rev. 2.0 May 2005 Page 12 of 12

Revision History

2.0 5/20/05 Pre-Production status.