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2M-BIT SERIAL FLASH MEMORY Datasheet Dec. 2014 Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 1

FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 2 INFORMATION IN THIS DOCUMENT IS INTENDED AS A REFERENCE TO ASSIST OUR CUSTOMERS IN THE SELECTION OF SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD PRODUCT BEST SUITED TO THE CUSTOMER'S APPLICATION; THEY DO NOT CONVEY ANY LICENSE UNDER ANY INTELLECTUAL PROPERTY RIGHTS, OR ANY OTHER RIGHTS, BELONGING TO SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD OR A THIRD PARTY . WHEN USING THE INFORMATION CONTAINED IN THIS DOCUMENTS, PLEASE BE SURE TO EVALUATE ALL INFORMATION AS A TOTAL SYSTEM BEFORE MAKING A FINAL DECISION ON THE APPLICABILITY OF THE INFORMATION AND PRODUCTS. PURCHASERS ARE SOLELY RESPONSIBLE FOR THE CHOICE, SELECTION AND USE OF THE SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD PRODUCTS AND SE RVICES DESCRIBED HEREIN, AND SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD ASSUMES NO LIABILITY WHATSOEVER RELATING TO THE CHOICE, SELECTION OR USE OF THE SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD PRODUCTS AND SERVICES DESCRIBED HEREIN. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD REPRESENTATIVE, SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. FUTURE ROUTINE REVISIONS WILL OCCUR WHEN APPROPRIATE, WITHOUT NOTICE. CONTACT SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD SALES OFFICE TO OBTAIN THE LATEST SPECIFICATIONS AND BEFORE PLACING YOUR PRODUCT ORDER. PLEASE ALSO PAY ATTENTION TO INFORMATION PUBLISHED BY SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD BY VARIOUS MEAN S, INCLUDING SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD HOME PAGE (HTTP://WWW.FMSH.COM/). PLEASE CONTACT SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD LOCAL SALES OFFICE FOR THE SPECIFICATION REGARDING THE INFORMATION IN THIS DOCUMENT OR SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD PRODUCTS. Trademarks Shanghai Fudan Microelectronics Group Co., Ltd name and logo, the “ 复旦” logo are trademarks or registered trademarks of Shanghai Fudan Microelectronics Group Co., Ltd or its subsidiaries in China. Shanghai Fudan Microelectronics Group Co., Ltd, Printed in the China, All Rights Reserved.

  1. Description The FM25F02A is a 2M-bit (256K-byte) Serial Flash memory, with advanced write protection mechanisms. The FM25F02A supports the standard Serial Peripheral Interface (SPI), and a high performance Dual output as well as Dual I/O. The FM25F02A can be programmed 1 to 256 bytes at a time, using the Page Program instruction. It is designed to allow either single Sector/Block at a time or full chip erase operation. The FM25F02A can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector or block. 2. Features z 2Mbit of Flash memory – 64 uniform sectors with 4K-byte each – 4 uniform blocks with 64K-byte each – 256 bytes per programmable page z Wide Operation Range – 2.3V~3.6V single voltage supply – Industrial temperature range z Serial Interface – Standard SPI: CLK, CS#, DI, DO, WP# – Dual SPI: CLK, CS#, DQ0, DQ1, WP# – Continuous READ mode support z High Performance – Max FAST_READ clock frequency: 100MHz – Max READ clock frequency: 66MHz – Typical page program time: 1.5ms – Typical sector erase time: 90ms – Typical block erase time: 500ms – Typical chip erase time: 1.8s z Low Power Consumption – Typical standby current: 1μA z Security – Software and hardware write protection – Lockable 256-Byte OTP security sectors – Low Voltage Write Inhibit – 64-Bit Unique ID for each device z High Reliability – Endurance: 100,000 prog ram/erase cycles – Data retention: 20 years z Green Package – 8-pin SOP (150mil) – 8-pin SOP (208mil) – 8-pin TSSOP – 8-pad TDFN (2×3mm) – All Packages are RoHS Compliant and Halogen- free 3. Packaging Type 4. Pin Configurations PIN NO. PIN NAME I/O FUNCTION

1 CS# I Chip Select Input

(DQ1) I/O Data Output (Data Input Output 1)(1)

3 WP# I Write Protect Input

4 VSS Ground

(DQ0) I/O Data Input (Data Input Output (1)

6 CLK I Serial Clock Input

7 HOLD# I Hold Input

8 VCC Power Supply

Note: 1 DQ0 and DQ1 are used for Dual SPI instructions. Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 3

  1. Block Diagram Figure 1 FM25F02A Serial Flash Memory Block Diagram Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 4

FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 5 6. Pin Descriptions Serial Clock (CLK): The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. Serial Data Input, Output and I/Os (DI, DO and DQ 0, DQ1): The FM25F02A supports standard SPI and Dual SPI operation. Standard SPI instructi ons use the unidirecti onal DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidi rectional DO (output) to read data or status from the device on the falling edge of CLK. Dual SPI instructions use the bi directional DQ pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Chip Select (CS#): The SPI Chip Select (CS#) pin enabl es and disables device operation. When CS# is high, the device is deselected and the Serial Data Ou tput (DO) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When CS# is brought low, the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted. The CS # input must track the VCC supply level at power-up (see “9 Write Protection” and Figure 26). If needed a pull-up resister on CS# can be used to accomplish this. HOLD (HOLD#): The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high, device operation can resume. The HOLD# function can be useful when multiple devices are sharing the same SPI signals. The HOLD# pin is active low. Write Protect (WP#): The Write Protect (WP#) pin can be us ed to prevent the Status Registers from being written. Used in conjunction with the Status Register’s Block Protect (BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The WP# pin is active low. 7. Memory Organization The FM25F02A array is organized into 1,024 programmable pages of 256-bytes each. Up to 256 bytes can be programmed (bits are programmed from 1 to 0) at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The FM25F02A has 64 erasable sectors and 4 erasable 64-k byte blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. Table 1 Memory Organization Block (64KB) Sector (4KB) Address Range 63 03F000h 03FFFFh … … … 48 030000h 030FFFh 2 47 02F000h 02FFFFh

FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 6 Block (64KB) Sector (4KB) Address Range … … … 32 020000h 020FFFh 31 01F000h 01FFFFh … … … 16 010000h 010FFFh 15 00F000h 00FFFFh … … … 2 002000h 002FFFh 1 001000h 001FFFh 0 000000h 000FFFh

  1. Device Operations 8.1. Standard SPI The FM25F02A is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the nor mal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of CS#. For Mode 3, the CLK signal is normally high on the falling and rising edges of CS#. Figure 2 The difference between Mode 0 and Mode 3 8.2. Dual SPI The FM25F02A supports Dual SPI operation when using instructi ons such as “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flas h devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code- shadowing) or for executing non-speed- critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: DQ 0 and DQ1. 8.3. Hold For Standard SPI operation, the HOLD# signal a llows the FM25F02A operation to be paused while it is actively selected (when CS# is lo w). The HOLD# function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the HOLD# function can save the state of the instructi on and the data in the buffer so programming can resume where it left off once the bus is available again. To initiate a HOLD# condition, the device must be selected with CS# low. A HOLD# condition will activate on the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the HOLD# condition will activate after the next falling edge of CLK. The HOLD# condition will terminate on the rising edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the HOLD# condition will terminate after the next falling edge of CLK. During a HOLD# condition, the Serial Data Out put (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (CS#) signal should be kept Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 7

active (low) for the full duration of the HOLD# operation to avoid resetting the internal logic state of the device. Figure 3 Hold Condition Waveform Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 8

FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 9 9. Write Protection Applications that use non- volatile memory must take into c onsideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the FM25F02A provides several means to protect the data from inadvertent writes. Write Protect Features z Device resets when VCC is below threshold z Time delay write disable after Power-up z Write enable/disable instructions and automatic write dis able after erase or program z Software and Hardware (WP# pin) wr ite protection using Status Register z Write Protection using Power-down instruction z Lock Down write protection for Stat us Register until the next power-up z One Time Program (OTP) write protection fo r array and Security Sectors using Status Register. Upon power-up or at power-down, the FM25F02A will maintain a reset condition while VCC is below the threshold value of VWI, (See “XX 12.3X XPower-up TimingX X” and XX Figure 26X). While reset, all operations are disabled and no in structions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of t PUW. This includes the Write E nable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (CS#) must track the VCC supply level at power-up until the VCC-min level and t VSL time delay is reached. If needed a pull-up resister on CS# can be used to accomplish this. After power-up the device is aut omatically placed in a write-di sabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Blo ck Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled state of 0. Software controlled write protection is facilitated using the Write St atus Register instruction and setting the Status Register Pr otect (SRP) and Block Protect (BP2, BP1 and BP0) bits. These settings allow a portion or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (WP#) pin, ch anges to the Status R egister can be enabled or disabled under hardware control. See Status Register section for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction.

  1. Status Register The Read Status Register instruction can be used to provide status on the availability of the Flash memory array, if the device is write enabled or di sabled, the state of writ e protection, Security Sector lock status. The Write Status Register instruction can be used to configure the device write protection features and Security Sector OTP lo ck. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bit (SRP), the Write Enable instruction, and the WP# pin. Factory default for all Status Register bits are 0. S6 S5S7 S3 S2S4 S1 S0 R RSRP/ LB BP1 BP0BP2 WEL WIP STATUS REGISTER PROTECT / LOCK BIT RESERVED BLOCK PROTECT BITS (non-volatile) WRITE ENABLE LATCH ERASE/WRITE IN PROGRESS Figure 4 Status Register 10.1. WIP Bit WIP is a read only bit in the status register (S 0) that is set to a 1 state when the device is executing a Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register. During this time the device will ignore further inst ructions except for t he Read Status Register (see tW, tPP, tSE, tBE, and tCE in “XX 12.6X XAC Electrical CharacteristicsX X”). When the program, erase or write status register (or security sector) instruction has completed, the WIP bit will be cleared to a 0 state indicating the device is ready for further instructions. 10.2. Write Enable Latch bit (WEL) Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register. 10.3. Block Protect Bits (BP2, BP1, BP0) The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Pr otection control and status. Block Protect bits can be set using Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 10

FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 11 the Write Status Register Instruction (see tW in “XX 12.6X XAC Electrical CharacteristicsX X”). All, none or a portion of the memory array can be protec ted from Program and Erase instructions (see XX Table 2X XStatus Register Memory ProtectionX X). The factory default setting for the Block Protection Bits is 0, none of the array protected. 10.4. Status Register Protect bit / Lock_bit (SRP/LB) The Status Register Protect (S RP) bit is operated in conjunction with the Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected mode (when t he Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volat ile bits of the Status Register (SRP, BP2, BP1, BP0) become read-only bits and the Wr ite Status Register (WRSR) instruction is no longer accepted for execution. In OTP mode, this bit is served as Lock_bit (LB), user can read/program/erase security sector as normal sector while LB value is equal 0, after LB is programmed with 1 by WRSR command, the security sector is protected from program and erase operation. The LB can only be programmed once. Note : In OTP mode, the WRSR command will ignor e any input data and progr am LB to 1, user must clear the protect bits before enter OT P mode and program the OTP code, then execute WRSR command to lock the security sector before leaving OTP mode. 10.5. Status Register Memory Protection Table 2 Status Register Memory Protection Status Register Content Memory Content BP2 bit BP1 bit BP0 bit Protect Areas Address Density (KB) Portion 0 0 0 None None None None 0 0 1 Sector 0-61 000000h-03DFFFh 248KB Lower 62/64 0 1 0 Sector 0-59 000000h-03BFFFh 240KB Lower 60/64 0 1 1 Sector 0-55 000000h-037FFFh 224KB Lower 56/64 1 0 0 Sector 0-47 000000h-02FFFFh 192KB Lower 48/64 1 0 1 Sector 0-31 000000h-01FFFFh 128KB Lower 32/64 1 1 0 All 000000h-03FFFFh 256KB All 1 1 1 All 000000h-03FFFFh 256KB All

FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 12 11. 10BInstructions The Standard SPI instruction set of the FM25F02A consists of 15 basic instructions that are fully controlled through the SPI bus (see XX Table 4X Instruction Set). Instructions are initiated with the falling edge of Chip Select (CS#). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of edge CS#. Cloc k relative timing diagrams for each instruction are included in XX Figure 5 through Figure 25 X. All read instructions can be completed after any clocked bit. However, all instructions that Writ e, Program or Erase must complete on a byte boundary (CS# driven high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further prot ects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the progr am or erase cycle has completed. 11.1. Manufacturer and Device Identification Table 3 Manufacturer and Device Identification OP Code MF7-MF0 ID15-ID0 ID7-ID0 ABh 11h 90h A1h 11h 9Fh A1h 3112h 11.2. Standard SPI Instructions Set Table 4 Standard SPI Instructions Set (1) INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Write Enable 06h Write Disable 04h Read Status Register 05h (S7-S0) (2) Write Status Register 01h (S7-S0) Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3) Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0 Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0 Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0 Chip Erase C7h/60h Power-down B9h Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0) Release Powerdown / ID(4) ABh dummy dummy dummy (ID7-ID0)(2)

FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 13 INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Manufacturer/Device ID(4) 90h dummy dummy 00h (MF7-MF0) (ID7-ID0) JEDEC ID(4) 9Fh (MF7-MF0) Manufacturer (ID15-ID8) Memory Type (ID7-ID0) Capacity Read Unique ID 4Bh dummy dummy dummy dummy (UID63-UID0) Enter OTP mode 3Ah Notes: 1. Data bytes are shifted with Mo st Significant Bit first. Byte fi elds with data in parenthesis “( )” indicate data output from the device on DO pin. 2. The Status Register contents and Device ID will repeat continuously until CS# terminates the instruction. 3. At least one byte of data i nput is required for Page Program and Program Security Sectors, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. 4. See XTable 3X X XManufacturer and Device IdentificationX X table for device ID information. 11.3. Dual SPI Instructions Set Table 5 Dual SPI Instructions Set INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …) (6) Fast Read Dual I/O BBh A23-A8 (5) A7-A0, M7- M0 (5) (D7- D0, …) (6) Notes: 5. Data bytes are shifted with Mo st Significant Bit first. Byte fi elds with data in parenthesis “( )” indicate data output from the device on 1 or 2 DQ pins. 6. The Status Register contents and Device ID will repeat continuously until CS# terminates the instruction. 7. At least one byte of data i nput is required for Page Program and Program Security Sectors, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. 8. See Table 3 Manufacturer and Device Identification table for device ID information. 9. Dual SPI address input format: DQ 0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 DQ1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 10. Dual SPI data output format: DQ0 = (D6, D4, D2, D0) DQ1 = (D7, D5, D3, D1)

11.6. Read Status Register (RDSR) (05h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving CS# low and shifting the inst ruction code “05h” into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in XX Figure 7 X. The Status Register bits are shown in XFigure 4X X and include the WIP, WEL, BP2-BP0 and SRP bits. The Read Status Register instru ction may be used at any time, even while a Program, Erase or Write Status Register cycle is in progress. Th is allows the WIP status bit to be checked to determine when the cycle is complete and if th e device can accept another instruction. The Status Register can be read continuously. The instruction is completed by driving CS# high. Figure 7 Read Status Register Instruction 11.7. Write Status Register (WRSR) (01h) The Write Status Register (WRSR) instruction allows the Status Register to be written. Only non- volatile Status Register bits SRP, BP2, BP1, BP0 can be written to. All ot her Status Register bit locations are read-only and will not be affected by the Write Status Register (WRSR) instruction. The Status Register bits are shown in XX Figure 4X. To write non-volatile Status Register bits , a standard Write Enable (06h) instruction must previously have been executed for the device to accept the Write Status Register (WRSR) instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving CS# low, sending the instruction code “01h”, and then writing the status register data byte as illustrated in XX Figure 8X. To complete the Write Status Register (WRSR) instruction, the CS# pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register (WRSR) instruction will not be executed. During non-volatile Status Register write operat ion (06h combined with 01h), after CS# is driven high, the self-timed Write Stat us Register cycle will commence for a time duration of t W (See “XX 12.6X XAC Electrical CharacteristicsX X”). While the Write Status Register cycle is in progress, the Read Status Register instruction may still be acce ssed to check the status of the WIP bit. The WIP bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After th e Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 15

0 Instruction (0Bh)

CS# CLK 8 9 10 28 29 30 31 24-Bit Address DO =MSB DI High Impedance 23 22 21 3 2 1 0 31 32 33 34 35 36 37 38 Dummy Clocks CS# CLK 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 DO DI High Impedance Data Out 2 7 6 5 4 3 2 1 0 7 7 6 5 4 3 2 1 0 Data Out 1 Figure 10 Fast Read Instruction. 11.10. Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instructi on is similar to the standard Fast Read (0Bh) instruction except that da ta is output on two pins; DQ 0 and DQ 1. This allows data to be transferred from the FM25F02A at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal fo r quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution. Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest possible frequency of F R (see “12.6 AC Electrical Characteristics”). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 11 . The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the DQ 0 pin should be high- impedance prior to the falling edge of the first data out clock. Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 17

Figure 11 Fast Read Dual Output Instruction 11.11. Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two I/O pins, DQ 0 and DQ 1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Addre ss bits A23-A0 two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. Fast Read Dual I/O with “Continuous Read Mode” The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 12. The upper nibble of the (M7-4) c ontrols the length of the next Fa st Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction c ode. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the DQ pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after CS# is raised and then lowered) does not require the BBh instruction code, as shown in Figure 13. This reduces the instruct ion sequence by eight clocks and allows the Read address to be immediately entered after CS# is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is raised and then lowe red) requires the first byte instruction code, thus re turning to normal operation. It is recommended to input FFFFh on DQ 0 for the next instruction (16 clocks), to ens ure M4 = 1 and return the device to normal operation. Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 18

11.12. Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the CS # pin low then shifting the instruction code “02h” followed by a 24-bit address A23-A0 and at least one data byte, into the DI pin. The CS# pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program instruction sequence is shown in XX Figure 14. If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page lengt h, the addressing will increment to the beginning of the next page. To perform a partial page program, the number of clocks can not exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the last byte has been latched. If th is is not done the Page Program instruction will not be executed. After CS# is driven high, the self-timed Page Program instruct ion will commence for a time duration of t PP (See “XX 12.6X XAC Electrical CharacteristicsX X”). While the Page Program cycle is in progress, the Read Status Regist er instruction may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits. Figure 14 Page Program Instruction 11.13. Sector Erase (20h) The Sector Erase instruction sets all memory with in a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruct ion must be executed befor e the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruct ion code “20h” followed a 24-bit sector address A23-A0 (see XX Figure 1X). The Sector Erase instruction sequence is shown in XFigure 15X X . The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 20

done the Sector Erase instruction will not be executed. After CS# is driven high, the self-timed Sector Erase instruction will co mmence for a time duration of t SE (See “ XX 12.6X XAC Electrical Characteristics X X”). While the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the st atus of the WIP bit. Th e WIP bit is a 1 during the Sector Erase cycle and becom es a 0 when the cycle is fini shed and the device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protec ted by the Block Protect (BP2, BP1, and BP0) bits (see XX Table 2X XStatus Register Memory ProtectionX X table). Figure 15 Sector Erase Instruction 11.14. 32KB Block Erase (BE32) (52h) The 32KB Block Erase instruction sets all memory within a specified bl ock (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Regi ster bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code “52h” followed a 24-bit block address A23-A0. The Block Erase instruction sequence is shown in Figure 16. The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After CS# is driven high, the self-timed Block Erase instruction will commence for a time duration of t BE2 (See 12.6 AC Electrical Characteristics”). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of t he WIP bit. The WIP bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is r eady to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruct ion will not be executed if the addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Table 2 Status Register Memory Protection table). Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 21

Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in XX Figure 18 The CS# pin must be driven high after the eighth bi t has been latched. If this is not done the Chip Erase instruction will not be ex ecuted. After CS# is driven hi gh, the self-timed Chip Erase instruction will commence for a time duration of t CE (See HH “HX12.6X XAC Electrical CharacteristicsX X”). While the Chip Erase cycle is in progress, t he Read Status Register instruction may still be accessed to check the status of the WIP bit. Th e WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (BP2, BP1, and BP0) bits. Figure 18 Chip Erase Instruction Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 23

11.17. Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruct ion. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See I CC1 and I CC2 in “XX 12.4X XDC Electrical CharacteristicsX X”). The instruction is initiat ed by driving the CS# pin low and shifting the instruction code “B9h” as shown in XX Figure 19X. The CS# pin must be driven high after the eight h bit has been latched. If this is not done the Power-down instruction will not be executed. After CS# is driven hi gh, the power-down state will enter within the time duration of t DP (See “ XX 12.6X XAC Electrical CharacteristicsX X”). While in the power-down state only the Release from Power- down / Device ID instruction, which restores the device to normal operation, will be recognized. All other instructi ons are ignored. This includes the Read Status Register instru ction, which is always availabl e during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 19 Deep Power-down Instruction 11.18. Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instru ction is a multi-purpose instruction. It can be used to release the device from the power-d own state, or obtain the devices electronic identification (ID) number. To release the device from the pow er-down state, the instruction is issued by driving the CS# pin low, shifting the instruction code “ ABh” and driving CS# high as shown in XX Figure 20 X. Release from power-down will take the time duration of t RES1 (See “X12.6X X XX AC Electrical Characteristics X”) before the device will resume normal operation and ot her instructions are accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in XX Figure 21X. The Device ID value for the FM25F02A is listed in XTable 3X X XX Manufacturer and Devi ce Identification X table. The Device ID c an be read continuously. The instruction is completed by driving CS# high. When used to release the devic e from the power-down state and obtain the Device ID, the instruction is the same as pr eviously described, and shown in XX Figure 21, except that after CS# is Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 24

CS# CLK Instruction (90h) 0 1 2 3 4 5 6 7 Mode 3 Mode 0 8 9 10 Address (000000h) 28 29 30 31 23 22 21 3 2 1 0 =MSB High Impedance 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 7 6 5 4 3 2 1 0 Device ID Mode 3 Mode 0 Manufacturer ID CS# CLK DO DI 7 6 5 4 3 2 1 0 Figure 22 Read Manufacturer / Device ID Instruction 11.20. Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each FM25F02A device. T he ID number can be used in c onjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the CS# pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks. After which, the 64- bit ID is shifted out on the falling edge of CLK as shown in Figure 23. Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 26

CS# CLK (DQ1) DI (DQ0) 63 62 61 2 1 0 High Impedance =MSB 64-bit Unique Serial Number 31 32 33 34 35 36 37 38 39 40 41 4223 24 25 26 27 28 29 30 Mode 3 Mode 0 100 101 102 Dummy Byte 3 Dummy Byte 4 CS# CLK (DQ1) DI (DQ0) Instruction (4Bh) 0 1 2 3 4 5 6 7 Mode 3 Mode 0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Dummy Byte 1 Dummy Byte 2 High Impedance Figure 23 Read Unique ID Number Instruction (SPI Mode only) 11.21. Read JEDEC ID (9Fh) For compatibility reasons, the FM25F02A provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memori es. The instruction is initiated by driving the CS# pin low and shifting the instruction code “9Fh”. The JE DEC assigned Manufacturer ID byte for Shanghai Fudan Microelectronics Group Co., Ltd (A1h) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity ID7-ID0 are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in XX Figure 24 . For memory type and capacity values refer to XTable 3X X Manufacturer and Device Identification table. Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 27

Figure 24 Read JEDEC ID Instruction 11.22. Enter OTP Mode (3Ah) This Flash has an extra 256 bytes security sector, user must issue ENTER OTP MODE command to read, program or erase security sector. After entering OTP mode, the security sector is mapping to sector 63, SRP bit becomes LB and can be read with RDSR command. Program / Erase command will be disabled when LB is ‘1’ WRSR command will ignore the input data and program LB to 1. User must clear the protect bits before enter OTP mode. Security sector can only be program and erase when LB equal ‘0’ and BP[2:0] = ‘000’. In OTP mode, user can read other sectors, but program/erase other sectors only allowed when LB equal ‘0’. User can use WRDI (04h) command to exit OTP mode. Table 5 Security Sector Adress Sector Sector Size Adress Range 63 256 byte 03F000h – 03F0FFh Note: The Secruty sector is mapping to sector 63 While in OTP mode, user can use Sector Erase (20h) command only to erase OTP data. Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 28

Instruction (3Ah) CLK DI CS# DO HIGH IMPEDANCE Figure 25 Enter OTP mode Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 29

  1. Electrical Characteristics 12.1. Absolute Maximum Ratings Operating Temperature -40°C to +85°C Storage Temperature -65°C to +150°C Voltage on I/O Pin with Respect to Ground -0.5V to VCC+0.4V VCC -0.5V to 4.0V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any ot her conditions beyond those indicated in the operational sections of this sp ecification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 12.2. Pin Capacitance PARAMETER SYMBOL CONDITIONS Max Units Input Capacitance CIN (1) V IN = 0V, f = 5 MHz 6 pF Output Capacitance COUT (1) V OUT = 0V, f = 5 MHz 8 pF Note: 1. This parameter is characterized and is not 100% tested. 12.3. Power-up Timing Applicable over recommended operating range from: TA = -40°C to 85°C, VCC = 2.3V to 3.6V, (unless otherwise noted). PARAMETER SYMBOL SPEC UNIT MIN MAX VCC (min) to CS# Low tVSL 10 µs Time Delay Before Write Instruction tPUW 1 10 ms Figure 26 Power-up Timing Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 30

FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 31 12.4. DC Electrical Characteristics Table 6 DC Characteristics Applicable over recommended operating range from: TA = -40°C to 85°C, VCC = 2.3V to 3.6V, (unless otherwise noted). SYMBOL PARAMETER CONDITIONS SPEC UNITMIN TYP MAX Vcc Supply Voltage 2.3 3.6 V ILI Input Leakage Current ±2 µA ILO Output Leakage Current ±2 µA ICC1 Standby Current VCC=3.6V, CS# = VCC, VIN = Vss or VCC 1 5 µA ICC2 Deep Power-down Current VCC=3.6V, CS# = VCC, VIN = Vss or VCC 1 5 µA ICC3 Operating Current (READ) VCC=3.6V,CLK=0.1VCC/0. 9VCC, at 100MHz, DO open 25 mA ICC4 Operating Current (WRSR)) VCC=3.6V,CS#=VCC 8 12 mA ICC5 Operating Current (PP) VCC=3.6V,CS#=VCC 20 25 mA ICC6 Operating Current (SE) VCC=3.6V,CS#=VCC 20 25 mA ICC7 Operating Current (BE) VCC=3.6V,CS#=VCC 20 25 mA VIL (1) Input Low Voltage -0.5 0.2VCC V VIH (1) Input High Voltage 0.7VCC VCC+0.4 V VOL Output Low Voltage IOL = 1.6 mA 0.4 V VOH Output High Voltage IOH = -100 µA VCC-0.2 V VWI Write Inhibit Threshold Voltage 1.0 2.2 V Notes: 1. V IL min and VIH max are reference only and are not tested.

12.5. AC Measurement Conditions Table 7 AC Measurement Conditions SYMBOL PARAMETER SPEC UNIT MIN MAX CL Load Capacitance 20 pF TR, TF Input Rise and Fall Times 5 ns VIN Input Pulse Voltages 0.2 VCC to 0.8 VCC V IN Input Timing Reference Voltages 0.3 VCC to 0.7 VCC V OUT Output Timing Reference Voltages 0.5VCC V Input Levels

0.8 Vcc

0.2 Vcc

0.7 Vcc

0.3 Vcc

Input Timing Reference Level

0.5 Vcc

Output Timing Reference Level AC Measurement Level Figure 27 AC Measurement I/O Waveform 12.6. AC Electrical Characteristics Table 8 AC Characteristics Applicable over recommended operating range from: TA = -40°C to 85°C, VCC = 2.7V to 3.6V, (unless otherwise noted). SYMBOL PARAMETER SPEC UNIT MIN TYP MAX FR Serial Clock Frequency for: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, WRSR

100 MHz

fR Serial Clock Frequency for READ, RDSR, RDID 66 MHz tCH (1) Serial Clock High Time 4 ns tCL (1) Serial Clock Low Time 4 ns tCLCH (2) Serial Clock Rise Time (Slew Rate) 0.1 V/ns tCHCL (2) Serial Clock Fall Time (Slew Rate) 0.1 V/ns tSLCH CS# Active Setup Time 5 ns tCHSH CS# Active Hold Time 5 ns tSHCH CS# Not Active Setup Time 5 ns tCHSL CS# Not Active Hold Time 5 ns tSHSL CS# High Time (for Array Read Æ Array Read) 100 ns tSHQZ (2) Output Disable Time 6 ns tCLQX Output Hold Time 0 ns tDVCH Data In Setup Time 2 ns tCHDX Data In Hold Time 5 ns tHLCH HOLD# Low Setup Time ( relative to CLK ) 5 ns tHHCH HOLD# High Setup Time ( relative to CLK ) 5 ns Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 32

FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 33 SYMBOL PARAMETER SPEC UNIT MIN TYP MAX tCHHH HOLD# Low Hold Time ( relative to CLK ) 5 ns tCHHL HOLD# High Hold Time ( relative to CLK ) 5 ns tHLQZ (2) HOLD# Low to High-Z Output 6 ns tHHQX (2) HOLD# High to Low-Z Output 6 ns tCLQV Output Valid from CLK 8 ns tWHSL Write Protect Setup Time before CS# Low 20 ns tSHWL Write Protect Hold Time after CS# High 100 ns tDP (2) CS# High to Deep Power-down Mode 3 µs tRES1 (2) CS# High to Standby Mode without Electronic Signature Read 3 µs tRES2 (2) CS# High to Standby Mode with Electronic Signature Read 1.8 µs tW Write Status Register Cycle Time 10 15 ms tPP Page Programming Time 1.5 5 ms tSE Sector Erase Time 0.09 0.3 s tBE1 Block Erase Time (64KB) 0.5 2 s tBE2 Block Erase Time (32KB) 0.3 1.2 s tCE Chip Erase Time 1.8 5 s Notes: 1. t CH+tCL >= 1 / FR or 1/fR ; 2. This parameter is charac terized and is not 100% tested. Applicable over recommended operating range from: TA = -40°C to 85°C, VCC = 2.3V to 2.7V, (unless otherwise noted). SYMBOL PARAMETER SPEC UNIT MIN TYP MAX FR Serial Clock Frequency for: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, WRSR

80 MHz

fR Serial Clock Frequency for READ, RDSR, RDID 33 MHz tPP Page Programming Time 6 15 ms tSE Sector Erase Time 0.15 0.65 s tBE1 Block Erase Time (64KB) 1.4 3 s tBE2 Block Erase Time (32KB) 0.8 2 s tCE Chip Erase Time 5 15 s

  1. Ordering Information Company Prefix Product Family Product Density Package Type (1) FM = Fudan Microelectronics Group Co.,ltd 25F = 2.7~ 3.6V Serial Flash Memory with 4KB Uniform-Sector, Standard / Dual SPI 02 = 2M-bit SO = 8-pin SOP（150mil） SOB = 8-pin SOP（208mil） TS = 8-pin TSSOP DN = 8-pin TDFN (2x3mm) (2) FM 02 -XXX HSF ID Code G = RoHS Compliant, Halogen-free, Antimony-free Product Carrier U = Tube T = Tape and Reel 25F -HA Product Version Note: 1. For SO, TS and DN package, MSL1 package are available, for detail please contact local sales office. 2. For Thinner package please contact local sales office. Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 35
  1. Part Marking Scheme 14.1. SOP8 (150mil) 14.2. SOP8 (208mil) Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 36 14.3. TSSOP8

14.4. TDFN8 (2x3mm) Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 37

  1. Packaging Information SOP 8 (150mil) Symbol MIN MAX A 1.350 1.750 A1 0.050 0.250 b 0.330 0.510 c 0.150 0.250 D 4.700 5.150 E1 3.800 4.000 E 5.800 6.200 e 1.270(BSC) L 0.400 1.270 θ 0° 8° NOTE: 1. Dimensions are in Millimeters. Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 38

SOP 8 (208mil) Symbol MIN MAX A – – 2.100 A1 0.050 0.250 b 0.350 0.500 c 0.100 0.250 D 5.130 5.330 E1 5.180 5.380 E 7.700 8.100 e 1.270(BSC) L 0.500 0.850 θ 0° 8° NOTE: 1. Dimensions are in Millimeters. Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 39

D 2.900 3.100 E1 4.300 4.500 b 0.190 0.300 c 0.090 0.200 E 6.250 6.550 A 1.200 A1 0.050 0.150 e 0.650 (BSC) L 0.450 0.750 θ 0° 8° NOTE: 1. Dimensions are in Millimeters. Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 40

TDFN8 (2x3mm) Symbol MIN MAX A 0.700 0.800 A1 0.000 0.050 D 1.900 2.100 E 2.900 3.100 D2 1.400 1.600 E2 1.400 1.600 k 0.200(MIN) b 0.200 0.300 e 0.500(TYP) L 0.200 0.400 NOTE: 1. Dimensions are in Millimeters. Datasheet FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 41

FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 42 16. Revision History Version Publication date Pages Revise Description 1.0 May. 2013 43 First Official Release 1.1 Aug. 2013 43 Corrected the typo 1.2 Sep. 2014 43 Updated the DC Electrical Characteristics 1.3 Dec. 2014 43 Updated the Ordering Information and Part Marking Scheme.

FM25F02A 2M-BIT SERIAL FLASH MEMORY Ver 1.3 43 Sales and Service Shanghai Fudan Microelectronics Group Co., Ltd. Address: Bldg No. 4, 127 Guotai Rd, Shanghai City China. Postcode: 200433 Tel: (86-021) 6565 5050 Fax: (86-021) 6565 9115 Shanghai Fudan Microelectronics (HK) Co., Ltd. Address: Unit 506, 5/F., East Ocean Centre, 98 Granville Road, Tsimshatsui East, Kowloon, Hong Kong Tel: (852) 2116 3288 2116 3338 Fax: (852) 2116 0882 Beijing Office Address: Room 423, Bldg B, Gehua Building,

1 QingLong Hutong, Dongzhimen Alley north Street,

Dongcheng District, Beijing City, China. Postcode: 100007 Tel: (86-010) 8418 6608 Fax: (86-010) 8418 6211 Shenzhen Office Address: Room.1301, Century Bldg, No. 4002, Shengtingyuan Hotel, Huaqiang Rd (North), Shenzhen City, China. Postcode: 518028 Tel: (86-0755) 8335 0911 8335 1011 8335 2011 8335 0611 Fax: (86-0755) 8335 9011 Shanghai Fudan Microelectronics (HK) Ltd Taiwan Representative Office Address: Unit 1225, 12F., No 252, Sec.1 Neihu Rd., Neihu Dist., Taipei City 114, Taiwan Tel : (886-2) 7721 1889 Fax: (886-2) 7722 3888 Shanghai Fudan Microelectronics (HK) Ltd Singapore Representative Office Address : 237, Alexandra Road, #07-01 The Alexcier, Singapore 159929 Tel : (65) 6472 3688 Fax: (65) 6472 3669 Shanghai Fudan Microelectronics Group Co., Ltd NA Office Address :2490 W. Ray Road Suite#2 Chandler, AZ 85224 USA Tel : (480) 857-6500 ext 18 Web Site: http://www.fmsh.com/