FM25160

FM25160 ETC | Alldatasheet

Document overview

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Technical content

Features

16K bit Ferroelectric Nonvolatile RAM

• Organized as 2,048 x 8 bits
• High endurance 10 Billion (10 10 ) read/writes
• 10 year data retention at 85 ° C
• NoDelay™ write
• Advanced high - reliability fe rroelectric process Fast Serial Peripheral Interface - SPI
• Up to 2.1 MHz maximum bus frequency
• Direct hardware replacement for EEPROM
• Supports SPI Mode 0 (CPOL=0, CPHA=0) Sophisticated Write Protection Scheme
• Hardware protection
• Software protection L ow Power Consumption
• 10 µA standby current Industry Standard Configuration
• Industrial temperature - 40 ° C to +85 ° C
• 8 - pin SOP or DIP

Description

The FM25160 is a 16 - kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric ra ndom access memory or FRAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile m emories. Unlike serial EEPROMs, the FM25160 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array mere hundreds of nanoseconds after it has been successfully transferred to the device. The next bus cycl e may c7ommence immediately. In addition, the product offers substantial write endurance compared with other nonvolatile memories. The FM25160 is capable of supporting up to 1E10 read/write cycles -- far more than most systems will require from a serial me mory. These capabilities make the FM25160 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the lon g write time of EEPROM can cause data loss. The FM25160 provides substantial benefits to users of serial EEPROM, in a hardware drop - in replacement. The FM25160 uses the high - speed SPI bus, which enhances the high - speed write capability of FRAM technology . It is guaranteed over an industrial temperature range of - 40°C to +85°C. Pin Configuration CS SO WP VSS VCC HOLD SCK SI Pin Names Function /CS Chip Select SO Serial Data Output /WP Write Protect VSS Ground SI Serial Data Input SCK Serial Cloc k /HOLD Hold VCC Supply Voltage 5V

Ordering Information

FM25160 - P 8 - pin plastic DIP FM25160 - S 8 - pin SOP

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Figure 1. Block Diagram

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Pin Name Pin Number I/O Pin Description /CS 1 I Chip Select. Activates t he device. When high, all outputs are tri - state and the device ignores other inputs. The part remains in a low power standby mode. When low, the part recognizes activity on the SCK signal. A falling edge on /CS must occur prior to every op - code. SO 2 O S erial Output. SO is the data output pin. It is driven actively during a read and remains tri - state at all other times including when HOLD \\ is low. Data transitions are driven on the falling edge of the serial clock. * SO can be connected to SI for a singl e pin data interface since the part communicates in half - duplex. /WP 3 I Write Protect. This pin prevents write operations to the status register. This is critical since many other write protection features are controlled through the status register. A complete explanation of write protection is provided below. *Note that the function of /WP is different from the FM25040 where it prevent all writes to the part. VSS 4 I Ground SI 5 I Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet ICC specifications. * SI may be connected to SO for a single pin data interface. SCK 6 I Serial Clock. All I/O activity is synchron ized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. The part is static so the clock frequency may be any value between 0 and 2.1 MHz and may be interrupted at any time. /HOLD 7 I Hold. The /HOLD signal i s used when the host CPU must interrupt a memory operation for another task. Taking the /HOLD signal to a low state pauses the current operation. The part ignores any transition on SCK or /CS. All transitions on /HOLD must occur while SCK is low. VCC 8 I Supply Voltage. 5V Overview The FM25160 is a serial FRAM memory. The memory array is logically organized as 2,048 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to se rial EEPROMs. The major difference between the FM25160 and a serial EEPROM with the same pin - out relates to its superior write performance. Memory Architecture When accessing the FM25160, the user addresses 2,048 locations each with 8 data bits. These dat a bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op - code including a page address, and a word address. The word address consists of 8 - bits that specify one of 256 addresses. The page address is 3 - bits and so there are 8 pages each of 256 locations. The complete address of 11 - bits specifies each byte address uniquely. Most functions of the FM25160 are either controlled by the SPI interface or are handle d automatically by on - board circuitry. The access time for memory operation essentially is zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to po ll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section below. Users expec t several obvious system benefits from the FM25160 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast - write operation is less susceptibl e to corruption than an EEPROM since it is completed quickly. By contrast an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25160 contains no power management circuits other than a simple internal

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FM25160 operates in SPI Mode 0 only. addresses and data are then transferred. Figure 2. System Configuration with SPI port Figure 3. System Configuration without SPI port

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single function such as to enable a write operation. address and one or more bytes of data. Table 1. Op - code Commands The FM25160 will power up with writes disabled. register, called WEL, ind icates the state of the latch. WEL=1 indicates that writes are permitted. WREN command bus configuration. Figure 4. WREN Bus Configuration Figure 5. WRDI Bus Configuration

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described in detail in a later section. command, the /WP pin must be high or inactive. writing to the Status register, not the memory array. Status register is organized as follows. Table 2. Status Register Bits 0 and 4 - 6 are fixed at 0 and can not be modified. flag indicates the state of the Write Enable Latch. protected as shown in the following table. Figure 6. RDSR Bus Configuration Figure 7. WRSR Bus Configuration

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Table 3. Block Memory Write Protection protect inadvertent changes to the block protect bits. register is write protected if WPEN=1 and /WP=0. write protection conditions. Table 4. Write Protection

0 X X Protected Protected Protected

sequential writes may be performed. counter will roll over to 000h. Data is read MSB first. but the SCK pin can toggle during a hold state.

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Data Retention and Endurance Data retention is specified in the electrical specifications below. For purposes of clarity, this section contrasts the retention and endurance of FRAM with EEPROM. The retention performance of FRAM is very comparable to EEPROM in its characteristics. However, the effe ct of endurance cycles on retention is different. A typical EEPROM has a write endurance specification that is fixed. Surpassing the specified level of cycles on an EEPROM usually leads to a hard memory failure. By contrast, the effect of increasing cycl es on FRAM produces an increase in the soft error rate. That is, there is a higher likelihood of data loss but the memory continues to function properly. A hard failure would not occur by simply exceeding the endurance specification; simply a reduction in data retention reliability. While enough cycles would cause an apparent hard error, this is simply a very high soft error rate. This characteristic makes it problematic to assign a fixed endurance specification. Endurance is a soft specification. Therefo re, the user may operate the device with different levels of endurance cycling for different portions of the memory. For example, critical data needing the highest reliability level could be stored in memory locations that receive comparatively few cycles. Data with shorter - term use could be located in an area receiving many more cycles. A scratchpad area, needing little if any retention can be cycled until there is virtually no retention capability remaining. This would occur several orders of magnitude ab ove the endurance spec. Internally, a FRAM operates with a read and restore mechanism similar to a DRAM. Therefore, endurance cycles are applied for each access: read or write. The FRAM architecture is based on an array of rows and columns. Each access c auses a cycle for an entire row. Therefore, data locations targeted for substantially differing numbers of cycles should not be located within the same row. In the FM25160, there are 256 rows each 64 bits wide. Each 8 bytes in the address mark the beginni ng of a new row. Figure 8 Memory Write Figure 9 Memory Read

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Applications

The versatility of FRAM technology fits into many diverse applications. Clearly the strength of higher write endurance and faster writes make FRAM superior to EEPROM in all but one - time programmable applications. The advan tage is most obvious in data collection environments where writes are frequent and data must be nonvolatile. The attributes of fast writes and high write endurance combine in many innovative ways. A short list of ideas is provided here. 1. Data collection . In applications where data is collected and saved, FRAM provides a superior alternative to other solutions. It is more cost effective than battery backup for SRAM and provides better write attributes than EEPROM. 2. Configuration . Any nonvolatile memory ca n retain a configuration. However if the configuration changes and power failure is a possibility, the higher write endurance of FRAM allows changes to be recorded without restriction. Any time the system state is altered, the change can be written. This a voids writing to memory on power down when the available time is short and power scarce. 3. High noise environments . Writing to EEPROM in a noisy environment can be challenging. When severe noise or power fluctuations are present, the long write time of EEPR OM creates a window of vulnerability during which the write can be corrupted. The fast write of FRAM is complete within a microsecond. This time is typically too short for noise or power fluctuation to disturb it. 4. Time to market . In a complex system, mult iple software routines may need to access the nonvolatile memory. In this environment the time delay associated with programming EEPROM adds undue complexity to the software development. Each software routine must wait for complete programming before allow ing access to the next routine. When time to market is critical, FRAM can eliminate this simple obstacle. As soon as a write is issued to the FM25160, it is effectively done -- no waiting. 5. RF/ID . In the area of contactless memory, FRAM provides an ideal s olution. Since RF/ID memory is powered by an RF field, the long programming time and high current consumption needed to write EEPROM is unattractive. FRAM provides a superior solution. The FM25160 is suitable for multi - chip RF/ID products. 6. Maintenance tra cking . In sophisticated systems, the operating history and system state during a failure is important knowledge. Maintenance can be expedited when this information has been recorded. Due to the high write endurance, FRAM makes an ideal system log. In addit ion, the convenient 2 - wire interface of the FM25160 allows memory to be distributed throughout the system using minimal additional resources.

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Ambient storage or operating te mperature - 40 °C to + 85 °C Voltage on any pin with respect to ground - 1.0V to +7.0V D.C. output current on any pin 5 mA Lead temperature (Soldering, 10 seconds) 300 ° C Stresses above those listed under Absolute Maximum Ratings may cause permanent da mage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings condition s for extended periods may affect device reliability DC Operating Conditions TA = - 40 ° C to + 85 ° C, VCC = 4.5V to 5.5V unless otherwise specified Symbol Parameter Min Typ Max Units Notes VCC Main Power Supply 4.5 5.0 5.5 V 1 ICC VCC Supply Current @ SCK = 1.0 MHz 0.9 1.2 mA 2 ICC VCC Supply Current @ SCK = 2.1 MHz 1.6 2.5 mA 2 ISB Standby Current 1 10 µA 3 ILI Input Leakage Current 10 µA 4 ILO Output Leakage Current 10 µA 4 VIL Input Low Voltage - 0.3 VCC x 0.3 V 1 VIH Input High Volt age VCC x 0.7 VCC + 0.5 V 1 VOL Output Low Voltage @ IOL = 2 mA

0.4 V 1

@ IOH = - 1 mA VCC - 0.8 V 1 VHYS Input Hysteresis VCC x .05 V 1, 5 Notes 1. Referenced to VSS. 2. SCK toggling between VCC - 0.3V and VSS, other inputs VSS or VCC - 0.3V 3. SCK = SI = /CS=VCC. All inputs VSS or VCC. 4. VIN or VOUT = VSS to VCC 5. This parameter is periodically sampled and not 100% tested.

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AC Parameters TA = - 40 ° C to + 85 ° C, VCC = 4.5V to 5.5V unless otherwise specified Symbol Parameter Min Max Un its fCK SCK Clock Frequency 0 2.1 MHz tCH Clock High Time 200 ns tCL Clock Low Time 200 ns tCSU Chip Select Setup 240 ns tCSH Chip Select Hold 240 ns tOD Output Disable 240 ns tODV Output Data Valid 200 ns tOH Output Hold 0 ns tD Deselect Time 240 ns tR Data Rise Time 2.0 µS tF Data Fall Time 2.0 µS tH Data Hold Time 100 ns tSU Data Setup Time 100 ns tHS /Hold Setup Time 90 ns tHH /Hold Hold Time 90 ns tHZ /Hold Low to Hi - Z 100 ns tLZ /Hold High to Data Active 100 ns Note s 1. Rise and fall times measured between 10% and 90% of waveform. Capacitance TA = 25 ° C , f=1.0 MHz, VCC = 5V Symbol Parameter Max Units Notes CO Output capacitance (SDA) 8 pF 1 CI Input capacitance 6 pF 1 Notes 1. This parameter is periodically sample d and not 100% tested. AC Test Conditions Input Pulse Levels VCC * 0.1 to VCC * 0.9 Input rise and fall times 10 ns Input and output timing levels VCC*0.5 Equivalent AC Load Circuit

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Data Retention TA = - 40 ° C to + 85 ° C, VCC = 4.5V to 5.5V unless otherwise specified Parameter Min Units Notes Data Retention 10 Years 1 Notes 1. Data retention is specified at 85 ° C. The relationship between retention, temperature, and the associated reliability level is characterized separately. Serial Data Bus Timing /Hold Timing

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8 - pin SOP JEDEC MS - 012 Pin 1 Index Area E H D A B e .10 mm .004 in. a h 45 ° L C Selected Dimensions Refer to JEDEC MS - 012 for complete dimensions and notes. Controlling dimensions is in millimeters. Conversions to inches are not exa ct. Symbol Dim Min Nom. Max A mm in. 1.35 .053 1.75 .069 A1 mm in. .10 .004 .25 .010 B mm in. .33 .013 .51 .020 C mm in. .19 .007 .25 .010 D mm in. 4.80 .189 5.00 .197 E mm in. 3.80 .150 4.00 .157 e mm in.

1.27 BSC

.050 BSC H mm in. 5.80 .228 6.20 .244 h mm in. .25 .010 .50 .197 L mm in. .40 .016 1.27 .050 α 0 ° 8 °

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8 - pin DIP JEDEC MS - 001 Index Area D A1 eD1 b A2 A eA eB E Selected Dimensions Refer to JEDEC MS - 001 for complete dimensions and notes. Controlling dimensions is in inches. Conversions to millimeters are not exact. Symbol Dim Min Nom. Max A in. mm .210 5.33 A1 in. mm 0.015 .381 A2 in. mm 0.1 15 2.92 0.130 3.30 0.195 4.95 b in. mm 0.014 .356 0.018 .457 0.022 .508 D in. mm 0.355 9.02 0.365 9.27 0.400 10.2 D1 in. mm 0.005 .127 E in. mm 0.300 7.62 0.310 7.87 0.325 8.26 E1 in. mm 0.240 6.10 0.250 6.35 0.280 7.11 e in. mm .100 BSC

2.54 BSC

eA in. mm .300 BSC

7.62 BSC

eB in. mm 0.430 10.92 L in. mm 0.115 2.92 0.130 3.30 0.150 3.81