FM24CL64

FM24CL64 ETC | Alldatasheet

Document overview

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• PDF pages: 13

Technical content

Features

64K bit Ferroelectric Nonvolatile RAM

• Organized as 8,192 x 8 bits
• Unlimited Read/Write Cycles
• 10 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface
• Up to 1 MHz maximum bus frequency
• Direct hardware replacement for EEPROM
• Supports legacy timing for 100 kHz & 400 kHz Low Power Operation
• True 2.7V-3.6V Operation
• 75 µA Active Current (100 kHz)
• 1 µA Standby Current Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin SOIC

Description

The FM24CL64 is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM24CL64 performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. In addition, the product offers write endurance orders of magnitude higher than EEPROM. Also, FRAM exhibits much lower power during writes than EEPROM since write operations do not require an internally elevated power supply voltage for write circuits. These capabilities make the FM24CL64 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system. The FM24CL64 provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The FM24CL64 is provided in industry standard 8-pin surface mount package using a familiar two-wire protocol. It is guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration VSS VDD WP SCL SDA Pin Names Function A0-A2 Device Select Address SDA Serial Data/address SCL Serial Clock WP Write Protect VSS Ground VDD Supply Voltage

Ordering Information

Figure 1. FM24CL64 Block Diagram open-drain and is intended to be wire-OR’d with other devices on the two-wire bus. driver includes slope control for falling edges. A pull-up resistor is required. incorporates a Schmitt trigger input for noise immunity.

zero beyond the time needed for the serial protocol. more detail in the interface section below. vulnerable to noise during much of the cycle. users but is described in this section. device on the bus that is being controlled is a slave. The FM24CL64 always is a slave device. Figure 2. Typical System Configuration

1010 A 2 A 1 A 0 R / W

Figure 4. Slave Address beginning a write operation as explained below. data transfer occurs MSB (most significant bit) first. counter will wrap from 1FFFh to 0000h. will always return a ready condition.

Rev 2.0 July 2003 Page 8 of 13 complexity to the software development. Each software routine must wait for complete programming before allowing access to the next routine. 5. RF/ID . In the area of contactless memory, FRAM provides an ideal solution. Since RF/ID memory is powered by an RF field, the long programming time and high current consumption needed to write EEPROM is unattractive. FRAM provides a superior solution. The FM24CL64 is suitable for multi-chip RF/ID products. 6. Maintenance tracking . In sophisticated systems, the operating history and system state during a failure is important knowledge. Maintenance can be expedited when this information has been recorded. Due to the high write endurance, FRAM makes an ideal system log. In addition, the convenient 2-wire interface of the FM24CL64 allows memory to be distributed throughout the system using minimal additional resources.

Rev 2.0 July 2003 Page 9 of 13 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +5.0V VIN Voltage on any pin with respect to V SS -1.0V to +5.0V and VIN < VDD+1.0V TSTG Storage Temperature -55°C to +125°C TLEAD Lead Temperature (Soldering, 10 seconds) 300° C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD =2.7V to 3.65V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 2.7 3.65 V IDD VDD Supply Current @ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 150 400 µA µA µA ISB Standby Current 1 µA 2 ILI Input Leakage Current 10 µA 3 ILO Output Leakage Current 10 µA 3 VIL Input Low Voltage -0.3 0.3 V DD V 4 VIH Input High Voltage 0.7 V DD V DD + 0.5 V 4 VOL Output Low Voltage @ IOL = 3.0 mA 0.4 V RIN Address Input Resistance (WP, A2-A0) For VIN = VIL (max) For VIN = VIH (min) KΩ MΩ VHYS Input Hysteresis 0.05 V DD V 4 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to pins with pull down resistors. 4. This parameter is characterized but not tested. 5. The input pull-down circuit is strong (50KΩ ) when the input voltage is below VIL and weak (1MΩ ) when the input voltage is above VIH.

Rev 2.0 July 2003 Page 10 of 13 AC Parameters (TA = -40° C to + 85° C, VDD =2.7V to 3.65V unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz 1 tLOW Clock Low Period 4.7 1.3 0.6 µs tHIGH Clock High Period 4.0 0.6 0.4 µs tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs tBUF Bus Free Before New Transmission 4.7 1.3 0.5 µs tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 µs tHD:DAT Data In Hold 0 0 0 ns tSU:DAT Data In Setup 250 100 100 ns tR Input Rise Time 1000 300 300 ns 2 tF Input Fall Time 300 300 100 ns 2 tSU:STO Stop Condition Setup 4.0 0.6 0.25 µs tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to 1 MHz. 2 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3V) Symbol Parameter Max Units Notes CI/O Input/output capacitance (SDA) 8 pF 1 CIN Input capacitance 6 pF 1 Notes 1 This parameter is periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels 0.1 V DD to 0.9 VDD Input rise and fall times 10 ns Input and output timing levels 0.5 V DD Equivalent AC Load Circuit 3.65V Output 1100 Ω 100 pF

Rev 2.0 July 2003 Page 11 of 13 Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing tSU:SDA Start tR tF Stop Start tBUF tHIGH 1/fSCL tLOW tSP tSP Acknowledge tHD:DAT tSU:D AT tAA tDH SCL SDA Write Bus Timing tSU:STO Start Stop Start Acknowledge tAA tHD:DAT tHD:STA tSU:DAT SCL SDA Data Retention (VDD = 2.7V to 3.65V unless otherwise specified) Parameter Min Units Notes Data Retention 10 Years 1 Notes 1. Endurance is the guaranteed number of read- or write-cycles per address that can be performed while maintaining the specified data retention. It is unlikely to reach this limit for most applications.

Rev 2.0 July 2003 Page 12 of 13 8-pin SOIC JEDEC MS-012 Pin 1 Index Area E H D A B e .10 mm .004 in. α h 45 ° L C Selected Dimensions Refer to JEDEC MS-012 for complete dimensions and notes. Controlling dimensions in millimeters. Conversions to inches are not exact. Symbol Dim Min Nom. Max A mm in. 1.35 0.053 1.75 0.069 A1 mm in. 0.10 0.004 0.25 0.010 B mm in. 0.33 0.013 0.51 0.020 C mm in. 0.19 0.007 0.25 0.010 D mm in. 4.80 0.189 5.00 0.197 E mm in. 3.80 0.150 4.00 0.157 e mm in.

1.27 BSC

.050 BSC H mm in. 5.80 0.228 6.20 0.244 h mm in. 0.25 0.010 0.50 0.197 L mm in. 0.40 0.016 1.27 0.050 α 0° 8°

Rev 2.0 July 2003 Page 13 of 13

Revision History

0.1 7/21/00 Initial Release 0.2 5/9/01 Endurance changed to unlimited. 0.3 10/11/01 Changed Data Retention table. Added pin numbers to pinout. 1.0 3/29/02 Changed status to Preliminary. 2.0 7/23/03 Changed status to Production. Extended storage temperature limits.