FM24C32

FM24C32U FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

I Extended operating voltage: 2.7V to 5.5V I Up to 400 KHz clock frequency at 2.7V to 5.5V I Low power consumption —0.2mA active current typical —10 µA standby current typical —1 µA standby current typical (L version) —0.1 µA standby current typical (LZ version) I Schmitt trigger inputs I 32 byte page write mode I Self timed write cycle (6ms typical) I Hardware Write Protection for upper half of the array I Low VCC programming lockout for VCC = 5V±10% (“H” option) —Internal ERASE/WRITE logic is disabled if VCC is below 3.8V I Endurance: 1 Million data changes I Data Retention: Greater than 40 years I Packages: 8-Pin DIP and 8-Pin SO I Temperature range —Commercial: 0 °C to +70°C —Industrial (V): -40 °C to +85°C —Automotive (E): -40 °C to +125°C H.V. GENERATION TIMING &CONTROL E2PROM ARRAY YDEC DATA REGISTER XDEC CONTROL LOGIC WORD ADDRESS COUNTER SLAVE ADDRESS REGISTER & COMPARATOR START STOP LOGIC WRITE LOCKOUT CK DIN R/W SDA SCL WP VCC VSS DOUT

2 www.fairchildsemi.com FM24C32U Rev. A.1 FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROM V SS VCC WP SCL SDA FM24C32U Connection Diagram Dual-in-Line Package (N) and SO Package (M8) See Package Number N08E and M08A Pin Names VSS Ground SDA Serial Data I/O SCL Serial Clock Input WP Write Protect VCC Power Supply

3 www.fairchildsemi.com FM24C32U Rev. A.1 FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Ordering Information

FM 24 C XX U F T LZ E XXX Letter Description Package N 8-pin DIP M8 8-pin SOIC Temp. Range None 0 to 70 °C V -40 to +125 °C E -40 to +85 °C Voltage Operating Range Blank 4.5V to 5.5V H 4.5V to 5.5V and V CC Lockout L 2.7V to 5.5V LZ 2.7V to 5.5V and <1µA Standby Current Blank Normal Pin Out T Rotated Die Pin Out SCL Clock Frequency Blank 100KHz F 400KHz Process U Ultralite Process Density 32 32K with Write Protect C CMOS Technology Interface 24 IIC FM Fairchild Non-Volatile Memory

4 www.fairchildsemi.com FM24C32U Rev. A.1 FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROM Product Specifications Absolute Maximum Ratings Ambient Storage Temperature –65°C to +150°C All Input or Output Voltages with Respect to Ground 6.5V to –0.3V Lead Temperature (Soldering, 10 seconds) +300 °C ESD Rating 2000V min. Operating Conditions Ambient Operating Temperature FM24C32U 0 °C to +70°C FM24C32UE -40 °C to +85°C FM24C32UV -40 °C to +125°C Positive Power Supply FM24C32U/FM24C32UH 4.5V to 5.5V FM24C32UL 2.7V to 5.5V FM24C32ULZ 2.7V to 5.5V Standard VCC (4.5V to 5.5V) DC Electrical Characteristics Symbol Parameter Test Conditions Limits Units Min Typ Max (Note 1) ICCA Active Power Supply f SCL = 400 KHz 0.2 1.0 mA Current f SCL = 100 KHz ISB Standby Current V IN = GND or VCC 10 50 µA ILI Input Leakage Current V IN = GND A 0, A1, A2, WP 0.1 1 µA to VCC SCL 0.5 2 µA ILO Output Leakage Current V OUT = GND to VCC 0.1 1 µA VIL Input Low Voltage –0.3 V CC x 0.3 V VIH Input High Voltage V CC x 0.7 V CC + 0.5 V VOL Output Low Voltage I OL = 3 mA 0.4 V Low VCC (2.7V to 5 .5V) DC Electrical Characteristics Symbol Parameter Test Conditions Limits Units Min Typ Max (Note 1) ICCA Active Power Supply Current f SCL = 400 KHz 0.2 1.0 mA fSCL = 100 KHz ISB Standby Current V IN = GND V CC = 2.7V - 4.5V (L) 1 10 µA (Note 3) or V CC VCC = 2.7V - 4.5V (LZ) 0.1 1 µA VCC = 4.5V - 5.5V 10 50 µA ILI Input Leakage Current V IN = GND A 0, A1, A2, WP 0.1 1 µA to VCC SCL 0.5 2 µA ILO Output Leakage Current V OUT = GND to VCC 0.1 1 µA VIL Input Low Voltage –0.3 V CC x 0.3 V VIH Input High Voltage V CC x 0.7 V CC + 0.5 V VOL Output Low Voltage I OL = 3 mA 0.4 V Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2) Symbol Test Conditions Max Units CI/O Input/Output Capacitance (SDA) V I/O = 0V 8 pF CIN Input Capacitance (A0, A1, A2, SCL) V IN = 0V 6 pF Note 1: Typical values are TA = 25°C and nominal supply voltage (5V). Note 2: This parameter is periodically sampled and not 100% tested.

5 www.fairchildsemi.com FM24C32U Rev. A.1 FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROM AC Test Conditions Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10 ns Input & Output Timing Levels V CC x 0.3 to VCC x 0.7 Output Load 1 TTL Gate and C L = 100 pF Bus Timing SCL SDA IN SDA OUT tF tLOW tHIGH tR tLOW tAA tDH tBUF tSU:STA tHD:DATtHD:STA tSU:DAT tSU:STO 0.9VCC 0.1VCC 0.7VCC 0.3VCC Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V) Symbol Parameter 100 KHz 400 KHz Units Min Max Min Max fSCL SCL Clock Frequency 100 400 KHz TI Noise Suppression Time Constant at SCL, SDA Inputs (Minimum VIN 100 50 ns Pulse width) tAA SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9 µs tBUF Time the Bus Must Be Free before 4.7 1.3 µs a New Transmission Can Start tHD:STA Start Condition Hold Time 4.0 0.6 µs tLOW Clock Low Period 4.7 1.5 µs tHIGH Clock High Period 4.0 0.6 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs (for a Repeated Start Condition) tHD:DAT Data in Hold Time 0 0 ns tSU:DAT Data in Setup Time 250 100 ns tR SDA and SCL Rise Time 1 0.3 µs tF SDA and SCL Fall Time 300 300 ns tSU:STO Stop Condition Setup Time 4.7 0.6 µs tDH Data Out Hold Time 300 50 ns tWR Write Cycle Time (Note 4) 4.5V to 5.5V V CC 10 10 ms 2.7V to 4.5V VCC 15 15 Note 4: The write cycle time (t WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the FM24C32U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer "Write Cycle Timing" diagram. AC Testing Input/Output Waveforms

6 www.fairchildsemi.com FM24C32U Rev. A.1 FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROM SDA SCL Master Transmitter/ Receiver Slave Transmitter/ Receiver Master Transmitter Slave Receiver Master Transmitter/ Receiver VCCVCC Typical System Configuration Note: Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7kΩ) SDA SCL STOP CONDITION START CONDITION WORD n 8th BIT ACK tWR Write Cycle Timing Note: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.

7 www.fairchildsemi.com FM24C32U Rev. A.1 FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROM Background Information (IIC Bus) Extended IIC specification is an extension of Standard IIC speci- fication to allow addressing of EEPROMs with more than 16Kbits of memory on an IIC bus. The difference between the two specifications is that Extended IIC specification defines two bytes of “Array Address” information while Standard IIC specification defines only one. All other aspects are identical between the two specifications. Using two bytes of Array Address and 3 address signals (A2, A1 and A0), it is now possible to address up to 4 Mbits 8 * 28 * 23 * 8 = 4 Mbits) of memory on an IIC bus. Note that due to format difference, it is not possible to have peripherals which follow Standard IIC specification (e.g. 16K bit EEPROM) and peripherals which follow Extended IIC specifica- tion (e.g. 32K bit EEPROM) on a common IIC bus. IIC bus allows synchronous bi-directional communication be- tween a TRANSMITTER and a RECEIVER using a Clock signal (SCL) and a Data signal (SDA). Additionally there are up to three Address signals (A2, A1 and A0) which collectively serve as “chip select signal” to a device (e.g. EEPROM) on the bus. All communication on the IIC bus must be started with a valid START condition (by a MASTER), followed by transmittal (by the MASTER) of byte(s) of information (Address/Data). For every byte of information received, the addressed RECEIVER provides a valid ACKNOWLEDGE pulse to further continue the communi- cation unless the RECEIVER intends to discontinue the commu- nication. Depending on the direction of transfer (Write or Read), the RECEIVER can be a SLAVE or the MASTER. A typical IIC communication concludes with a STOP condition (by the MAS- TER). Addressing an EEPROM memory location involves sending a command string with the following information: [DEVICE TYPE]— [DEVICE/PAGE BLOCK SELECTION]— [R/W BIT]— [ARRAY ADDRESS#1]— [ARRAY ADDRESS#0] Slave Address Slave Address is an 8-bit information consisting of a Device type field (4bits), Device/Page block selection field (3bits) and Read/ Write bit (1bit). Slave Address Format Device Type IIC bus is designed to support a variety of devices such as RAMs, EPROMs etc., along with EEPROMS. Hence to properly identify various devices on the IIC bus, a 4-bit “Device Type” identifier string is used. For EEPROMS, this 4-bit string is 1-0-1-0. Every IIC device on the bus internally compares this 4-bit string to its own “Device Type” string to ensure proper device selection. Device/Page Block Selection When multiple devices of the same type (e.g. multiple EEPROMS) are present on the IIC bus, then the A2, A1 and A0 address information bits are used in device selection. Every IIC device on the bus internally compares this 3-bit string to its own physical configuration (A2, A1 and A0 pins) to ensure proper device selection. This comparison is in addition to the “Device Type” comparison. In addition to selecting an EEPROM, these 3 bits are also used to select a “page block” within the selected EEPROM. Each page block is 512Kbit (64 K Bytes) in size. If an EEPROM contains more than one page bock then the selection of a page block within the EEPROM is by using A2, A1 and A0 bits. Read/Write Bit Last bit of the Slave Address indicates if the intended access is Read or Write. If the bit is "1," then the access is Read, whereas if the bit is "0," then the access is Write. Acknowledge Acknowledge is an active LOW pulse on the SDA line driven by an addressed receiver to the addressing transmitter to indicate receipt of 8-bits of data. The receiver provides an ACK pulse for every 8-bits of data received. This handshake mechanism is done as follows: After transmitting 8-bits of data, the transmitter re- leases the SDA line and waits for the ACK pulse. The addressed receiver, if present, drives the ACK pulse on the SDA line during the 9th clock and releases the SDA line back (to the transmitter). Refer Figure 3. Array Address#1 This is an 8-bit information containing the most significant 8-bits of 16-bit memory array address of a location to be selected within a page block of the device. Array Address#0 This is an 8-bit information containing the least significant 8-bits of 16-bit memory array address of a location to be selected within a page block of the device. Device Type Identifier Device/Page Block Selection 1 0 1 0 A2 A1 A0 R/W (LSB)

9 www.fairchildsemi.com FM24C32U Rev. A.1 FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROM Data Validity (Figure 1) Start and Stop Definition (Figure 2) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER 18 9 START CONDITION ACKNOWLEDGE PULSE tAA tDH SDA SCL START CONDITION STOP CONDITION SCL DATA STABLE DATA CHANGE SDA Acknowledge Response from Receiver (Figure 3)

10 www.fairchildsemi.com FM24C32U Rev. A.1 FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROM Write Operations BYTE WRITE For byte write operation, two bytes of address are required after the slave address. These two bytes select 1 out of the 4096 locations in the memory. The master provides these two address bytes and for each address byte received, FM24C32U responds with an acknowledge pulse. Master then provides a byte of data to be written into the memory. Upon receipt of this data, FM24C32U responds with an acknowledge pulse. The master then terminates the transfer by generating a stop condition, at which time the FM24C32U begins the internal write cycle to the memory. While the internal write cycle is in progress the FM24C32U inputs are disabled, and the device will not respond to any requests from the master for the duration of t WR. Refer Figure 4 for the address, acknowledge and data transfer sequence. PAGE WRITE To minimize write cycle time, FM24C32U offers Page Write feature, which allows simultaneous programming of up to 32 contiguous bytes. To facilitate this feature, the memory array is organized in terms of “Pages”. A Page consists of 32 contiguous byte locations starting at every 32-Byte address boundary (for example, starting at array address 0x0000, 0x0020, 0x0040 etc.). Page Write operation is confined to a single page. In other words a Page Write operation will not cross over to locations on the next page but will “roll over ” to the beginning of the same page whenever end of page is reached and additional data bytes are a continued to be provided. A Page Write operation can be initiated to begin at any location within a page (starting address of the Page Write operation need not be the starting address of a Page). S T O P A C K A C K Bus Activity: Master SDA Line Bus Activity: EEPROM A C K A C K DATA n DATA n+31 A C K WORD ADDRESS (1) WORD ADDRESS (0) SLAVE ADDRESS S T A R T S T O P A C K Bus Activity: Master SDA Line Bus Activity: EEPROM A C K DATA A C K A C K WORD ADDRESS (1) WORD ADDRESS (0) SLAVE ADDRESS S T A R T Page Write is initiated in the same manner as the Byte Write operation; but instead of terminating the cycle after transmitting the first data byte, the master can further transmit up to 31 more bytes. After the receipt of each byte, FM24C32U will respond with an acknowledge pulse, increment the internal address counter to the next address, and is ready to accept the next data. If the master should transmit more than 32 bytes prior to generating the STOP condition, the address counter will “roll over ” and previously loaded data will be re-loaded. As with the Byte Write operation, all inputs are disabled until completion of the internal write cycle. Refer Figure 5 for the address, acknowledge, and data transfer sequence. Acknowledge Polling Once the stop condition is issued to indicate the end of the host’s write operation, the FM24C32U initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the FM24C32U is still busy with the write operation, no ACK will be returned. If the FM24C32U has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Write Protection Programming of the upper half (upper 8Kbit) of the memory will not take place if the WP pin of the FM24C32U is connected to V CC. The FM24C32U will respond to slave and byte addresses; but if the memory accessed is write protected by the WP pin, the FM24C32U will not generate an acknowledge after the first byte of data has been received. Thus the program cycle will not be started when the stop condition is asserted. Byte Write (Figure 4) Page Write (Figure 5)

12 www.fairchildsemi.com FM24C32U Rev. A.1 FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROM 8-Pin Molded Small Outline Package (M8) Package Number M08A Physical Dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) Lead #1 IDENT Seating Plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) Typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) Typ 0.016 - 0.050 (0.406 - 1.270) Typ. All Leads 8¡ Max, Typ. All leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads 0.004 (0.102) All lead tips 0.010 - 0.020

13 www.fairchildsemi.com FM24C32U Rev. A.1 FM24C32U – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROM Physical Dimensions inches (millimeters) unless otherwise noted Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Americas Europe Hong Kong Japan Ltd. Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg. Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan Franç ais Tel: +33 (0) 1-6930-3696 Tel; +852-2722-8338 Tel: 81-3-3818-8840 Italiano Tel: +39 (0) 2-249111-1 Fax: +852-2722-8383 Fax: 81-3-3818-8841 Molded Dual-In-Line Package (N) Package Number N08E 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337)DIA 1234 8765 0.250 - 0.005 (6.35 ± 0.127) 870.032 ± 0.005 (0.813 ± 0.127) Pin #1 Option 2 RAD 0.145 - 0.200 (3.683 - 5.080) 0.130 ± 0.005 (3.302 ± 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) Min0.018 ± 0.003 (0.457 ± 0.076) 90° ± 4° Typ 0.100 ± 0.010 (2.540 ± 0.254) 0.040 (1.016) 0.039 (0.991) Typ. 20° ± 1° 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) Pin #1 IDENT Option 1

0.280 MIN

0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762)MAX 0.125 (3.175) DIA NOM 0.009 - 0.015 (0.229 - 0.381) 0.045 ± 0.015 (1.143 ± 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95° ± 5° 0.090 (2.286) (7.112) IDENT