FM24C256EYYX

FM24C256 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

I Extended Operating Voltages — C256L: 2.7V - 5.5V — C256LZ: 2.7V - 5.5V I Low Power CMOS — 1mA active current typical — C256/C256L: 10µA standby current typical — C256LZ: less than 1µA standby current I 2-wire IIC serial interface I 64 byte page write mode I Max write cycle time of 6ms byte/page I 40 years data retention I Endurance: 100,000 data changes I Hardware write protect for entire array I Schmitt trigger inputs for noise suppression I Electrostatic discharge protection > 4000V I 8-pin DIP and 8-pin SO (150 mil) packages. Contact factory for CSP package availability DS800023-1 H.V. GENERATION TIMING &CONTROL E2PROM ARRAY YDEC DATA REGISTER XDEC CONTROL LOGIC WORD ADDRESS COUNTER SLAVE ADDRESS REGISTER & COMPARATOR START STOP LOGIC WRITE LOCKOUT START CYCLE CK DIN R/W LOAD INC SDA SCL WP VCC DOUT

2 www.fairchildsemi.com FM24C256 rev. B.3 FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect Connection Diagram Dual-In-Line Package (N) and 8-Pin SO Package (M8) Top View See Package Number N08E and M08A Pin Names A0, A1, A2 Device Address Input VSS Ground SDA Data I/O SCL Clock Input WP Write Protect VCC Power Supply VSS VCC WP SCL SDA FM24C256 DS800023-2

3 www.fairchildsemi.com FM24C256 rev. B.3 FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect

Ordering Information

FM 24 C XX F LZ E YY X Letter Description Blank Tube X Tape and Reel Package N 8-pin DIP M8 8-pin SO8 Temp. Range Blank 0 to 70 °C E -40 to +85 °C Voltage Operating Range Blank 4.5V to 5.5V L 2.7V to 5.5V LZ 2.7V to 5.5V and <1µA Standby Current SCL Clock Frequency Blank 100KHz F 400KHz Density 256 256K with write protect C CMOS Interface 24 IIC - 2 Wire FM Fairchild Non-Volatile Memory Part Number Clock Frequency V CC Standby Current FM24C256YYX 4.5V - 5.5V 10 µA typical FM24C256LYYX 100KHz 2.7V - 5.5V FM24C256LZYYX 1 µA max FM24C256FYYX 4.5V - 5.5V 10 µA typical FM24C256FLYYX 400KHz 2.7V - 5.5V FM24C256FLZYYX 1 µA max Part Number Clock Frequency V CC Standby Current FM24C256EYYX 4.5V - 5.5V 10 µA typical FM24C256LEYYX 100KHz 2.7V - 5.5V FM24C256LZEYYX 1 µA max FM24C256FEYYX 4.5V - 5.5V 10 µA typical FM24C256FLEYYX 400KHz 2.7V - 5.5V FM24C256FLZEYYX 1 µA max Commercial Temperature Range: 0° to +70°C Industrial Temperature Range: -40° to +85°C

4 www.fairchildsemi.com FM24C256 rev. B.3 FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect Absolute Maximum Ratings Ambient Storage Temperature –65 °C to +150°C All Input or Output Voltages with Respect to Ground 6.5V to –0.3V Lead Temperature (Soldering, 10 seconds) +300 °C ESD Rating 4000V min. Operating Conditions Ambient Operating Temperature FM24C256/L/LZ 0 °C to +70°C FM24C256F/FL/FLZ 0 °C to +70°C FM24C256E/LE/LZE -40 °C to +85°C FM24C256FE/FLE/FLZE -40 °C to +85°C Positive Power Supply FM24C256/E 4.5V to 5.5V FM24C256F/FE 4.5V to 5.5V FM24C256L/LZ 2.7V to 5.5V FM24C256FL/FLZ 2.7V to 5.5V FM24C256LE/LZE 2.7V to 5.5V FM24C256FLE/FLZE 2.7V to 4.5V Standard VCC (4.5V to 5.5V) DC Electrical Characteristics Symbol Parameter Test Conditions Limits Units Min Typ Max ICCA Active Power Supply Current f SCL = 100 kHz 0.5 1.0 mA fSCL = 400 kHz ISB Standby Current V IN = GND or VCC 10 50 µA ILI Input Leakage Current V IN = GND to VCC 0.1 1 µA ILO Output Leakage Current V OUT = GND to VCC 0.1 1 µA VIL Input Low Voltage –0.3 V CC x 0.3 V VIH Input High Voltage V CC x 0.7 V CC + 0.5 V VOL Output Low Voltage I OL = 2.1 mA 0.4 V Low VCC (2.7V to 5.5V) DC Electrical Characteristics Symbol Parameter Test Conditions Limits Units Min Typ Max ICCA Active Power Supply Current f SCL = 100 kHz 0.5 1.0 mA fSCL = 400 kHz ISB Standby Current for L V IN = GND or VCC = 4.5V - 5.5V 10 50 µA (Note 1) V IN = GND or VCC = 2.7V - 4.5V 1 10 Standby Current for LZ V IN = GND or VCC = 4.5V - 5.5V 10 50 VIN = GND or VCC = 2.7V - 4.5V 0.1 1 ILI Input Leakage Current V IN = GND to VCC 0.1 1 µA ILO Output Leakage Current V OUT = GND to VCC 0.1 1 µA VIL Input Low Voltage –0.3 V CC x 0.3 V VIH Input High Voltage V CC x 0.7 V CC + 0.5 V VOL Output Low Voltage I OL = 2.1 mA 0.4 V Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V Symbol Test Conditions Max Units CI/O Input/Output Capacitance (SDA) V I/O = 0V 8 pF CIN Input Capacitance (A0, A1, A2, SCL) V IN = 0V 6 pF Note 1: Typical values are for T A = 25°C and nominal supply voltage (5V).

5 www.fairchildsemi.com FM24C256 rev. B.3 FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect AC Conditions of Test Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10 ns Input & Output Timing Levels V CC x 0.5 Output Load 1 TTL Gate and C L = 100 pF Read and Write Cycle Limits (Standard and Low VCC Range - 2.7V-5.5V) Symbol Parameter 100 kHz 400 kHz Units Min Max Min Max fSCL SCL Clock Frequency 100 400 kHz TI Noise Suppression Time Constant at SCL, SDA Inputs (Minimum VIN 100 50 ns Pulse width) tAA SCL Low to SDA Data Out Valid 0.3 3.5 0.3 1.2 µs tBUF Time the Bus Must Be Free before 4.7 1.3 µs a New Transmission Can Start tHD:STA Start Condition Hold Time 4.0 0.6 µs tLOW Clock Low Period 4.7 1.5 µs tHIGH Clock High Period 4.0 0.6 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs (for a Repeated Start Condition) tHD:DAT Data in Hold Time 0 0 µs tSU:DAT Data in Setup Time 250 100 ns tR SDA and SCL Rise Time 1 0.3 µs tF SDA and SCL Fall Time 300 300 ns tSU:STO Stop Condition Setup Time 4.7 0.6 µs tDH Data Out Hold Time 100 100 ns tWR Write Cycle Time 6 6 ms (Note 2) Note 2: The write cycle time (t WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the FM24C256 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address

6 www.fairchildsemi.com FM24C256 rev. B.3 FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect BACKGROUND INFORMATION (IIC Bus) The IIC bus allows synchronous bidirectional communication be- tween Transmitter/Receiver using the SCL (clock) and SDA (Data I/O) lines. All communication must be started with a valid START condition, concluded with a STOP condition and acknowledged by the Receiver with an ACKNOWLEDGE condition. In addition, since the IIC bus is designed to support other devices such as RAM, EPROM, etc., the device type identifier string, or control byte, must follow the START condition. For EEPROMs, the first 4-bit of the control byte is 1010 binary for READ and WRITE operations. This is then followed by the device selection bits A2, A1 and A0, and acts as the three most significant bits of the word address.The final bit in the control byte determines the type of operation performed (READ/WRITE). A "1" signifies a READ while a "0" signifies a WRITE. The control byte is then followed by two bytes that define the word address, which is then followed by the data byte. The EEPROMs on the IIC bus may be configured in any manner required, providing the total memory addressed does not exceed 512K bits (64K bytes). EEPROM memory addressing is controlled by hardware configuring the A2, A1, and A0 pins (Device Address pins) with pull-up or pull-down resistors. ALL UNUSED PINS MUST BE GROUNDED (tied to V SS). Addressing an EEPROM memory location involves sending a command string with the following information: [DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK AD- DRESS]-[BYTE ADDRESS] Pin Description SERIAL CLOCK (SCL) Definitions Word 8 bits (byte) of data Page 64 sequential addresses (one byte each) that may be programmed during a "Page Write" programming cycle. Master Any IIC device CONTROLLING the transfer of data (such as a microcontroller). Slave Device being controlled (EEPROMS are always considered Slaves). Transmitter Device currently SENDING data on the bus (may be either a Master or Slave). Receiver Device currently receiving data on the bus (Master or Slave). The SCL input is used to clock all data into and out of the device. SERIAL DATA (SDA) SDA is a bidirectional pin used to transfer data to and from the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. Device Address Inputs (A0, A1, A2) Device address pins A0, A1, and A2 are connected to VCC or VSS to configure the EEPROM address for multiple device configura- tion. A total of eight different devices can be attached to the same SDA bus. Write Protection (WP) If WP is tied to V CC, program WRITE operations onto the entire array of the memory will not be executed. READ operations are always available. If WP is tied to V SS or left floating (unconnected), normal memory operation is enabled for READ/WRITE over the entire 256K bit memory array. This feature allows the user to assign the entire array of the memory as ROM, which can be protected against accidental programming writes. When WRITE is disabled, slave address and word address will be acknowledged but data will not be acknowledged. Device Operation The FM24C256xxx supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving devices as the receiver. The device controlling the transfer is the master and the device that is con- trolled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. There- fore, the FM24C256xxx is considered a slave in all applications. CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH and are reserved for indication of start and stop conditions. Refer to Figures 1 and 2. START CONDITION All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The FM24C256xxx continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. STOP CONDITION All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the FM24C256xxx to place the device in the standby power mode. /;/; SCL SDA IN SDA OUT tF tLOW tHIGH tR tLOW tAA tDH tBUF tSU:STA tHD:DATtHD:STA tSU:DAT tSU:STO DS800023-3 Bus Timing Note 3: SCL = Serial Clock Data SDA = Serial Data I/O

7 www.fairchildsemi.com FM24C256 rev. B.3 FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect Write Cycle Timing ACKNOWLEDGE ACK (acknowledge) is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3. The FM24C256xxx device will always respond with an acknowl- edge after recognition of a start condition and its slave address. If Write Cycle Timing: SDA SCL STOP CONDITION START CONDITION WORD n 8th BIT ACK tWR SDA SCL DATA STABLE DATA CHANGE SDA SCL START CONDITION STOP CONDITION DS800023-4 DS800023-5 Data Validity (Figure 1) Definition of Start and Stop (Figure 2) DS800023-6 both the device and a WRITE operation have been selected, the FM24C256xxx will respond with an acknowledge after the receipt of each subsequent eight bit word. In the READ mode the FM24C256xxx slave will transmit eight bits of data, release the SDA line and monitor the line for an acknowl- edge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode. SCL FROM MASTER Data Output from Transmitter Data Output from Receiver START ACKNOWLEDGE 18 9 Acknowledge Response from Receiver (Figure 3) DS800023-7

10 www.fairchildsemi.com FM24C256 rev. B.3 FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect Current Address Read (Figure 7) Random Read (Figure 8) Sequential Read (Figure 9) S T O P A C K NO A C K Bus Activity: Master SDA Line 101 0 Bus Activity A C K DATA n + x A C K DATA n + 1DATA n SLAVE ADDRESS A C K S T A R T S T O P A C K NO A C K Bus Activity: Master SDA Line 101 0 1010100 Bus Activity A C K A C K WORD ADDRESS (1) WORD ADDRESS (0) SLAVE ADDRESS SLAVE ADDRESS DATA n A C K S T A R T S T A R T S T O P A C K NO A C K 1010 DATASLAVE ADDRESS S T A R T DS800023-10 DS800023-11 DS800023-12

11 www.fairchildsemi.com FM24C256 rev. B.3 FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect Molded Small Out-Line Package (M8) Order Number FM24C256xxxM8 or FM24C256xxxEM8 Package Number M08A Physical Dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) Lead #1 IDENT Seating Plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) Typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) Typ 0.016 - 0.050 (0.406 - 1.270) Typ. All Leads 8¡ Max, Typ. All leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads 0.004 (0.102) All lead tips 0.010 - 0.020

12 www.fairchildsemi.com FM24C256 rev. B.3 FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect Physical Dimensions inches (millimeters) unless otherwise noted Molded Dual-In-Line Package (N) Order Number FM24C256xxxN or FM24C256xxxEN Package Number N08E 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337)DIA 1234 8765 0.250 - 0.005 (6.35 ± 0.127) 870.032 ± 0.005 (0.813 ± 0.127) Pin #1 Option 2 RAD 0.145 - 0.200 (3.683 - 5.080) 0.130 ± 0.005 (3.302 ± 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) Min0.018 ± 0.003 (0.457 ± 0.076) 90° ± 4° Typ 0.100 ± 0.010 (2.540 ± 0.254) 0.040 (1.016) 0.039 (0.991) Typ. 20° ± 1° 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) Pin #1 IDENT Option 1

0.280 MIN

0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762)MAX 0.125 (3.175) DIA NOM 0.009 - 0.015 (0.229 - 0.381) 0.045 ± 0.015 (1.143 ± 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95° ± 5° 0.090 (2.286) (7.112) IDENT Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Americas Europe Hong Kong Japan Ltd. Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg. Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan Français Tel: +33 (0) 1-6930-3696 Tel; +852-2722-8338 Tel: 81-3-3818-8840 Italiano Tel: +39 (0) 2-249111-1 Fax: +852-2722-8383 Fax: 81-3-3818-8841