FM24C16A-S

FM24C16A ETC1 | Alldatasheet

Document overview

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• PDF pages: 13

Technical content

Features

16K bit Ferroelectric Nonvolatile RAM

• Organized as 2,048 x 8 bits
• High Endurance (1012) Read/Write Cycles
• 10 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface
• Up to 1MHz maximum bus frequency
• Direct hardware replacement for EEPROM Low Power Operation
• 5V operation
• 150 µA Active Current (100 kHz)
• 10 µA Standby Current Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin SOIC

Description

The FM24C16A is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for over 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM24C16A performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. The FM24C16A is capable of supporting 10 12 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM24C16A ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows the system to write data more frequently, with less system overhead. The FM24C16A provides substantial benefits to users of serial EEPROM, and these benefits are available as a hardware drop-in replacement. The FM24C16A is available in an industry standard 8-pin SOIC and uses a two-wire protocol. The specifications are guaranteed over the industrial temperature range from -40°C to +85°C. Pin Configuration Pin Names Function SDA Serial Data/Address SCL Serial Clock WP Write Protect VDD Supply Voltage VSS Ground

Ordering Information

Figure 1. Block Diagram output driver includes slope control for falling edges. A pull-up resistor is required. the falling edge and clocked-in on the rising edge. all addresses may be written. This pin is internally pulled down.

Rev 0.1 June 2002 Page 8 of 13 state is altered, the change can be written. This avoids writing to memory on power down when the available time is short and power scarce. 3. High noise environments . Writing to EEPROM in a noisy environment can be challenging. When severe noise or power fluctuations are present, the long write time of EEPROM creates a window of vulnerability during which the write can be corrupted. The fast write of FRAM is complete within a microsecond. This time is typically too short for noise or power fluctuation to disturb it. 4. Time to market . In a complex system, multiple software routines may need to access the nonvolatile memory. In this environment the time delay associated with programming EEPROM adds undue complexity to the software development. Each software routine must wait for complete programming before allowing access to the next routine. When time to market is critical, FRAM can eliminate this simple obstacle. As soon as a write is issued to the FM24C16A, it is effectively done -- no waiting. 5. RF/ID . In the area of contactless memory, FRAM provides an ideal solution. Since RF/ID memory is powered by an RF field, the long programming time and high current consumption needed to write EEPROM is unattractive. FRAM provides a superior solution. The FM24C16A is suitable for multi-chip RF/ID products. 6. Maintenance tracking . In sophisticated systems, the operating history and system state during a failure is important knowledge. Maintenance can be expedited when this information has been recorded. Due to the high write endurance, FRAM makes an ideal system log. In addition, the convenient 2-wire interface of the FM24C16A allows memory to be distributed throughout the system using minimal additional resources.

Rev 0.1 June 2002 Page 9 of 13 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings Notes VDD Power Supply Voltage with respect to V SS -1.0V to +7.0V VIN Voltage on any signal pin with respect to V SS -1.0V to +7.0V and VIN < VDD+1.0V TSTG Storage temperature -55°C to +125°C TLEAD Lead temperature (Soldering, 10 seconds) 300° C Note 1: The VIN < VDD+1.0V requirement does not apply to the SDA and SCL pins. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 4.5 5.0 5.5 V IDD VDD Supply Current @ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 115 400 0.8 150 500 µA µA mA ISB Standby Current 1 10 µA 2 ILI Input Leakage Current 10 µA 3 ILO Output Leakage Current 10 µA 3 VIL Input Low Voltage -0.3 0.3 V DD V 4 VIH Input High Voltage 0.7 V DD V DD + 0.5 V 4 VOL Output Low Voltage @ IOL = 3 mA 0.4 V RIN Input Resistance (WP pin) For VIN = VIL (max) For VIN = VIH (min) KΩ MΩ VHYS Input Hysteresis 0.05 V DD V 4 Notes 1. SCL toggling between V DD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCL = SDA = V DD. All inputs VSS or VDD. Stop command issued. 3. V IN or VOUT = VSS to VDD. Does not apply to pins with pull down resistors. 4. This parameter is characterized but not tested. 5. The input pull-down circuit is strong (50K Ω ) when the input voltage is below VIL and much weaker (1MΩ ) when the input voltage is above VIH.

Rev 0.1 June 2002 Page 10 of 13 AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz 1 tLOW Clock Low Period 4.7 1.3 0.6 µs tHIGH Clock High Period 4.0 0.6 0.4 µs tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs tBUF Bus Free Before New Transmission 4.7 1.3 0.5 µs tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 µs tHD:DAT Data In Hold Time 0 0 0 ns tSU:DAT Data In Setup Time 250 100 100 ns tR Input Rise Time 1000 300 300 ns 2 tF Input Fall Time 300 300 100 ns 2 tSU:STO Stop Condition Setup 4.0 0.6 0.25 µs tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 The speed-related specifications are guaranteed characteristic points from DC to 1 MHz. 2 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5V) Symbol Parameter Max Units Notes CI/O Input/output capacitance (SDA) 8 pF 1 CIN Input capacitance 6 pF 1 Notes 1 This parameter is periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels 0.1 V DD to 0.9 VDD Input rise and fall times 10 ns Input and output timing levels 0.5 V DD Equivalent AC Load Circuit 5.5V Output 1700 Ω 100 pF

Rev 0.1 June 2002 Page 11 of 13 Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing tSU:SDA Start tR tF Stop Start tBUF tHIGH 1/fSCL tLOW tSP tSP Acknowledge tHD:DAT tSU:D AT tAA tDH SCL SDA Write Bus Timing tSU:STO Start Stop Start Acknowledge tAA tHD:DAT tHD:STA tSU:DAT SCL SDA Data Retention (VDD = 4.5V to 5.5V unless otherwise specified) Parameter Min Units Notes Data Retention 10 Years 1 Notes 1. The relationship between retention, temperature, and the associated reliability level is characterized in a separate reliability report.

Rev 0.1 June 2002 Page 12 of 13 8-pin SOIC (JEDEC MS-012 variation AA) Pin 1 Index Area E H D A B e .10 mm .004 in. α h 45 ° L C Selected Dimensions Refer to JEDEC MS-012 for complete dimensions and notes. Controlling dimensions in millimeters. Conversions to inches are not exact. Symbol Dim Min Nom. Max A mm in. 1.35 0.053 1.75 0.069 A1 mm in. 0.10 0.004 0.25 0.010 B mm in. 0.33 0.013 0.51 0.020 C mm in. 0.19 0.007 0.25 0.010 D mm in. 4.80 0.189 5.00 0.197 E mm in. 3.80 0.150 4.00 0.157 e mm in.

1.27 BSC

0.050 BSC

in. 5.80 0.228 6.20 0.244 h mm in. 0.25 0.010 0.50 0.197 L mm in. 0.40 0.016 1.27 0.050 α 0° 8°

Rev 0.1 June 2002 Page 13 of 13

Revision History

0.1 6/26/02 Initial Release