FLS6617 ONSEMI | Alldatasheet
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© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FLS6617 • Rev. 1.1 FLS6617 — Primary-Side-Regulation PWM with POWER MOSFET Integrated FLS6617 Primary-Side-Regulation PWM with POWER MOSFET Integrated
Features
Low Standby Power under 30 mW High-Voltage Startup Fewest External Component Counts Constant-Voltage (CV) and Constant-Current (CC) Control without Secondary-Feedback Circuitry Green-Mode: Linearly Decreasing PWM Frequency with Cycle Skipping Fixed PWM Frequency at 50 kHz with Proprietary Frequency Hopping to Solve EMI Problem Peak-Current-Mode Control in CV Mode Cycle-by-Cycle Current Limiting VDD Over-Voltage Protection with Auto Restart VDD Under-Voltage Lockout (UVLO) Gate Output Maximum Voltage Clamped at 15 V Fixed Over-Temperature Protection with Auto Restart Available in the 7-Lead SOP Package
Applications
Battery chargers for cellular phones, cordless phones, PDA, digital cameras, power tools, etc. Replaces linear transformers and RCC SMPS Related Resources Fairchild Power Supply WebDesigner — Flyback Design & Simulation - In Minutes at No Expense
Description
This third-generation Primary Side Regulation (PSR) and highly integrated PWM controller provides several features to enhance the performance of low-power flyback converters. The proprietary TRUECURRENT® technology of FLS6617 enables precise CC regulation and simplified circuit design for battery-charger applications leading to lower-cost, smaller, and lighte r chargers, compared to a conventional design or a linear transformer. To minimize standby power consumption, the proprietary green mode provides off-time modulation to linearly decrease PWM frequency under light-load conditions. Green mode assists the power supply in meeting power conservation requirements. By using the FLS6617, a charger can be implemented with few external components and minimized cost. A typical output CV/CC characteristic envelope is shown in Figure 1. VO IO ±7% Figure 1. Typical Output V- I Characteristic
Ordering Information
Temperature Range Package Packing Method FLS6617MX -40°C to +125°C 7-Lead, Small Outline Package (SOP-7) Tape & Reel
Figure 4. Top Mark Figure 5. Pin Configuration peak-current-mode control in CV mode and provide the output-current regulation in CC mode.
2 VDD
Power Supply. IC operating current and MOSFET driving current are supplied through this pin. startup and turn-off are 16 V and 5 V, respectively. The operating current is lower than 5 mA.
3 GND Ground
4 NC No Connection
voltage of auxiliary winding. 7 HV High Voltage. This pin connects to bulk capacitor for high-voltage startup. 8 DRAIN Driver Output. Power MOSFET drain. This pin is the high-voltage power MOSFET drain.
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FLS6617 • Rev. 1.1 4 FLS6617 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dama ge the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Units VHV HV Pin Input Voltage 500 V VVDD DC Supply Voltage(1,2) 30 V VVS VS Pin Input Voltage -0.3 6.0 V VCS CS Pin Input Voltage -0.3 6.0 V VCOMV Voltage Error Amplifier Output Voltage -0.3 6.0 V VCOMI Current Error Amplifier Output Voltage -0.3 6.0 V VDS Drain-Source Voltage 700 V ID Continuous Drain Current TA=25°C 1 A TA=100°C 0.6 A IDM Pulsed Drain Current 4 A EAS Single Pulse Avalanche Energy 50 mJ IAR Avalanche Current 1 A PD Power Dissipation (TA＜50°C) 660 mW θJA Thermal Resistance (Junction-to-Air) 147 °C/W ȌJT Thermal Resistance (Junction-to-Case) 11 °C/W TJ Operating Junction Temperature -40 +150 °C TSTG Storage Temperature Range -55 +150 °C TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 °C ESD Electrostatic Discharge Capability (Except HV Pin) Human Body Model, JEDEC-JESD22_A114 4.0 kV Charged Device Model, JEDEC-JESD22_C101 2.0 Notes: 1. Stresses beyond those listed under Absolute Maximum Ratin gs may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to the GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the condi tions for actual device operation. Recommended operating conditions are specified to ensure optimal perform ance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Units TA Operating Ambient Temperature -40 +125 °C
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FLS6617 • Rev. 1.1 5 FLS6617 — Primary-Side-Regulation PWM with POWER MOSFET Integrated
Electrical Characteristics
Unless otherwise specified, VDD=15 V and TA=25°C. Symbol Parameter Condition Min. Typ. Max. Unit VDD Section VOP Continuously Operating Voltage 23 V VDD-ON Turn-On Threshold Voltage 15 16 17 V VDD-OFF Turn-Off Threshold Voltage 4.5 5.0 5.5 V IDD-OP Operating Current 2.5 5.0 mA IDD-GREEN Green-Mode Operating Supply Current 0.95 1.2 mA VDD-OVP VDD Over-Voltage-Protection Level (OVP) 24 V tD-VDDOVP VDD Over-Voltage-Protection Debounce Time 90 200 350 µs HV Startup Current Source Section VHV-MIN Minimum Startup Voltage on HV Pin(3) 50 V IHV Supply Current Drawn from HV Pin VAC=90 V (VDC=100 V), VDD=0 V 1 2.0 5.0 mA IHV-LC Leakage Current after Startup HV=500 V, VDD=VDD-OFF+1 V 0.5 3.0 µA Oscillator Section fOSC Normal Frequency 1 Center Frequency >Vo*0.78 44 50 56 kHz Frequency Hopping Range ±1.6 ±3.4 ±5.2 Normal Frequency 2 Center Frequency <Vo*0.78 Frequency Hopping Range ±2.5 VF-JUM-53 Frequency Jumping Point 50 kHz→36 kHz, Vs 1.75 1.95 2.15 V VF-JUM-35 36 kHz→50 kHz, Vs 2.05 2.25 2.45 V fOSC-N-MIN Minimum Frequency at No-Load 270 395 520 Hz fOSC-CM-MIN Minimum Frequency at CCM 13 kHz VS-F-SKIPH COMV Level for High Cycle Skipping Period Change(3) 1.14 V VS-F-SKIPL COMV Level for Low Cycle Skipping Period Change(3) 0.80 V TSKIP-CV Cycle skipping period(3) VS-F-SKIPH<COMV<VN 240 ms VS-F-SKIPL>COMV 160 ms fDV Frequency Variation vs. VDD Deviation VDD=10 V, 25 V 1 2 % fDT Frequency Variation vs. Temperature Deviation TA=-40°C to 105°C 15 % Voltage-Sense Section Itc IC Bias Current 10 µA VBIAS-COMV Adaptive Bias Voltage Dominated by VCOMV RVS=20 kȍ 1.4 V Continued on the following page…
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FLS6617 • Rev. 1.1 6 FLS6617 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Unless otherwise specified, VDD=15 V and TA=25°C. Symbol Parameter Condition Min. Typ. Max. Unit Current-Sense Section tPD Propagation Delay to GATE Output 90 200 ns tMIN-N Minimum On Time at No-Load 700 850 1050 ns VTH Threshold Voltage for Current Limit 0.8 V Voltage Error Amplifier Section VVR Reference Voltage 2.475 2.500 2.525 V VN Green-Mode Starting Voltage on EA_V fOSC=Normal Frequency1 - 2 kHz 2.5 V VG Green-Mode Ending Voltage on EA_V fOSC =1 kHz 0.5 V Current Error Amplifier Section VIR Reference Voltage 2.475 2.500 2.525 V Internal MOSFET Section(4) DCYMAX Maximum Duty Cycle 60 75 85 % BVDSS Drain-Source Breakdown Voltage ID=250 μA, VGS=0 V 700 900 V ∆BVDSS/∆TJ Breakdown Voltage Temperature Coefficient ID=250 μA, Referenced to TA=25°C
0.53 V/°C
RDS(ON) Static Drain-Source On-Resistance ID=0.5 A, VGS=10 V 13 16 ȍ IS Maximum Continuous Drain-Source Diode Forward Current 1 A IDSS Drain-Source Leakage Current VDS=700 V, TA=25°C 10 µA VDS=560 V, TA=100°C 100 µA tD-ON Turn-On Delay Time VDS=350 V, ID=1 A, RG=25 ȍ(5) 10 30 ns tD-OFF Turn-Off Delay Time 20 50 ns CISS Input Capacitance VGS=0 V, VDS=25 V, fS=1 MHz 175 200 pF COSS Output Capacitance 23 25 pF Over-Temperature-Protection Section TOTP Threshold Temperature for OTP(6) +140 °C Notes: 3. Guaranteed by design. 4. These parameters, although guaranteed, are not 100% tested in production. 5. Pulse test : pulse width ≦ 300 µs, duty cycle ≦ 2%. 6. When the over-temperature protection is activated, the pow er system enter auto-restart mode and output is disabled.
modulates the PWM frequency as shown in Figure 23. Figure 23. Switching Frequency in Green Mode frequency between 44 kHz and 56 kHz. consumption current before the PWM starts to switch. delivered from the auxiliary winding. Figure 24. HV Startup Circuit hold-up capacitor properly supplies VDD during startup. the protections are implemented as auto-restart mode .
5 V, internal startup circuit is enabled again and the
Figure 25. Auto-Restart Operation PWM output if the junction temperature exceeds 140°C.
15 V Zener diode to protect the power MOSFET
transistors against undesired over-voltage gate signals. the power MOS gate resistance are advised. Figure 26. Operation Area
3.85 7.35 1.27
1.75 TYP
3.81
0.65 TYP
1.75 MAX
0.25 0.10 0.51 0.33 C 4.00 3.80 5.00 4.80 6.20 5.80 (0.33) 1.27 3.81 PIN #1
0.25 M C B A
A B 0.25 0.19 B 0.50 0.25 x 45 R0.10 R0.10 0.36 (1.04) 0.900 0.406 SEATING PLANE GAGE PLANE TOP VIEW FRONT VIEW SIDE VIEW LAND PATTERN RECOMMENDATION NOTES: A. THIS PACKAGE DOES NOT FULLY CONFORM TO JEDEC MS-012, VARIATION AA B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS D. DRAWING FILENAME: MKT-M07Brev4 OPTION A BEVEL EDGE OPTION B NO BEVEL EDGE 1 2 3 4 567 DETAIL B SCALE 2:1 0.10 C
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