FL7921R

FL7921R ONSEMI | Alldatasheet

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© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL7921R • Rev. 1.1 FL7921R — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller FL7921R Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller

Features

 Integrated PFC and Flyback Controller  Critical-Mode PFC Controller  Zero-Current Detection for PFC Stage  Quasi-Resonant Operation for PWM Stage  Internal Minimum tOFF 8 µs for QR PWM Stage  Internal 10 ms Soft-Start for PWM  Brownout Protection  High / Low Line Over-Power Compensation  Auto Recovery Over-Current Protection  Auto Recovery Open-Loop Protection  Auto Recovery Over-Temperature Protection  Adjustable Over-Temperature with external NTC through the RT pin  Auto Recovery VDD Pin and Output Voltage OVP

Applications

 Medium to High Power LED Lighting Driver Application

Description

The highly integrated FL7921R combines a Power Factor Correction (PFC) controller and a Quasi - Resonant PWM controller. Integration provides cost - effect design and allows for fewer external components. For PFC, FL7921R uses a controlled on -time technique to provide a regulated DC output voltage and to perform natural power factor correction. An innovative THD optimizer reduces input current distortion at zero - crossing duration to imp rove THD performance. The PFC function is always on regardless of the PWM stage load condition to ensure that high PF can be achieved at light load condition. For PWM, FL7921R provides several functions to enhance power system performance: valley detection, green-mode operation, high / low line over -power compensation. Protection functions include secondary - side open -loop and over -current with auto -recovery protection, external recovery triggering, adjustable over - temperature protection through the RT pin and external NTC resistor, internal over -temperature shutdown, VDD pin OVP, DET pin over -voltage for output OVP, and brown-in / out for AC input voltage UVP. All protections are auto recovery mode except PWM current sense pin open protection. The FL7921R controller is available in a 16-pin, small- outline package (SOP).

Ordering Information

Temperature Range Package Packing Method FL7921RMX Recovery -40 °C to +125°C 16-Pin, Small-Outline Package (SOP) Tape & Reel

Figure 1. Typical Application

Figure 2. Functional Block Diagram

Figure 3. Marking Diagram Figure 4. Pin Configuration

1 RANGE

sets to low impedance if input voltage is at a high level.

2 COMP

divider and provides PFC output over- and under-voltage protections.

4 CSPFC

threshold (0.82 V typical), the PFC switch is turned off to activate cycle-by-cycle current limiting.

5 CSPWM

current during PWM tON time.

© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL7921R • Rev. 1.1 5 FL7921R — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Pin Definitions (Continued) Pin # Name Description 6 OPFC Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage is 15.5 V. 7 VDD Power supply. The threshold voltages for startup and turn-off are 18 V and 7.5 V, respectively. The startup current is less than 30 µA and the operating current is lower than 10 mA. 8 OPWM Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is 17.5 V. 9 GND The power ground and signal ground.

10 DET

This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for the following purposes:  Producing an offset voltage to compensate the threshold voltage of PWM current limit for providing over-power compensation. The offset is generated in accordance with the input voltage when the PWM switch is on.  Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley voltage switching and minimize the switching loss on the PWM switch.  Providing output over-voltage protection. A voltage comparator is built-in to the DET pin. The DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output OVP and this flat voltage is higher than 2.5 V, the controller enters auto recovery mode. 11 FB Feedback voltage pin. This pin is used to receive the output voltage / current level signal to determine PWM gate duty for regulating output voltage / current. The FB pin voltage can also activate open-loop, overload, and output-short circuit protection if the FB pin voltage is higher than a threshold of around 4.2 V for more than 50 ms. The input impedance of this pin is a 5 kΩ equivalent resistance. A one-third attenuator is connected between the FB pin and the input of the CSPWM/FB comparator. 12 RT Adjustable over-temperature protection. A constant current is flowed out of the RT pin. When the RT pin voltage is lower than 0.8 V (typical), the controller stops all PFC and PWM switching operation and enters auto recovery protection mode.

13 VIN

Line-voltage detection for brown-in / out protections. This pin can receive the AC input voltage level through a voltage divider. The voltage level of the VIN pin is not only used to control RANGE pin’s status; (ZCD) can also perform brown-in / out protection for AC input voltage UVP.

14 ZCD

Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching cycle. When the ZCD pin voltage is pulled to under 0.2 V (typical), it disables the PFC stage and the controller stops PFC switching. This can be achieved with an external circuit if disabling the PFC stage is desired.

15 NC No connection

16 HV High-voltage startup. HV pin is connected to the AC line voltage through a resistor 100 kΩtypical) for providing a high charging current to VDD capacitor.

© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL7921R • Rev. 1.1 6 FL7921R — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage 25 V VHV HV Pin Voltage 500 V VH OPFC, OPWM Pin Voltage -0.3 25.0 V VL Other Pins (INV, COMP, CSPFC, DET, FB, CSPWM, RT) -0.3 7.0 V VZCD Input Voltage to ZCD Pin -0.3 12.0 V PD Power Dissipation 800 mW JA Thermal Resistance (Junction-to-Air) 104 °C/W JC Thermal Resistance (Junction-to-Case) 41 °C/W TJ Operating Junction Temperature -40 +150 °C TSTG Storage Temperature Range -55 +150 °C TL Lead Temperature (Soldering 10 Seconds) +260 °C ESD Human Body Model, JESD22-A114 (All Pins Except HV Pin)(3) 5 kV Charged Device Model, JESD22-C101 (All Pins Except HV Pin)(3) 2 Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. 3. All pins including HV pin: CDM=0.5 kV, HBM=1 kV.

© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL7921R • Rev. 1.1 7 FL7921R — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller

Electrical Characteristics

VDD=15 V, TJ=-40°C ~125°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit VDD Section VOP Continuously Operating Voltage 25 V VDD-ON Turn-On Threshold Voltage 16.5 18.0 19.5 V VDD-PWM-OFF PWM-Off Threshold Voltage 9 10 11 V VDD-OFF Turn-Off Threshold Voltage TA=25°C 6.5 7.5 8.5 V IDD-ST Startup Current VDD=VDD-ON - 0.16 V, Gate Open 20 30 µA IDD-OP Operating Current VDD=15 V; OPFC, OPWM=100 kHz; CL-PFC, CL-PWM=2 nF 10 mA IDD-GREEN Green-Mode Operating Supply Current (Average) VDD=15 V, OPWM=450 Hz, CL-PWM=2 nF 5.5 mA IDD-PWM-OFF Operating Current at PWM-Off Phase VDD=VDD-PWM-OFF - 0.5 V 70 120 170 µA VDD-OVP VDD Over-Voltage Protection (Auto Recovery) 23 24 25 V tVDD-OVP VDD OVP De-bounce Time 100 150 200 µs IDD-LATCH CSPWM Pin Open Protection Latch-Up Holding Current VDD=7.5 V 120 μA HV Startup Current Source Section VHV-MIN Minimum Startup Voltage on HV Pin 50 V IHV Supply Current Drawn from HV Pin VAC=90 V (VDC=120 V), VDD=0 V 1.3 mA HV=500 V, VDD= VDD-OFF +1 V 1 µA VIN and RANGE Section VVIN-UVP Threshold Voltage for AC Input Under-Voltage Protection 0.95 1.00 1.05 V VVIN-RE-UVP Under-Voltage Protection Reset Voltage (for Startup) VVIN-UVP +0.25 V VVIN-UVP +0.30 V VVIN-UVP +0.35 V V tVIN-UVP Under-Voltage Protection Debounce Time (No Need at Startup and Hiccup Mode) 70 100 130 ms VVIN-RANGE-H High VVIN Threshold for RANGE Comparator 2.40 2.45 2.50 V VVIN-RANGE-L Low VVIN Threshold for RANGE Comparator 2.05 2.10 2.15 V tRANGE Range Enable / Disable Debounce Time 70 100 130 ms VRANGE-OL Output Low Voltage of RANGE Pin IO=1 mA 0.5 V IRANGE-OH Output High Leakage Current of RANGE Pin RANGE=5 V 200 nA tON-MAX-PFC PFC Maximum On-Time 22 25 28 µs Continued on the following page…

© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL7921R • Rev. 1.1 8 FL7921R — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Electrical Characteristics (Continued) VDD=15 V, TJ=-40°C ~125°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit PFC Stage Voltage Error Amplifier Section Gm Transconductance(4) 100 125 150 µmho VREF Feedback Comparator Reference Voltage 2.465 2.500 2.535 V VINV-H Clamp High Feedback Voltage RANGE=Open 2.70 2.75 2.80 V RANGE=Ground 2.60 2.65 2.70 VRATIO Clamp High Output Voltage Ratio(4) VINVH / VREF, RANGE=Open 1.06 1.14 V/V VINVH / VREF, RANGE=Ground 1.04 1.08 VINV-L Clamp Low Feedback Voltage 2.25 2.35 2.45 V VINV-OVP Over-Voltage Protection for INV Input RANGE=Open 2.90 2.95 V RANGE=Ground 2.75 2.80 tINV-OVP Over-Voltage Protection Debounce Time 50 70 90 µs VINV-UVP Under-Voltage Protection for INV Input 0.35 0.45 0.55 V tINV-UVP Under-Voltage Protection Debounce Time 50 70 90 µs VINV-BO PWM and PFC Off Threshold for Brownout Protection 1.15 1.20 1.25 V VCOMP-BO Limited Voltage on COMP Pin for Brownout Protection 1.55 1.60 1.65 V VCOMP Comparator Output High Voltage TA=25°C 4.8 6.0 V VOZ Zero Duty Cycle Voltage on COMP Pin 1.10 1.25 1.40 V ICOMP Comparator Output Source Current VINV=2.3 V, VCOMP=1.5 V 15 30 45 µA VINV=1.5 V, TA=25°C 0.50 0.75 1.00 mA Comparator Output Sink Current RANGE=Open, VINV=2.75 V, VCOMP=5 V, TA=25°C 20 30 40 µA RANGE=Ground, VINV=2.65 V, VCOMP=5 V 20 30 40 PFC Current-Sense Section VCSPFC Threshold Voltage for Peak Current Cycle-by-Cycle Limit VCOMP=5 V 0.82 V tPD Propagation Delay 110 200 ns tBNK Leading-Edge Blanking Time 110 180 250 ns AV CSPFC Compensation Ratio for THD 0.90 0.95 1.00 V/V Continued on the following page…

© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL7921R • Rev. 1.1 9 FL7921R — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Electrical Characteristics (Continued) VDD=15 V, TJ=-40°C ~125°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit PFC Output Section VZ PFC Gate Output Clamping Voltage VDD=25 V 14.0 15.5 17.0 V VOL PFC Gate Output Voltage Low VDD=15 V, IO=100 mA 1.5 V VOH PFC Gate Output Voltage High VDD=15 V, IO=100 mA 8 V tR PFC Gate Output Rising Time VDD=12 V, CL=3 nF, 20~80% 30 65 100 ns tF PFC Gate Output Falling Time VDD=12 V, CL=3 nF, 80~20% 30 50 70 ns PFC Zero-Current Detection Section VZCD Input Threshold Voltage Rising Edge VZCD Increasing 1.9 2.1 2.3 V VZCD-HYST Threshold Voltage Hysteresis VZCD Decreasing 0.25 0.35 0.45 V VZCD-HIGH Upper Clamp Voltage IZCD=3 mA 8 10 V VZCD-LOW Lower Clamp Voltage 0.40 0.65 0.90 V VZCD-SSC Starting Source Current Threshold Voltage 1.3 1.4 1.5 V tDELAY Maximum Delay from ZCD to Output Turn-On VCOMP=5 V, fS=60 kHz 50 200 ns tRESTART-PFC Restart Time 300 500 700 µs tINHIB Inhibit Time (Maximum Switching Frequency Limit) VCOMP=5 V 1.5 2.5 3.5 µs VZCD-DIS PFC Enable / Disable Function Threshold Voltage 0.14 0.20 0.26 V tZCD-DIS PFC Enable / Disable Function Debounce Time VZCD=100 mV 100 150 200 µs PWM STAGE Feedback Input Section AV Input-Voltage to Current-Sense Attenuation(4) AV=△VCSPWM /△VFB, ZFB Input Impedance FB>VG 3 5 7 kΩ IOZ Bias Current(4) FB=VOZ 1.2 2.0 mA VOZ Zero Duty-Cycle Input Voltage 0.7 0.9 1.1 V VFB-OLP Open-Loop Protection Threshold Voltage 3.9 4.2 4.5 V tFB-OLP Debounce Time for Open-Loop Protection 40 50 60 ms tFB-SS Internal Soft-Start Time(4) VFB=0 V~3.6 V 8 10 12 ms Continued on the following page…

© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL7921R • Rev. 1.1 10 FL7921R — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Electrical Characteristics (Continued) VDD=15 V, TJ=-40°C ~125°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit DET Pin OVP and Valley Detection Section VDET-OVP Comparator Reference Voltage 2.45 2.50 2.55 V Av Open-Loop Gain(4) 60 dB BW Gain Bandwidth(4) 1 MHz tDET-OVP Output OVP (Auto Recovery) Debounce Time 100 150 200 µs IDET-SOURCE Maximum Source Current VDET=0 V 1 mA VDET-LOW Lower Clamp Voltage IDET=1 mA -0.5 -0.3 -0.1 V tVALLEY-DELAY Delay from Valley Signal Detected to Output Turn-on(4) 150 200 250 ns tOFF-BNK Leading-Edge Blanking Time for DET-OVP (2.5 V) and Valley Signal when PWM MOSFET Turns Off(4) 3 4 5 µs tTIME-OUT Time-Out After tOFF-MIN 8 9 10 µs PWM Oscillator Section tON-MAX-PWM Maximum On Time 38 45 52 µs tOFF-MIN Minimum Off-Time VFB≧VN, TA=25°C 7 8 9 µs VFB=VG 32 37 42 VN Beginning of Green-On Mode at FB Voltage Level TA=25°C 1.95 2.10 2.25 V VG Beginning of Green-Off Mode at FB Voltage Level TA=25°C 1.00 1.15 1.30 V ΔVG Hysteresis for Beginning of Green-Off Mode at FB Voltage Level 0.1 V tSTARTER-PWM Start Timer (Time-Out Timer) VFB ＜VG, TA=25°C 1.85 2.25 2.65 ms VFB ＞VFB-OLP, TA=25°C 22 28 34 µs PWM Output Section VCLAMP PWM Gate Output Clamping Voltage VDD=25 V 16.0 17.5 19.0 V VOL PWM Gate Output Voltage Low VDD=15 V, IO=100 mA 1.5 V VOH PWM Gate Output Voltage High VDD=15 V, IO=100 mA 8 V tR PWM Gate Output Rising Time CL=3 nF, VDD=12 V, 20~80% 80 110 ns tF PWM Gate Output Falling Time CL=3 nF, VDD=12 V, 20~80% 40 70 ns Continued on the following page…

© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL7921R • Rev. 1.1 11 FL7921R — Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Electrical Characteristics (Continued) VDD=15 V, TJ=-40°C ~125°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit Current Sense Section tPD Delay to Output 150 200 ns VLIMIT Limit Voltage on CSPWM Pin for Over-Power Compensation IDET ＜75 µA, TA=25°C 0.81 0.84 0.87 V IDET=185 µA, TA=25°C 0.69 0.72 0.75 IDET=350 µA, TA=25°C 0.55 0.58 0.61 VSLOPE Slope Compensation(4) tON=45 µs, RANGE=Open 0.25 0.30 0.35 V tON=0 µs 0.05 0.10 0.15 tON-BNK Leading-Edge Blanking Time 300 ns VCS-FLOATING CSPWM Pin Floating VCSPWM Clamped High Voltage CSPWM Pin Floating 4.5 5.0 V VCS-OV CSPWM Pin Open Protection(4) 3 V tCS-H Delay with CSPWM Pin Floating CSPWM Pin Floating 100 150 200 µs RT Pin Over-Temperature Protection Section TOTP Internal Threshold Temperature for OTP(4) 125 140 155 °C TOTP-HYST Hysteresis Temperature for Internal OTP(4) 30 °C IRT Internal Source Current of RT Pin 90 100 110 µA VRT-REC Auto Recovery-Mode Triggering Voltage 0.75 0.80 0.85 V VRT-RE-REC Auto Recovery-Mode Release Voltage VRT-REC +0.15 VRT-REC +0.20 VRT-REC +0.25 V VRT-OTP-LEVEL Threshold Voltage for Two-level Debounce Time 0.45 0.50 0.55 V tRT-OTP-H Debounce Time for OTP 10 ms tRT-OTP-L Debounce Time for Externally Triggering VRT<VRT-OTP-LEVEL, TA=25°C 70 110 150 µs Note: 4. Guaranteed by design.

Figure 45. FB Pin Open-Loop, Short Circuit, and voltage is pulled to high level by internal bias voltage. the FB pin protection is activated. current until V DD voltage reaches the turn-on voltage. turn-off voltage VDD-PWM-OFF.

PIN #1 FRONT VIEW TOP VIEW SEE DETAIL A SEATING PLANE C GAGE PLANE DETAIL A SCALE: 2:1 B A 6.00 8.89 4.00 3.80 10.00 9.80 (0.30) 1.27 0.25 0.05

1.75 MAX

0.25 0.19 0.36 0.50 0.25 R0.10 R0.10 0.90 0.50 (1.04)

0.25 C B A

0.10 C NOTES: A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AC, ISSUE C. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-2009 E) LANDPATTERN STANDARD: SOIC127P600X175-16AM F) DRAWING FILE NAME: M16AREV13. LAND PATTERN RECOMMENDATION 0.51 0.31 1.50 1.25 3.85 7.35 1.27 0.65 1.75 8.89

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