FL73282 ONSEMI | Alldatasheet
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© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL73282 • Rev.1.0 FL73282 — Half-Bridge Gate Driver FL73282 Half-Bridge Gate Driver
Features
Floating Channel for Bootstrap Operation to +900 V Typically 350 mA / 650 mA Sourcing/Sinking Current Driving Capability for Both Channels Common-Mode dv/dt Noise Canceling Circuit Extended Allowable Negative VS Swing to -9.8 V for Signal Propagation at VCC=VBS=15 V VCC & VBS Supply Range from 10 V to 20 V UVLO Functions for Both Channels Matched Propagation Delay Below 50 ns Built-in 170 ns Dead-Time Output in Phase with Input Signal
Applications
Fluorescent Lamp Ballast HID Ballast SMPS Motor Driver General Purpose Half Bridge Topology
Description
The FL73282, a monolithic half bridge gate-drive IC, can drive MOSFETs and IGBTs that operate up to +9 00 V. Fairchild’s high -voltage process and common mode noise canceling technique provides stable operation o f the high-side driver under high-dV S/dt noise circumstances. An advanced level-shift circuit allows high-side gate driver operation up to V S=-9.8 V (typical) for V BS=15 V. The UVLO circuits for both channels prevent malfunction when V CC or VBS is lower than the specified threshold voltage. Output drivers typically source/sink 350 mA / 650 mA, respectively, which is suitable for all kinds of half- and full-bridge inverters. Figure 1. SOP 8
Ordering Information
Part Number Operating Temperature Range Package Packing Method FL73282MX(1) -40°C to +125°C 8-Lead, Small Outline Integrated Circuit, (SOIC) Tape & Reel Note: 1. These devices passed wave-soldering test by JESD22A-111.
Figure 4. Pin Assignments (Top View)
1 VCC I Low-Side Supply Voltage
2 HIN I Logic Input for High-Side Gate Driver Output
3 LIN I Logic Input for Low-Side Gate Driver Output
4 COM Logic Ground and Low-Side Driver Return
5 LO O Low-Side Driver Output
6 VS I High-Voltage Floating Supply Return
7 HO O High-Side Driver Output
8 VB I High-Side Floating Supply
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL73282 • Rev.1.0 4 FL73282 — Half-Bridge Gate Driver Absolute Maximum Ratings Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VS High-Side Floating Offset Voltage VB-24 VB+0.3 V VB High-Side Floating Supply Voltage -0.3 924.0 V VCC Low-Side and Logic-Fixed Supply Voltage -0.3 24 V VHO High-Side Floating Output Voltage VHO VS-0.3 VB+0.3 V VLO Low-Side Floating Output Voltage VLO -0.3 VCC+0.3 V VIN Logic Input Voltage (HIN, LIN) -0.3 VCC+0.3 V COM Logic Ground VCC-24 VCC+0.3 V dVS/dt Allowable Offset Voltage Slew Rate ±50 V/ns PD (3)(4)(5) Power Dissipation 0.625 W θJA Thermal Resistance 200 °C/W TJ Junction Temperature 150 °C TSTG Storage Temperature -55 150 °C Notes: 3. Refer to the following standards: JESD51-2: Integral circuit’s thermal test method environmental conditions, natural convection; JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages. 4. Do not exceed maximum power dissipation (P D) under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the condi tions for actual device operation. Recommended operating conditions are specified to ensure optimal perfo rmance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VB High-Side Floating Supply Voltage VS+10 VS+20 V VS High-Side Floating Supply Offset Voltage 6-VCC 900 V VHO High-Side (HO) Output Voltage VS VB V VLO Low-Side (LO) Output Voltage COM VCC V VIN Logic Input Voltage (HIN, LIN) COM VCC V VCC Low-Side Supply Voltage 10 20 V TA Ambient Temperature -40 +125 °C
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL73282 • Rev.1.0 5 FL73282 — Half-Bridge Gate Driver Static Electrical Characteristics VBIAS(VCC, VBS) = 15.0 V, T A = 25°C, unless otherwise specified. The V IN and IIN parameters are referenced to COM. The VO and IO parameters are referenced to VS and COM and are applicable to the respective outputs HO and LO. Symbol Parameter Condition Min. Typ. Max. Unit Power Supply Section IQCC Quiescent VCC Supply Current VIN=0 V or 5 V 80 180 A IQBS Quiescent VBS Supply Current VIN=0 V or 5 V 50 120 A IPCC Operating VCC Supply Current fIN=20 kHz, rms value 550 A IPBS Operating VBS Supply Current fIN=20 kHz, rms value 600 A ILK Offset Supply Leakage Current VB=VS=900 V 10 A Bootstrapped Supply Section VCCUV+ VBSUV+ VCC & VBS Supply Under-Voltage Positive going Threshold 8.2 9.2 10.0 V VCCUV- VBSUV- VCC & VBS Supply Under-Voltage Negative going Threshold 7.6 8.7 9.6 V VCCUVH VBSUVH VCC Supply Under-Voltage Lockout Hysteresis 0.5 V Input Section VIH Logic "1" Input Voltage 2.5 V VIL Logic "0" Input Voltage 0.8 V IIN+ Logic "1" Input Bias Current VIN=5 V 20 50 A IIN- Logic "0" Input Bias Current VIN=0 V 1.0 2.0 A RIN Logic Input Pull-Down Resistance 100 250 K Gate Driver Output Section VOH High-Level Output Voltage, VBIAS-VO IO=0 A 85 mV VOL Low-Level Output Voltage, VO IO=0 A 85 mV IO+ Output HIGH Short-Circuit Pulsed Current VO=0 V,VIN=5 V with PW≤10 μs 250 350 mA IO- Output LOW Short-Circuit Pulsed Current VO=15 V,VIN=0 V with PW≤10 μs 500 650 mA VS Allowable Negative VS Pin Voltage for HIN Signal Propagation to HO -9.8 -7.0 V
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL73282 • Rev.1.0 6 FL73282 — Half-Bridge Gate Driver Dynamic Electrical Characteristics VBIAS(VCC, VBS) = 15.0 V, VS = COM, CL = 1000 pF and TA= 25°C, unless otherwise specified.. Symbol Parameter Conditions Min. Typ. Max. Unit tON Turn-On Propagation Delay VS=0 V 80 150 220 ns tOFF Turn-Off Propagation Delay VS=0 V or 900 V(5) 80 150 220 ns tR Turn-On Rise Time VLIN=VHIN=5 V 60 140 ns tF Turn-Off Fall Time VLIN=VHIN=0 V 30 80 ns DT Dead Time 70 170 270 ns MT Delay Matching, HS & LS Turn-on/off 50 ns tPW Minimum Input Pulse Width that changes the Output(5)(6) 220 ns Notes: 5. These parameters are guaranteed by design. 6. The minimum input pulse width time included dead time
Figure 36. Internal Dead Time Definition
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