FL3100T ONSEMI | Alldatasheet
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© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL3100T • Rev.1.0 FL3100T — Low-Side Gate Driver with PWM Dimming Control for Smart LED Lighting FL3100T Low-Side Gate Driver with LED PWM Dimming Control for Smart LED Lighting
Features
Non-inverting Input Logic with DIM Control Input for PWM Dimming Down to 0.1% for Hybrid Dimming 4.5 to 18 V Operating Range TTL Inputs Independent of Supply Voltage 2.5 A Sink / 1.8 A Source at VOUT = 6 V Internal Resistors Turn Driver Off If No Inputs 13 ns Typical Rise Time and 9 ns Typical Fall-Time with 1 nF Load MillerDrive™ Technology Typical Propagation Delay Time Under 20 ns with Input Falling or Rising 6-Lead, 2 x 2 mm MLP or 5-Pin, SOT23 Packages Rated from -40°C to 125°C Ambient
Applications
Smart LED Drivers with Accurate PWM Dimming General LED Lighting
Description
The FL3100T 2 A gate driver is designed to drive an N- channel enhancement-mode MOSFET in low-side switching applications by providing high peak current pulses during the short switching intervals. The FL3100T has two inputs that can be configured to operate in non-inverting (IN) mode with a DIM pin for PWM dimming control of the LED Driver . High accuracy PWM dimming control required in smart LED drivers is possible by adjusting the duty ratio of the DIM input. If one or both inputs are left unconnected, internal resistors bias the inputs such that the output is pulled LOW to hold the power MOSFET off. The driver is available with fixed TTL input thresholds. Internal circuitry provides an under-voltage lockout function by holding the output LOW until the supply voltage is within operating range . The FL3100T delivers fast MOSFET switching performance, which helps maximize efficiency in high-frequency LED driver designs. The FL3100T is available in a 5-pin, SOT23 or a 2 x 2 mm, 6-lead, Molded Leadless Package (MLP) for the smallest size with excellent thermal performance. Typical Application Circuit VDDFL3100T ILED MCU IN DIM OUT Figure 1. LED PWM Dimming Application Circuit for Smart LED Lighting
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL3100T • Rev.1.0 2 FL3100T — Low-Side Gate Driver with PWM Dimming Control for Smart LED Lighting
Ordering Information
Part Number Package Packing Method Quantity / Reel FL3100TMPX 6-Lead, 2 x 2 mm MLP Tape & Reel 3000 FL3100TSX 5-Pin, SOT23 Tape & Reel 3000 Block Diagrams DIM 4
1 VDD
5 OUT
2 GND
VDD_OK IN 3 100k 100k 100k Figure 2. Simplified Block Diagram (SOT23 Pin-out)
3 VDD
4 OUT
5 PGND
Figure 3. Simplified Block Diagram (MLP Pin-out)
Figure 4. 6-Lead MLP (Top View) Figure 5. SOT23-5 (Top View) 1 3 VDD Supply Voltage. Provides power to the IC. 2 AGND Analog ground for input signals (MLP only). Connect to PGND underneath the IC. 2 GND Ground (SOT-23 only). Common ground reference for input and output circuits. to AGND or PGND to enable regular operation of the output. electrically connected to pin 5.
- Default input signal if no external connection is made.
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL3100T • Rev.1.0 4 FL3100T — Low-Side Gate Driver with PWM Dimming Control for Smart LED Lighting Thermal Characteristics(2) Package JL (3) JT (4) JA (5) Unit 6-Lead, 2 x 2 mm Molded Leadless Package (MLP) 2.7 133.0 58.0 °C/W SOT23-5 56 99 157 °C/W Notes: 2. Estimates derived from thermal simulation; actual values depend on the application. 3. Theta_JL ( JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. 4. Theta_JT ( JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 5. Theta_JA ( ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink using a 2SP2 board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dama ge the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD VDD to PGND -0.3 20.0 V VIN Voltage on IN and DIM to GND, AGND, or PGND GND - 0.3 VDD + 0.3 V VOUT Voltage on OUT to GND, AGND, or PGND GND - 0.3 VDD + 0.3 V TL Lead Soldering Temperature (10 Seconds) +260 ºC TJ Junction Temperature -55 +150 ºC TSTG Storage Temperature -65 +150 ºC Recommended Operating Conditions The Recommended Operating Conditions table defines the condi tions for actual device operation. Recommended operating conditions are specified to ensure optimal perfo rmance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VDD Supply Voltage Range 4.5 18.0 V VIN Input Voltage IN, DIM 0 VDD V TA Operating Ambient Temperature -40 +125 ºC
© 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FL3100T • Rev.1.0 5 FL3100T — Low-Side Gate Driver with PWM Dimming Control for Smart LED Lighting
Electrical Characteristics
Unless otherwise noted, V DD = 12 V, T J = -40°C to + 125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit Supply VDD Operating Range 4.5 18.0 V IDD Supply Current Inputs/ EN Not Connected 0.50 0.80 mA VON Turn-On Voltage 3.5 3.9 4.3 V VOFF Turn-Off Voltage 3.3 3.7 4.1 V Inputs VINL_T IN, DIM Logic LOW Voltage, Maximum 0.8 V VINH_T IN, DIM Logic HIGH Voltage, Minimum 2.0 V IIN Non-inverting Input IN from 0 to VDD -1 175 µA IDIMim DIM Input IN from 0 to VDD -175 1 µA VHYS IN, DIM Logic Hysteresis Voltage 0.2 0.4 0.8 V Output ISINK OUT Current, Mid-Voltage, Sinking(6) OUT at VDD/2, CLOAD = 0.1 µF, f = 1 kHz 2.5 A ISOURCE OUT Current, Mid-Voltage, Sourcing(6) OUT at VDD/2, CLOAD = 0.1 µF, f = 1 kHz -1.8 A IPK_SINK OUT Current, Peak, Sinking(6) CLOAD = 0.1 µF, f = 1 kHz 3 A IPK_SOURCE OUT Current, Peak, Sourcing(6) CLOAD = 0.1 µF, f = 1 kHz -3 A tRISE Output Rise Time(7) CLOAD = 1000 pF 13 20 ns tFALL Output Fall Time(7) CLOAD = 1000 pF 9 14 ns tD1, tD2 Output Prop. Delay, TTL Inputs(7) 0 – 5 VIN; 1 V/ns Slew Rate 9 16 30 ns IRVS Output Reverse Current Withstand(6) 500 mA Notes: 6. Not tested in production. 7. See Timing Diagrams of Figure 6 and Figure 7.
Figure 6. IN P in Figure 7. DIM P in
LED in MCU-driven hybrid dimming applications. in a closed loop LED driver stage. command the PWMlight dimming on the LED current, i.e. on the LED current is possible. Figure 29. LED PWM Dimming Application a possible implementation for mixed mode dimming. Figure 30. LED Current with PWM Dimming the rise time from 0 to 3.3 V should be 550 ns or less. retrigger the driver input, causing erratic operation.
3.9 V operational level, this circuit holds the output
MOSFET on with VDD below 3.9 V.
Thermal Characteristics table. characterization parameter JB = 51°C/W. reduction for increased reliability. Figure 35. Smart LED Driver using the MCU and FL3100T in the Buck DC-DC Stage
0.05 C 0.05 C 2.0 2.0 PIN#1 IDENT A B SIDE VIEW RECOMMENDED LAND PATTERN BOTTOM VIEW SEATING PLANE 1 3 PIN #1 IDENT 0.65 1.30 1.21 0.52(6X) 0.90 0.42(6X)0.65 2.25 1.68 (0.40) (0.70) NOTES: A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC MO-229 REGISTRATION B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. D. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. E. DRAWING FILENAME: MKT-MLP06Krev5. (0.20)4X
0.10 C A B
0.05 C (6X) (6X) (0.60) 0.08 C
0.10 C
C 1.72 0.15
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