FER5VC4S1 FUTUREWAFER | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 1
Technical content
Extra Low Capacitance for Integrated ESD Mechanical Data Notes Dice size AX:600um,BX:420um/P1,3,4,6-85*95um/Pin 5-270*105um Wafer size 4” (Gross die:27,500pcs/Good die>25,575pcs) Chip Thickness (A)138um±12um (B)470um±20um Scribe line width 60um Top metal Al/Au/Ag Back side metal Al/Au/Ag/Sn Parameter Symbol Conditions Value Unit Reverse stand-off voltage VRWM 5.0 V Peak pulse power PPP Tp=8/20us 150 W Peak pulse current IPP Tp=8/20us 5.0 A Electrostatic discharge VESD IEC61000-4-2 Level 4 ±15(AIR) KV Max.junction temp. Tj +150 ℃ Parameter Symbol Condition Min. Typ. Max. Unit Breakdown voltage VBR IT=1mA Pin 5 to 2 6.1 8.0 8.5 V Reverse leakage current IR VR=5V Pin 1,3,4,5,6 to 2 0.9 uA Forward Voltage VF 1F=15mA Pin2 to Pin1,3,4,5,6 0.95 V Clamping Voltage VC IPP=1A IPP=5A 15.0 28.0 V Diode capacitance I/O-GND CI/O-GND VR=0V f=1MHZ 0.8 pf Diode capacitance I/O-I/O CI/O-I/O VR=0V f=1MHZ 0.4 pf Characteristics TA=25℃ Notes: (1)sampling testing:no bad dice inking/guaranteed good die >93% (2)Testing follow customer (3)Tj=Ta+Rth(j-a)*(pf+pr),where Rth(j-a)-thermal resistance,Pf-forward power dissipation, Pr-revers power dissipation (4)**For device testing Futurewafer Technology Co.,Ltd www.futurewafer.com.tw+886-3-3573583 FER5VC4S1 EW1608A5-FW-A