FEDL62Q2500

Rohm

16-bit micro controller

Manufacturer: Rohm

Document: 40 Pages / 1Mb

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FEDL62Q2500 ROHM | Alldatasheet

Document overview

Manufacturer or author: LAPIS Technology Co., Ltd.
PDF pages: 40

Technical content

Issue Date: Feb 2, 2023 ML62Q2500 Group 16-bit micro controller GENERAL DESCRIPTION ML62Q2500 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and integrated with program memory(Flash memory), data memory(RAM), data Flash (Erase unit:128byte, Write unit:1byte) and rich peripheral functions such as the multiplier/divider, CRC generator, Clock generator, Timer, General Purpose Ports, UART, Synchronous serial port, I2C bus interface unit(Master, Slave), Voltage Level Supervisor(VLS), Successive approximation type 12bit A/D converter, Safety function (IEC60730/60335 Class B) and so on. The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline architecture parallel processing. The built-in on-chip debug function enables debugging and programming the software. Also, ISP (In-System Programming) function supports the Flash programming in production line. The ML62Q2500 Group has products as show in the Table1 with multiple package and memory size combinations. Table 1 Product List Program memory Data memory (RAM) Data Flash 32pin TQFP32 WQFN32 40pin WQFN40 48pin TQFP48 WQFN48 128Kbyte 8Kbyte 4Kbyte ML62Q2504 ML62Q2524 ML62Q2534 64Kbyte ML62Q2502 ML62Q2522 ML62Q2532 Please see the last 2 pages “Notes for product usage” and “Notes” in this document on use with this product .

FEATURES

 CPU – 16-bit RISC CPU : nX-U16/100 (A35 core) – Instruction system : 16-bit length instructions – Instruction set : Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on – Built-in On-chip debug function (connect to the Lapis Technolofy on-chip debug emulator) – Minimum instruction execution time : 1 count of system clock Approximately 30.5 μs/62.5ns/41.6ns (at 32.768 kHz/16 MHz/24MHz system clock)  Coprocessor for multiplication and division – Signed or Unsigned is selectable Parameter Expression Operation time [cycle] Multiplication 16bit × 16bit 4 Division 32bit ÷ 16bit 8 32bit ÷ 32bit 16 Multiply-accumulate (non-saturating, non-saturating) 16bit × 16bit + 32bit 4  Operating voltage and temperature – Operating voltage : VDD = 1.8 to 5.5 V – Operating temperature : -40 °C to +105 °C  Flash memory Parameter Program memory area Data Flash memory area Erase/Write count 100 cycles 10,000 cycles Write unit 32bit(4byte) 8bit(1byte) Erase unit 16Kbyte/1Kbyte all area/128byte Erase/Write temperature 0 °C to +40 °C -40 °C to +85 °C – Background Operation (CPU can work while erasing and rewriting to the Data Flash memory area.) – The built-in on-chip debug function and ISP (In-System Programming) function enable Flash programming  Data RAM area – Rewrite unit: 8bit/16bit (1byte/2byte) – Parity check function is available (interrupt or reset is generatable at Parity error)  Clock generation circuit – Low-speed clock (LSCLK) Internal low-speed RC oscillation (RC32K) : Approximately 32.768 kHz External low-speed clock input (EXT32K) : Approximately 32.768 kHz External low-speed crystal oscillation (XT32K) : Approximately 32.768 kHz, 4 selectable crystal oscillation mode (Tough, Normal, Low power mode, and Ultra low power mode) – High-speed clock (HSCLK) PLL oscillation: 3 selectable oscillation frequency (24MHz ,16MHz and 1MHz) by code option – Watch Dog Timer (WDT): built-in independent clock for WDT (RC1K: Approximately 1.024kHz) – High-speed time base clock (HTBCLK) Generates a clock with a period of 2 to 8 times that of HSCLK as a peripheral clock.  Reset – System Resets by reset input pin, Power-On Reset, voltage level supervisor (VLS), WDT overflow, WDT invalid clear, RAM parity error, and PC error (unused ROM area access (instruction access) ) – Software reset by BRK instruction (reset CPU only) – Reset the peripherals individually/collectively by software This product uses Super Flash® technology licensed from Silicon Storage Technology, Inc. Super Flash® is a registered trademark of Silicon Storage Technology, Inc.

 Power management – Optimal power management with various standby modes – STOP/STOP-D mode(All clocks are stopped), HALT-D mode(clocks for System and part of the periferal block are stopped), HALT/HALT-H mode(clocks for System are stopped) – HALT-D mode is suitable for long term standby, HALT-H mode is suitable for short term Intermittent operation standby – Indivisual clock input controll to the peripheral blocks by software – High-speed clock frequency(HSCLK) is configurable (1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of PLL clock, Max 7steps) – Clock gear: High-speed system clock frequency is changeable dynamically (1/1, 1/2, 1/4, 1/8, 1/16, 1/32 of HSCLK, Max 6steps)  Interrupt controller – Non-maskable interrupt source : 1 (Internal sources: WDT) – Maskable interrupt sources : 34 (included the external interrupt 8 sources) – Four step interrupt levels – External interrupt ports : 8 (selectable from max.24 pins) with sampling filter and edge(rise, fall, both) selection.  General-purpose ports (GPIO) – I/O port : Max. 40 (Including pins for shared functions) – Input port : Max. 3 (Including one pin for shared on-chip debug and two pins for shared low speed crystal oscillation) – Carrier frequency output function (for IR communication)  Watchdog timer (WDT) : 1 channel – Overflow period : 8selectable (7.8，15.6，31.3，62.5，125，500，2000，8000[ms]) – Selectable window function (enable or disable): configurable clear enable period (50% or 75% of overflow period) with invalid clear. When disable, Interrupts the first overflow and resets the second overflow. When enable, reset occurs for the first overflow. – Selectable WDT operation : select Enable or Disable by code option – Selectable operation in HALT/HALT-H mode and HALT-D mode(Continue counting/Stop counting) – Readable WDT counter: WDT counter monitor function  Low-speed Time base counter(LTBC) : 2 channels – Generate 8 frequency (128，64，32，16，8，4，2，1[Hz]) internal pulse signals by dividing the Low-speed clock (LSCLK) – 4 interrupts are generatable from 8 different frequencys internal pulse signals – One of internal pulse signals selected to interrupt can be output from general purpose port (TBCO)  Functional timer : 2 channels – Various modes (Continuous, One shot, capture, PWM with the same period and different duties, and complementary PWM output with the dead time) – Event trigger (external terminal, 16bit timer, functional timer, LTBC, RC1K) – Selectable counter clock from various sources (divided by 1 to 8 of LSCLK, HSCLK, HTBCLK, external clock)  16-bit General timers : 6 channels – Timer output (toggled by overflow) – Selectable counter clock from various sources (divided by 1 to 8 of LSCLK, HSCLK, HTBCLK, LTBC, RC1K, and external clock) – Timer X is shared with waiting for the stability of low-speed crystal oscillation  Synchronous Serial Port : 2 channels (with FIFO: 1channel, without FIFO: 1channel) – FIFO: 4steps for each transmitting and receiving – Selectable from Master and Slave – Selectable from LSB first or MSB first – Selectable 8-bit length or 16-bit length

 UART (Full-duplex communication mode): 3 channels – Selectable from 5 to 8bit length, parity or no parity, odd parity or even parity, 1 stop b it or 2 stop bits, Positive logic or Negative logic, LSB first or MSB first – Sampling filter for receiving data and start bit – Built-in baud rate generator (HSCLK@16MHz: 4800bps to 920kbps, LSCLK: up to 2400bps)  I2C bus : 2 channels – Select from Master mode or Slave mode: 1channel. Master mode only: 1channel – Standard mode (100 kbps), fast mode (400 kbps) and 1Mbps mode(1Mbps) – 7bit address format – Master mode: Handshake (Clock synchronization), 10bit slave address format is supported – Slave mode: Clock stretch function,  • Successive approximation type 12bit A/D converter (SA-ADC) : input 14 channels – Conversion time: Min. 1.375μs / ch (When the VDD is higher than 2.7V and the conversion clock is 16MHz) – Reference voltages are selectable from VDD pin input voltage or External reference voltage (VREF pin) – dedicated result register for each channel – Continuous conversion, Trigger start, Interrupt determining by upper limit or lower limit threshold of conversion result  Voltage Level Supervisor (VLS) : 1 channel – Threshold voltage: 15 selectable (from 1.85V to 4.00V) – Functional Voltage level detection reset (VLS reset) or Functional Voltage level detection interrupt (VLS0 interrupt) is generatable – Equipped with single mode / with sampling filter / low consumption operation  CRC (Cyclic Redundancy Check) generator – Generation equation: X16+X12+X5+1 – Selectable from LSB first or MSB first – Built-in Automatic program memory CRC calculation mode in HALT mode  Safety Function – Automatic switching to the internal low-speed RC oscillation in case the low-speed crystal oscillation stopped – RAM/SFR guard – Automatic program memory CRC calculation – RAM parity error detection – ROM unused area access reset (instruction access) – Clock mutual monitoring, WDT counter monitoring – SA-ADC test – Communication loop back test (UART, Synchronous serial port, I2C bus(master)) – GPIO test  Shipping package Package Body size (including lead) [mm × mm] Pin pitch [mm] Product name 32 pin plastic WQFN 5.0 × 5.0 ( - ) 0.50 ML62Q2502/2504-xxxGD 40 pin plastic WQFN 6.0 × 6.0 ( - ) 0.50 ML62Q2522/2524-xxxGD 48 pin plastic WQFN 7.0 × 7.0 ( - ) 0.50 ML62Q2532/2534-xxxGD xxx: ROM code number, (NNN: ROM code is blank)

How To Read The Part Number Figure 1 Part Number ML 62 Q 25 3 4 – xxx TB Package Type GD : WQFN TB : TQFP ROM Code Number NNN : Blank XXX : Custom Code Number Program Memory Size 2 : 64KB 4 : 128KB Pin Count 0 : 32 2 : 40 3 : 48 Group Name 25 : 2500 Group Program Memory Type Q : Flash Memory CPU Type 62 : 16bit CPU nX-U16/100 LAPIS Technology Logic Product

Table 2 Main Function List Part number Pin Interrupt Timer Communication Analog Total pin Power pin Reset Input pin Debug Input port Input port *1 I/O port (LED drive is supported) External interrupt pin External interrupt source Non maskable interrupt source Internal maskable interrupt source 16bit Timer [ch] 16bit Functional Timer [ch] 16bit Functional Timer [Port] Watchdog Timer [ch] Time base counter [ch] Synchronous serial (without FIFO) [ch] Synchronous serial (with FIFO) [ch] Full-duplex UART [ch] I2C bus interface (Master only) [ch] I2C bus unit (Master/Slave) [ch] 12bit Successive type A/D converter [ch] Voltage Level Supervisor [ch] ML62Q2502 32 3 1 1 3 24 16 8 1 26 6 2 4 1 2 1 1 3 1 1 14 1 ML62Q2504 ML62Q2522 40 32 19 ML62Q2524 ML62Q2532 48 40 24 ML62Q2534 *1: Shared with pins for crystal oscillation and debug input.

*1 : Not available as the input port when connecting to the on-chip debug emulator. *2 : Not available as the input port when connecting to the crystal resonator. EPSW1～3 PSW Timing Controller UART Unit ALU GREG 0 ～15 Instruction Decoder ELR1～3 LR EA SP Instruction Register ECSR1～3 DSR/CSR PC BUS Controller CPU（nX-U16/100） On-Chip ICE / ISP Program Memory （FLASH） SCKF0 SDIF0 SDOF0 SSNF0 RAM Interrupt WDT VLS I2C Bus Unit SDAU0 SCLU0 16-bit Timer TMOn Functional Timer FTOn FTOnN GPIO (External Interrupt) P02~P73 P00 *1 PI0,PI1 *2 EXI 0-7 Power Circuit VDD VSS VDDL TEST1_N TEST0 Clock Generation Circuit LCKO HCKO Low-speed RC Oscillation Low-speed Crystal Oscillation XT0 XT1 RC1K Oscillation SA-ADC VREF AINn Low Speed Time Base Counter TBCO CRC Generator Data FLASH Safety Function Reset Function Multiplier/Divider (Coprocessor) FLASH Controller SSIO Unit RX D0 TXD 0 RX D1 TXD 1 RX D2 TXD 2 INT INT INT INT INT INT INT INT INT INT INT INT RESET_N SDAM0 SCLM0 SCLK0 SIN0 SOUT0

Fig.3-1 48 pin TQFP P62 TMO4 P61 EXI7 TMO3 P60 EXI6 TMO2 P27 EXI2 TBCO AIN7 P26 SIN0 AIN6 P25 SOUT0 SDAU0 AIN5 P24 SCLK0 SCLU0 AIN4 P23 SSNF0 SDAM0 FTO1N AIN3 P22 SDIF0 SCLM0 FTO1 AIN2 P21 SDOF0 TXD0 FTMO0N AIN1 * P20 SCKF0 RXD0 FTO0 AIN0 P17 TBCO 36 35 34 33 32 31 30 29 28 27 26 25 VREF FTO0 RXD0 SCLK0 EXI4 P30 ▉ 37 24 ▉P13 SSNF0 FTO1N TMOX AIN13 AIN8 FTO0N TXD0 SOUT0 EXI5 P31 ▉ 38 23 ▉P12 EXI7 SDIF0 FTO1 TMO4 AIN9 FTO1 RXD1 SIN0 EXI6 P32 ▉ 39 22 ▉P11 EXI6 SDOF0 TXD2 FTO0N TMO3 LCKO * AIN10 FTO1N TXD1 EXI7 P33 ▉ 40 21 ▉P10 EXI5 SCKF0 RXD2 FTO0 TMO2 HCKO EXI0 P34 ▉ 41 20 ▉P07 EXI4 TXD1 HCKO * EXI1 P35 ▉ 42 19 ▉P06 EXI3 SIN0 RXD1 TMO4 EXI2 P36 ▉ 43 18 ▉P05 EXI2 SOUT0 TXD0 TMO3 EXI3 P37 ▉ 44 17 ▉P04 EXI1 SCLK0 RXD0 TMO2 AIN11 TMO2 FTO0 SCLU0 P70 ▉ 45 16 ▉P57 FTO1N AIN12 LCKO TMO3 FTO0N SDAU0 P71 ▉ 46 15 ▉P56 FTO1 TMO4 FTO1 SCLM0 RXD2 EXI0 P72 ▉ 47 14 ▉P55 FTO0N * TBCO TMOX FTO1N SDAM0 TXD2 EXI3 P73 ▉ 48 13 ▉P54 FTO0 1 2 3 4 5 6 7 8 9 10 11 12 EXI1 PI0 XT0 EXCK PI1 XT1 VDD VSS VDDL RESET_N TEST1_N EXI0 TEST0 P00 RXD1 P02 LCKO TXD1 P03 RXD0 EXI4 P52 TXD0 EXI5 P53 *: キャリア周波数出力対応 ML62Q253x TQFP48 (Top View) *: Supported Carrier frequency output

Fig.3-2 48 pin WQFN P62 TMO4 P61 EXI7 TMO3 P60 EXI6 TMO2 P27 EXI2 TBCO AIN7 P26 SIN0 AIN6 P25 SOUT0 SDAU0 AIN5 P24 SCLK0 SCLU0 AIN4 P23 SSNF0 SDAM0 FTO1N AIN3 P22 SDIF0 SCLM0 FTO1 AIN2 P21 SDOF0 TXD0 FTMO0N AIN1 * P20 SCKF0 RXD0 FTO0 AIN0 P17 TBCO 36 35 34 33 32 31 30 29 28 27 26 25 VREF FTO0 RXD0 SCLK0 EXI4 P30 37 ▉24 P13 SSNF0 FTO1N TMOX AIN13 AIN8 FTO0N TXD0 SOUT0 EXI5 P31 38 ▉23 P12 EXI7 SDIF0 FTO1 TMO4 AIN9 FTO1 RXD1 SIN0 EXI6 P32 39 ▉22 P11 EXI6 SDOF0 TXD2 FTO0N TMO3 LCKO * AIN10 FTO1N TXD1 EXI7 P33 40 ▉21 P10 EXI5 SCKF0 RXD2 FTO0 TMO2 HCKO EXI0 P34 41 ▉20 P07 EXI4 TXD1 HCKO * EXI1 P35 42 ▉19 P06 EXI3 SIN0 RXD1 TMO4 EXI2 P36 43 ▉18 P05 EXI2 SOUT0 TXD0 TMO3 EXI3 P37 44 ▉17 P04 EXI1 SCLK0 RXD0 TMO2 AIN11 TMO2 FTO0 SCLU0 P70 45 ▉16 P57 FTO1N AIN12 LCKO TMO3 FTO0N SDAU0 P71 46 ▉15 P56 FTO1 TMO4 FTO1 SCLM0 RXD2 EXI0 P72 47 ▉14 P55 FTO0N * TBCO TMOX FTO1N SDAM0 TXD2 EXI3 P73 48 ▉13 P54 FTO0 1 2 3 4 5 6 7 8 9 10 11 12 EXI1 PI0 XT0 EXCK PI1 XT1 VDD VSS VDDL RESET_N TEST1_N EXI0 TEST0 P00 RXD1 P02 LCKO TXD1 P03 RXD0 EXI4 P52 TXD0 EXI5 P53 DIE PAD = N.C. *: キャリア周波数出力対応 ML62Q253x WQFN48 (Top View) DIE PAD = NC *: Supported Carrier frequency output

Fig.3-3 40 pin WQFN P30 EXI4 SCLK0 RXD0 FTO0 VREF P27 EXI2 TBCO AIN7 P26 SIN0 AIN6 P25 SOUT0 SDAU0 AIN5 P24 SCLK0 SCLU0 AIN4 P23 SSNF0 SDAM0 FTO1N AIN3 P22 SDIF0 SCLM0 FTO1 AIN2 P21 SDOF0 TXD0 FTMO0N AIN1 * P20 SCKF0 RXD0 FTO0 AIN0 P17 TBCO 30 29 28 27 26 25 24 23 22 21 AIN8 FTO0N TXD0 SOUT0 EXI5 P31 31 ▉20 P13 SSNF0 FTO1N TMOX AIN13 AIN9 FTO1 RXD1 SIN0 EXI6 P32 32 ▉19 P12 EXI7 SDIF0 FTO1 TMO4 AIN10 FTO1N TXD1 EXI7 P33 33 ▉18 P11 EXI6 SDOF0 TXD2 FTO0N TMO3 LCKO * EXI0 P34 34 ▉17 P10 EXI5 SCKF0 RXD2 FTO0 TMO2 HCKO EXI1 P35 35 ▉16 P07 EXI4 TXD1 HCKO * EXI2 P36 36 ▉15 P06 EXI3 SIN0 RXD1 TMO4 AIN11 TMO2 FTO0 SCLU0 P70 37 ▉14 P05 EXI2 SOUT0 TXD0 TMO3 AIN12 LCKO TMO3 FTO0N SDAU0 P71 38 ▉13 P04 EXI1 SCLK0 RXD0 TMO2 TMO4 FTO1 SCLM0 RXD2 EXI0 P72 39 ▉12 P55 FTO0N * TBCO TMOX FTO1N SDAM0 TXD2 EXI3 P73 40 ▉11 P54 FTO0 1 2 3 4 5 6 7 8 9 10 EXI1 PI0 XT0 EXCK PI1 XT1 VDD VSS VDDL RESET_N TEST1_N EXI0 TEST0 P00 RXD1 P02 LCKO TXD1 P03 DIE PAD = N.C. *: キャリア周波数出力対応 ML62Q252x WQFN40 (Top View) DIE PAD = NC *: Supported Carrier frequency output

Fig.3-4 32 pin TQFP P27 EXI2 TBCO AIN7 P26 SIN0 AIN6 P25 SOUT0 SDAU0 AIN5 P24 SCLK0 SCLU0 AIN4 P23 SSNF0 SDAM0 FTO1N AIN3 P22 SDIF0 SCLM0 FTO1 AIN2 P21 SDOF0 TXD0 FTMO0N AIN1 * P20 SCKF0 RXD0 FTO0 AIN0 24 23 22 21 20 19 18 17 VREF FTO0 RXD0 SCLK0 EXI4 P30 ▉ 25 16 ▉P13 SSNF0 FTO1N TMOX AIN13 AIN8 FTO0N TXD0 SOUT0 EXI5 P31 ▉ 26 15 ▉P12 EXI7 SDIF0 FTO1 TMO4 AIN9 FTO1 RXD1 SIN0 EXI6 P32 ▉ 27 14 ▉P11 EXI6 SDOF0 TXD2 FTO0N TMO3 LCKO * AIN10 FTO1N TXD1 EXI7 P33 ▉ 28 13 ▉P10 EXI5 SCKF0 RXD2 FTO0 TMO2 HCKO AIN11 TMO2 FTO0 SCLU0 P70 ▉ 29 12 ▉P07 EXI4 TXD1 HCKO * AIN12 LCKO TMO3 FTO0N SDAU0 P71 ▉ 30 11 ▉P06 EXI3 SIN0 RXD1 TMO4 TMO4 FTO1 SCLM0 RXD2 EXI0 P72 ▉ 31 10 ▉P05 EXI2 SOUT0 TXD0 TMO3 * TBCO TMOX FTO1N SDAM0 TXD2 EXI3 P73 ▉ 32 9 ▉P04 EXI1 SCLK0 RXD0 TMO2 1 2 3 4 5 6 7 8 EXI1 PI0 XT0 EXCK PI1 XT1 VDD VSS VDDL RESET_N TEST1_N EXI0 TEST0 P00 *: キャリア周波数出力対応 ML62Q250x TQFP32 (Top View) *: Supported Carrier frequency output

Fig.3-5 32 pin WQFN P27 EXI2 TBCO AIN7 P26 SIN0 AIN6 P25 SOUT0 SDAU0 AIN5 P24 SCLK0 SCLU0 AIN4 P23 SSNF0 SDAM0 FTO1N AIN3 P22 SDIF0 SCLM0 FTO1 AIN2 P21 SDOF0 TXD0 FTMO0N AIN1 * P20 SCKF0 RXD0 FTO0 AIN0 24 23 22 21 20 19 18 17 VREF FTO0 RXD0 SCLK0 EXI4 P30 25 ▉16 P13 SSNF0 FTO1N TMOX AIN13 AIN8 FTO0N TXD0 SOUT0 EXI5 P31 26 ▉15 P12 EXI7 SDIF0 FTO1 TMO4 AIN9 FTO1 RXD1 SIN0 EXI6 P32 27 ▉14 P11 EXI6 SDOF0 TXD2 FTO0N TMO3 LCKO * AIN10 FTO1N TXD1 EXI7 P33 28 ▉13 P10 EXI5 SCKF0 RXD2 FTO0 TMO2 HCKO AIN11 TMO2 FTO0 SCLU0 P70 29 ▉12 P07 EXI4 TXD1 HCKO * AIN12 LCKO TMO3 FTO0N SDAU0 P71 30 ▉11 P06 EXI3 SIN0 RXD1 TMO4 TMO4 FTO1 SCLM0 RXD2 EXI0 P72 31 ▉10 P05 EXI2 SOUT0 TXD0 TMO3 * TBCO TMOX FTO1N SDAM0 TXD2 EXI3 P73 32 ▉9 P04 EXI1 SCLK0 RXD0 TMO2 1 2 3 4 5 6 7 8 EXI1 PI0 XT0 EXCK PI1 XT1 VDD VSS VDDL RESET_N TEST1_N EXI0 TEST0 P00 DIE PAD = N.C. *: キャリア周波数出力対応 ML62Q250x WQFN32 (Top View) DIE PAD = NC *: Supported Carrier frequency output

Pin No. Pin name Career frequency output ML62Q250x ML62Q252x ML62Q253x GPI/EXI ADC SSIO*/** UART I2C* FTM Timer CLKOUT/ LTBC 9 13 17 P04 ― EXI1 ― SCLK0-0 RXD0 ― ― TMO2 ― 10 14 18 P05 ― EXI2 ― SOUT0-0 TXD0 ― ― TMO3 ― 11 15 19 P06 ― EXI3 ― SIN0-0 RXD1 ― ― TMO4 ― 12 16 20 P07 ● EXI4 ― ― TXD1 ― ― ― HCKO 13 17 21 P10 ― EXI5 ― SCKF0-0 RXD2 ― FTO0 TMO2 HCKO 14 18 22 P11 ● EXI6 ― SDOF0-0 TXD2 ― FTO0N TMO3 LCKO 15 19 23 P12 ― EXI7 ― SDIF0-0 ― ― FTO1 TMO4 ― 16 20 24 P13 ― ― AIN13 SSNF0-0 ― ― FTO1N TMOX ― 17 22 26 P20 ― ― AIN0 SCKF0-1 RXD0 ― FTO0 ― ― 18 23 27 P21 ● ― AIN1 SDOF0-1 TXD0 ― FTO0N ― ― 19 24 28 P22 ― ― AIN2 SDIF0-1 ― SCLM0-0 FTO1 ― ― 20 25 29 P23 ― ― AIN3 SSNF0-1 ― SDAM0-0 FTO1N ― ― 21 26 30 P24 ― ― AIN4 SCLK0-1 ― SCLU0-0 ― ― ― 22 27 31 P25 ― ― AIN5 SOUT0-1 ― SDAU0-0 ― ― ― 23 28 32 P26 ― ― AIN6 SIN0-1 ― ― ― ― ― 24 29 33 P27 ― EXI2 AIN7 ― ― ― ― ― TBCO 25 30 37 P30 ― EXI4 VREF SCLK0-2 RXD0 ― FTO0 ― ― 26 31 38 P31 ― EXI5 AIN8 SOUT0-2 TXD0 ― FTO0N ― ― 27 32 39 P32 ― EXI6 AIN9 SIN0-2 RXD1 ― FTO1 ― ― 28 33 40 P33 ― EXI7 AIN10 ― TXD1 ― FTO1N ― ― 29 37 45 P70 ― ― AIN11 ― ― SCLU0-1 FTO0 TMO2 ― 30 38 46 P71 ― ― AIN12 ― ― SDAU0-1 FTO0N TMO3 LCKO 31 39 47 P72 ― EXI0 ― ― RXD2 SCLM0-1 FTO1 TMO4 ― 32 40 48 P73 ● EXI3 ― ― TXD2 SDAM0-1 FTO1N TMOX TBCO *: The SSIO and I2C use with a combination of the same suffix pins. **: Assign each function; SCLK0/SCKF0/FTOn/FTOnN/HCKO, to only one LSI pin each.

“I/O” Field in the below table define the pin type (“-“ : power supply pin, “I” : Input pin, “O” : Out put pin, “I/O” bi-directional pin) Table 4 Pin Description Function Functional pin name LSI pin name I/O Description Power － VSS － Negative power supply pin (-) Define the potential of this terminal as VSS － VDD － Positive power supply pin (+). Connect a capacitor CV (more than 1µF) between this pin and VSS. Define the potential of this terminal as VDD. － VDDL － Power supply for internal logic (internal regulator’s output). Connect a capacitor CL (1μF) between this pin and VSS. Debug ISP TEST0 P00/ TEST0 I/O Input/output for testing This pin which is shared with P00 is used as on-chip debug interface and ISP function and is initialized as pull-up input mode by the system reset. TEST1_N TEST1_N I Input for testing This pin is used as on-chip debug interface and ISP function and is initialized as pull-up input mode by the system reset. Reset RESET_N RESET_N I Reset input. Applying “L” level shifts the MCU in system reset mode. Applying “H” level shifts the CPU in program running mode. No pull-up resistor is installed. General input port (GPI) PI0, PI1 XT0, XT1 I General purpose input. - High-impedance (initial value) - Input without Pull-up P00 P00/ TEST0 I General purpose input. - Input with Pull-up (initial value) - Input without Pull-up Not available as general inputs when using the on-chip debug interface or ISP function. General port (GPIO) P02 ~ P07 P02 ~ P07 I/O General purpose input/output - High-impedance (initial value) - Input with Pull-up - Input without Pull-up - CMOS output - N channel (N-ch) open drain output P10 ~ P17 P10 ~ P17 P20 ~ P27 P20 ~ P27 P30 ~ P37 P30 ~ P37 P52 ~ P57 P52 ~ P57 P60 ~ P62 P60 ~ P62 P70 ~ P73 P70 ~ P73 Clock Input XT0 XT0 I Connect to the Low speed crystal resonator Connect 32.768kHz crystal resonator and connect capacitors between the pin and VSS. When inputting a square wave, Connect to XT1 pin XT1 XT1 I/O Clock Output (7th func.) HCKO P07 P10 O High-speed clock output. LCKO P03 P11 P71 Low-speed clock output. TBCO P17 P27 P73 Low-speed time base counter output. Career frequency output ― P07 P11 P21 P73 O Career frequency output External Interrupt (1st func.) EXI0 P00 P72 P34 I External Maskable Interrupt 0 Input EXI1 P04 XT0 P35 External Maskable Interrupt 1 Input EXI2 P05 P27 P36 External Maskable Interrupt 2 Input EXI3 P06 P73 P37 External Maskable Interrupt 3 Input EXI4 P07 P30 P52 External Maskable Interrupt 4 Input EXI5 P10 P31 P53 External Maskable Interrupt 5 Input EXI6 P11 P32 P60 External Maskable Interrupt 6 Input EXI7 P12 P33 P61 External Maskable Interrupt 7 Input 16bit General Timer (6th func.) TMO2 P04 P10 P60 P70 O 16bit General Timer 2 output TMO3 P05 P11 P61 P71 16bit General Timer 3 output TMO4 P06 P12 P62 P72 16bit General Timer 4 output TMOX P13 P73 16bit General Timer X output

name LSI pin name I/O Description Functional Timer (5th func.) FTO0 P10 P20 P30 P54 P70 O Functional Timer0 P output FTO0N P11 P21 P31 P55 P71 Functional Timer0 N output FTO1 P12 P22 P32 P56 P72 Functional Timer1 P output FTO1N P13 P23 P33 P57 P73 Functional Timer1 N output I2C Bus (4th func.) SCLU0 P24 P70 I/O I2C Unit0 Clock input/output SDAU0 P25 P71 I2C Unit0 Data input/output SCLM0 P22 P72 I2C Master0 Clock input/output SDAM0 P23 P73 I2C Master0 Data input/output UART (3rd func.) RXD0 P04 P20 P30 P52 I UART0 received data input TXD0 P05 P21 P31 P53 O UART0 transmission data output RXD1 P02 P06 P32 I UART1 received data input TXD1 P03 P07 P33 O UART1 transmission data output RXD2 P10 P72 I UART2 received data input TXD2 P11 P73 O UART2 transmission data output Synchronous Serial Port (2nd func.) SCKF0 P10 P20 I/O Synchronous serial0 (with FIFO) clock input/output SDIF0 P12 P22 I Synchronous serial0 (with FIFO) data input SDOF0 P11 P21 O Synchronous serial0 (with FIFO) data output SSNF0 P13 P23 I/O Synchronous serial0 (with FIFO) slave select input/output SCLK1 P04 P24 P30 I/O Synchronous serial0 clock input/output SIN1 P06 P26 P32 I Synchronous serial0 data input SOUT1 P05 P25 P31 O Synchronous serial0 data output Successive approximation type A/D converter (SA-ADC) (1st func.) VREF P30 I SA-ADC external reference voltage input Define the potential of reference voltage for SA-ADC as VREF AIN0~AIN13 P13 P27-P20 P33-P31 P71-P70 I SA-ADC channel 0 to 13 analog input

TERMINATION OF UNUSED PINS Table 5 shows the processing of unused pins. Table 5 Termination of unused pins Pin pin termination NC Open RESET_N Connect to VDD TEST1_N Connect to VDD P00/TEST0 Open the pin with the initial condition of pulled-up input mode XT0, XT1 Open the pins with the initial condition of Hi-impedance mode. P02 ~ P07 P10 ~ P17 P20 ~ P27 P30 ~ P37 P52 ~ P57 P60 ~ P62 P70 ~ P73 [Note]  Terminate unused input pins according to the table 5 in order to avoid unexpected through -current in the pins.

ELECTRICAL CHARACTERISTICS

(VSS = 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 VDD Ta = +25°C -0.3 to +6.5 V Power supply voltage 2 VDDL Ta = +25°C -0.3 to +2.0 V Input voltage VIN Ta = +25°C -0.3 to VDD+0.3*1 V Output voltage1 VOUT1 Ta = +25°C -0.3 to VDD+0.3*1 V “H” level output current IOUTH Ta = +25°C 1pin -40*2 mA Total -180*2 “L” level output current IOUTL Ta = +25°C 1pin +40 mA Total +180 Power dissipation PD Ta = +25°C 1 W Storage temperature TSTG ― -55 to +150*3 °C *1: 6.5V or lower *2: The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin. *3: Please observe a storage conditions shown in the document “Board Mounting (soldering)” about the storage conditions until implementation. [Note]  Stresses above the absolute maximum ratings listed in the above table may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Recommended Operating Conditions (VSS = 0V) Parameter Symbol Condition Range Unit Operating temperature (Ambient) Ta ― -40 to +105 °C Operating temperature (Chip-Junction) Tj ― -40 to +115 °C Operating voltage 1 VDD ― 1.8 to 5.5 V Operating frequency (CPU) fOP VDD = 1.8 to 5.5V 30k to 25M Hz VDDL pin external capacitance CL ― 1.0 ±30% μF

The maximum chip-junction temperature, Tjmax, may be calculated using the following equation. 𝑇𝑇𝑗𝑗 𝑚𝑚𝑚𝑚𝑚𝑚 = 𝑇𝑇𝑚𝑚 𝑚𝑚𝑚𝑚𝑚𝑚 + 𝑃𝑃𝐷𝐷 𝑚𝑚𝑚𝑚𝑚𝑚 × 𝜃𝜃𝑗𝑗𝑚𝑚 𝑇𝑇𝑚𝑚 𝑚𝑚𝑚𝑚𝑚𝑚 : maximum ambient temperature 𝑃𝑃𝐷𝐷 𝑚𝑚𝑚𝑚𝑚𝑚 ∶ LSI maximum power dissipation 𝜃𝜃𝑗𝑗𝑚𝑚 : Package junction to ambient thermal resistance Design a Mounting board by considering heat radiation such as power dissipation and ambient temperature to satisfy the recommended conditions. The following table shows the each package’s thermal resistance for thermal design reference estimated by simulation based on the PCB (printed circuit board) conditions define as a below. Parameter Symbol Package type Value Unit L1 L2 Thermal resistance θja WQFN32 50.6 43.5 °C/W TQFP32 67.6 61.8 WQFN40 32.8 28.9 WQFN48 31.1 27.4 TQFP48 60.2 56.9 PCB conditions: PCB name L1 L2 Unit Number of layer 1 2 layer Wiring density 60% (top layer) 60% (top and bottom layer) ― Wind condition No wind (0m/s) ―

(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Condition Min. Typ.*2 Max. Unit Measuring circuit Operating mode circuit state *1 Tj≤ +95oC Tj≤ +115oC IDD0 STOP-D All clocks are stopped. ― 0.33 25 55 μA IDD1 STOP All clocks are stopped. ― 0.4 30 70 μA IDD2-0R HALT-D RC32K is oscillating. XT32K/PLL are stopped. ― 0.6 28 60 μA IDD2-0X HALT-D XT32K is oscillating with LP mode, without noise-filter. RC32K/PLL are stopped. ― 1.0 30 65 μA IDD2-1R HALT RC32K is oscillating. XT32K/PLL are stopped. ― 0.9 30 70 μA IDD3 CPU running in wait-mode SYSCLK=32.768kHz RC32K is oscillating. XT32K/PLL are stopped. ― 10 45 75 μA IDD4-H1 CPU running in wait-mode SYSCLK=1MHz PLL is oscillating as PLL1M mode. HSCLK = 1MHz ― 0.22 0.33 0.35 mA IDD4-H16 PLL is oscillating as PLL16M mode. HSCLK = 1MHz ― 0.32 0.48 0.5 mA IDD5-H16 CPU running in wait-mode SYSCLK=16MHz PLL is oscillating as PLL16M mode. HSCLK = 16MHz ― 2.4 3.24 3.3 mA IDD5-H24 CPU running in wait-mode SYSCLK=24MHz PLL is oscillating as PLL24M mode. HSCLK = 24MHz ― 3.5 4.4 4.5 mA *1: LTBC0 and WDT is operating except IDD0/1, and all clocks peripheral circuits are stopped by block control. LSCLK1 is stopped. The code option VLMD is "1". *2: On the condition of VDD=3.0V, Ta=+25°C

Low speed Crystal Oscillation (VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Crystal oscillation frequency *1 *2 fXTL ― ― 32.768 ― kHz Crystal oscillation start time TXTL ― ― ― 2 s *1: The oscillation frequency is determined by the oscillation circuit, crystal resonator and the external capacitance (CGL/CDL). As those parameters changes depending the crystal resonator, it requires evaluation on the actual PCB circuit for matching. Ask crystal resonator makers for matching and confirm the oscillation characteristics. *2: The quality of oscillation characteristics might be lost, depending on material of PCB, condition of wiring capacitance or parasitic capacitance on the external circuits. Note for designing the external circuit. - Make the wires on the external circuit as short as possible. - Place the crystal resonator and oscillation circuit as close to the MCU as possible and make the wires between the external capacitance and crystal resonator as short as possible. - Ensure no signal line flowing big current runs near the oscillation circuit. - Ensure no signal line runs under and near the oscillation circuit. - Make ground of external capacitance the same as MCU ground VSS pin and connect them to the ground that has low variation of current and voltage. - The quality of oscillation characteristics might be lost depending on operating environment due to moisture absorption of PCB and condensation of PCB surface, recommended to have measures such as covering the oscillation circuit with resin. Low speed Crystal Oscillation external circuit example External Clock Input (VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Input Frequency fEXCK ― Typ. -1.0% 32.768 Typ. +1.0% kHz Input pulse width tEXCKW ― 14.5 ― ― μs XT0 XT1 VSS CDL CGL Crystal resonator (32.768kHz)

(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Measuring circuit RC32K frequency fRCL1 Ta= -40 to +85°C except HALT-D mode Typ. -1.5% 32.768 Typ. +1.5% kHz Ta= -40 to +105°C except HALT-D mode Typ. -2.0% Typ. +2.0% fRCL2 HALT-D mode Typ. -10% Typ. +10% PLL oscillation frequency fPLL1 Ta= -40 to +85°C with RC32K Typ. -1.5% 24.002560 16.007168 0.999424 Typ. +1.5% MHz Ta= -40 to +105°C with RC32K Typ. -2.0% Typ. +2.0% PLL oscillation start time TPLL ― ― ― 2 ms wake-up from HALT-H VLMD=0 no temperature variation between before/after HALT-H ― ― 300 μs RC1K frequency (for WDT) fRC1K Ta= -20 to +85°C Typ. -15% 1.024 Typ. +15% kHz Ta= -40 to +105°C Typ. -25% Typ. +25% *: The frequency is the factory default specification. It may vary depending on the board mounting.

(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Measur ing circuit Output voltage1 “H”/“L” level (all input/output port) VOH1 IOH1=-10mA VDD≥4.5V VDD -1.5 ― ― V 2 IOH1=-1mA VDD≥1.8V VDD -0.5 ― ― VOL1 IOL1=+10mA VDD≥4.5V ― ― 1.5 IOL1=+1mA VDD≥1.8V ― ― 0.5 Output voltage2 “L” level (all input/output port except P00/TEST0) VOL2 When N-ch open drain output mode is selected IOL2=+15mA VDD≥4.5V ― ― 0.7 IOL2=+8mA VDD≥3.0V ― ― 0.5 IOL2=+3mA VDD≥2.0V ― ― 0.4 IOL2=+2mA VDD≥1.8V ― ― 0.4 (VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Measuri ng circuit Input current1 (RESET_N) IIH1 VIH1=VDD ― ― 1 μA IIL1 VIL1=VSS -1*1 ― ― Input current2 (P00/TEST0) IIL2 VIL2=VSS (pull-up mode) *2 -1500*1 -300*1 -20*1 V/IIL2 VIL2=VSS (pull-up mode) *2 3.7 10 80 kΩ IIH2Z VIH2=VDD (High impedance mode) ― ― 1 μA IIL2Z VIL2=VSS (High impedance mode) -1*1 ― ― Input current3 (all input port except RESET_N, TEST1N, P00/TEST0, input/output port) IIL3 VIL1=VSS (pull-up mode) *2 -250*1 -30*1 -2*1 V/IIL3 VIL1= VSS (pull-up mode) *2 22 100 800 kΩ IIH3Z VIH1=VDD (High impedance mode) ― ― 1 μA IIL3Z VIL1=VSS (High impedance mode) -1*1 ― ― Input current4 (PI0, PI1) IIH4 VIH1=VDD ― ― 1 IIL4 VIL1=VSS -1*1 ― ― Input voltage1 (all input port, input/output port) VIH1 ― 0.7 ×VDD ― VDD V 5 VIL1 ― 0 ― 0.3 ×VDD Pin capacitance (all input port, input/output port) CPIN f = 10kHz Ta = 25oC ― ― 10 pF ― *1: The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin. *2: Measurement conditions: Typ: VDD = 3.0V, Max: VDD = 1.8V, Min: VDD = 5.5V

(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symb ol Condition Min. Typ. Max. Unit Measu ring circuit “H” level output current1 *6 IOH1 1pin mA “H” level output total current1 *1*4 IOH3 Total of group A or B ** (duty ≤ 50%) VDD≥4.5V -90*5 ― ― VDD≥1.8V -20*5 ― ― All pin total (duty ≤ 50%) VDD≥1.8V -40*5 ― ― “L” level output current1 *6 IOL1 1pin (CMOS output mode) VDD≥4.5V ― ― 10*3 VDD≥1.8V ― ― 1*3 “L” level output current2 *6 IOL2 1pin (N-ch open drain output mode) VDD≥4.5V ― ― 15*3 VDD≥3.0V ― ― 8*3 VDD≥2.0V ― ― 3*3 VDD≥1.8V ― ― 2*3 “L” level output total current *2*4 IOL3 Total of group A or B ** (N-ch open drain output mode, duty≤50%) VDD≥4.5V ― ― 90 VDD≥3.0V ― ― 40 VDD≥2.0V ― ― 15 VDD≥1.8V ― ― 10 All pin total (N-ch open drain output mode, duty≤50%) VDD≥4.5V ― ― 180 VDD≥1.8V ― ― 20 Output leak (all input/output port) IOOH VOH=VDD (High impedance mode) ― ― +1 μA IOOL VOL=VSS (High impedance mode) -1*5 ― ― ** : Group A is “P02 to P07, P10 to P17 and P52 to P57”, group B is “P20 to P27, P30 to P37, P60 to P62 and P70 to P73”. *1: Sink-out current from VDD to the output pin, which can guarantee the device operation. *2: Sink-in current from the output pin to VSS, which can guarantee the device operation. *3: Do not exceed total current. *4: The total current is on the condition of Duty≤50% (same applies to IOH1). When the duty ＞50% the total current is calculated by following formula. Total current = IOL3 x 50/n (When the duty is n%) <For an example> When IOL3=100mA and n=80%, Total current = IOL3 x 50/80 = 62.5mA Current allowed per 1pin is independent of the duty and specified as IOL1 and IOL2. Do not apply current larger than Absolute Maximum Ratings. *5: The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin. *6: These values are satisfied with VOH1, VOL1 and VOL2.

(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition / Rating Unit Standard Mode Fast Mode 1Mbps Mode SCL clock frequency fSCL 0 ― 100 0 ― 400 0 ― 1000 kHz SCL hold time (start/restart condition) tHD:STA 4.0 ― ― 0.6 ― ― 0.26 ― ― μs SCL “L” level time tLOW 4.7 ― ― 1.3 ― ― 0.5 ― ― μs SCL “H” level time tHIGH 4.0 ― ― 0.6 ― ― 0.26 ― ― μs SCL setup time (restart condition) tSU:STA 4.7 ― ― 0.6 ― ― 0.26 ― ― μs SDA hold time tHD:DAT 0 ― ― 0 ― ― 0 ― ― μs SDA setup time tSU:DAT 0.25 ― ― 0.1 ― ― 0.1 ― ― μs SDA setup time (stop condition) tSU:STO 4.0 ― ― 0.6 ― ― 0.26 ― ― μs Bus-free time tBUF 4.7 ― ― 1.3 ― ― 0.5 ― ― μs When using the I2C as the master, configure the I2C master 0 mode register(I2M0MOD) and I2C bus 0 mode register (master side, I2U0MOD) so that meet these specifications. SCLU0 SCLM0 SDAU0 SDAM0 Start Condition Re-start Condition Stop Condition tBUF tHD:STA tLOW tHIGH tSU:STA tSU:DAT tHD:DAT tSU:STO 0.7×VDD 0.3×VDD 0.7×VDD 0.3×VDD tHD:STA

(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit SCLK input cycle tSCYC ― 1*1 ― ― μs SCLK input pulse width tSW ― tSCYC x 0.4 ― ― μs SOUT output delay time tSD VDD≥2.4V ― ― 100 ns VDD≥1.8V ― ― 200 ns SIN input setup time tSS ― 80 ― ― ns SIN input hold time tSH ― 50 ― ― ns *1: Need input cycles of SYSCLK x 4 or longer Master mode (VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit SCLK output cycle tSCYC VDD≥2.4V 250 SCLK*2 ― ns VDD≥1.8V 500 SCLK*2 ― ns SCLK output pulse width tSW ― tSCYC×0.4 tSCYC×0.5 tSCYC×0.6 ns SOUT output delay time tSD VDD≥2.4V ― ― 100 ns VDD≥1.8V ― ― 160 ns SIN input setup time tSS VDD≥2.4V 120 ― ― ns VDD≥1.8V 180 ― ― ns SIN input hold time tSH VDD≥2.4V 80 ― ― ns VDD≥1.8V 100 ― ― ns *2: Clock cycle selected by bit12 to 8(S0CK4 to 0) of the serial port 0 mode register (SIO0MOD) tSD SCLK SIN SOUT tSD tSS tSH tSW tSW tSCYC 0.3×VDD 0.7×VDD 0.3×VDD 0.7×VDD 0.3×VDD 0.7×VDD

Synchronous Serial Port with FIFO Slave mode (VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit SCKF input cycle tSCYC ― 1*1 ― ― μs SCKF input pulse width tSW ― tSCYC x 0.4 ― ― μs SDOF output delay time tSD VDD≥2.4V ― ― 100 ns VDD≥1.8V ― ― 200 ns SDIF input setup time tSS ― 80 ― ― ns SDIF input hold time tSH ― 50 ― ― ns *1: Need input cycles of SYSCLK x 4 or longer Master mode (VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit SCKF output cycle tSCYC VDD≥2.4V 250 SCLK*2 ― ns VDD≥1.8V 500 SCLK*2 ― ns SCKF output pulse width tSW ― tSCYC×0.4 tSCYC×0.5 tSCYC×0.6 ns SDOF output delay time tSD VDD≥2.4V ― ― 100 ns VDD≥1.8V ― ― 160 ns SDIF input setup time tSS VDD≥2.4V 120 ― ― ns VDD≥1.8V 180 ― ― ns SDIF input hold time tSH VDD≥2.4V 80 ― ― ns VDD≥1.8V 100 ― ― ns *2: Clock cycle selected by bit9 to 0(SF0BR9 to 0) of the SIOF0 baud rate register (SF0BRR) tSD SCKF SDIF SDOF tSD tSS tSH tSW tSW tSCYC 0.3×VDD 0.7×VDD 0.3×VDD 0.7×VDD 0.3×VDD 0.7×VDD

(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit TEST1_N clock input cycle tTCYC ― 400 ― 660 ns TEST1_N input pulse width tTW ― tTCYC x 0.4 ― ― ns TEST0 output delay time tTD VDD≥2.7V ― ― 80 ns VDD≥1.8V ― ― 200 ns TEST0 input setup time tTS ― 80 ― ― ns TEST0 input hold time tTH ― 50 ― ― ns EXl0~7 Timer Clock Input (VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Input Frequency fEXI ― ― ― 3 MHz Input pulse width tWEXI ― 135 ― ― ns tTD TEST1_N TEST0 (input) TEST0 (output) tTD tTS tTH tTW tTW tTCYC 0.3×VDD 0.7×VDD 0.3×VDD 0.7×VDD 0.3×VDD 0.7×VDD

(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Measuring circuit Reset pulse width*1 PRST ― 10 ― ― μs 1 [Note]  RESET_N input shorter pulse than the Reset pulse width (PRST) valid time should be avoided. The shorter pulse input may cause unexpected behavior. Slope of Power supply and Power On Reset (VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Measuring circuit Power on rising slope SVR ― ― ― 60 V/ms Power on falling slope SVF ― ― ― 2 V/ms Power on reset detection voltage VPORR At Power up (rising) 1.50 1.63 1.80 V VPORF At Power down (falling) 1.35 1.60 1.75 V Power on reset minimum pulse width PPOR ― 500 ― ― μs CPU operation start time (from the release of reset to the CPU starts to run) tCPUI ― 13 21 35 ms ― [Note]  If a pulse shorter than the Power on reset minimum pulse width is asserted to V DD, it may cause the MCU malfunction. Apply prevent measurement such as bypass capacitors or external reset input, and so on.  Set VDD to 1.8V or higher before starting CPU operation. PRST VIL1 VIL1 VIH1 RESET_N VDD VPORR PPOR VPORF 1.8V tCPUI SVR SVF SVF SVR At Power supply voltage level change At Power off At power on SVR At Power supply restart

(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Falling Rising Unit Measuring circuit VVLSF VVLSR VLS threshold voltage VVLSR VVLSF V 1 *1: Bit3~Bit0 of voltage level detection circuit 0 level register (VLS0LV). (VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Measuring circuit VLS current consumption IVLS ― ― 10 ― nA 1

Successive Approximation Type A/D Converter (VDD=2.1 to 5.5V, VSS =0V, Ta=-40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Resolution nAD ― －－ 12 bit Conversion clock fADCLK nominal value, VDD ≥ 2.7V, VREF ≥ 2.7V 32.768 － 16000 kHz nominal value, VDD ≥ 2.4V, VREF ≥ 2.4V 32.768 － 8000 kHz nominal value, VDD ≥ 2.1V, VREF ≥ 2.1V 32.768 － 1000 kHz Conversion time tCONV fADCLK = 16MHz 1.375 －－ μs fADCLK = 32.768kHz － 518.799 － μs A/D reference voltage VREF VDD ≥ VREF 2.1 － VDD V Overall error － 4.5V ≤ VREF ≤ 5.5V -6 － +6 LSB Integral non-linearity error INLAD fADCLK = 16MHz 2.7V ≤ VREF -4 － +4 LSB fADCLK = 8MHz 2.4V ≤ VREF -7 － +7 fADCLK = 1MHz 2.1V ≤ VREF -8 － +8 Differential non-linearity error DNLAD fADCLK = 16MHz 2.7V ≤ VREF -3 － +3 fADCLK = 8MHz 2.4V ≤ VREF -5 － +5 fADCLK = 1MHz 2.1V ≤ VREF -7 － +7 Zero-scale error ZSE fADCLK = 16MHz -8 － +8 fADCLK = 8MHz -8 － +8 fADCLK = 1MHz -10 － +10 Full-scale error FSE fADCLK = 16MHz -8 － +8 fADCLK = 8MHz -8 － +8 fADCLK = 1MHz -10 － +10 The current flows during the ADC sampling as it takes charging. Make the output impedance of the analog signal source 1kΩ or smaller. Also, putting 0.1µF capacitor on the ADC input pin is recommended to reduce the noise. A VDD VDDL VSS 1.0μF RI ≤ 1kΩ AINx 0.1μF 1.0μF Analog input

(VSS= 0V) Parameter Symbol Condition Range Unit Operating temperature TOP Data flash memory, At write/erase -40 to +85 Flash ROM, At write/erase 0 to +40 Operating voltage VDD At write/erase +1.8 to +5.5 V Maximum rewrite count CEPD Data Flash 10000 times CEPP Program Flash 100 Erasing unit ― Block erasing Program Flash 16K Byte Data Flash all area ― Sector erasing Program Flash 1K Byte Data Flash 128 Erasing time (Max.) ― Block erasing / Sector erasing 50 ms Writing unit ― Program Flash 4 Byte Data Flash 1 Writing time (Max.) ― Program Flash 80 μs ― Data Flash 40 Data retention period YDR rewriting count 100 times 15 years

Measuring circuit 2 Measuring circuit 3 Measuring circuit 4 Measuring circuit 5 VDD VSS CV CL VDDL CV : 1.0μF CL : 1.0μF CDL : 12pF CGL : 12pF XT0 XT1 CGL CDL A Crystal resonator (32.768kHz) Input pins V VDD VSS VIH VIL Output pins (*2) (*1) Current load VDDL Input pins A VDD VSS VIH VIL Output pins (*2) (*1) VDDL Input pins A VDD VSS Output pins (*2) VDDL Input pins VDD VSS VIH VIL Output pins (*1) VDDL (*1) Input logic circuit to determine the specified measuring conditions (*2) Measured connecting specified pins Output pins

(Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

REVISION HISTORY

No. Date Page Description Previous Edition Current Edition FEDL62Q2500-01 Oct. 20, 2022 - - 1st Edition FEDL62Q2500-02 Nov.9, 2022 - - Corrected typo, corrected appearance FEDL62Q2500-03 Feb.2, 2023 19 19 Corrected typo, HSCLK condition of IDD4-H16 19 19 New addition of Tj≤+95oC specification of IDD3, IDD4-H1, IDD4-H16, IDD5-H16 and IDD5-H24

Notes on this page are applicable to the all LAPIS Technology microcontroller products. For individual notes on each LAPIS Technology microcontroller product, refer to [Note] in the chapters of each user's manual. The individual notes of each user’s manual take priority over those contents in this page if they are different. 1. HANDLING OF UNUSED INPUT PINS Fix the unused input pins to the power pin or GND to prevent to cause the device performing wrong operation or increasing the current consumption due to noise, etc. If the handlings for the unused pins are described in the chapters, follow the instruction. 2. STATE AT POWER ON At the power on, the data in the internal registers and output of the ports are undefined until the power supply voltage reaches to the recommended operating condition and "L" level is input to the reset pin. On LAPIS Technology microcontroller products that have the power on reset function, the data in the internal registers and output of the ports are undefined until the power on reset is generated. Be careful to design the application system does not work incorrectly due to the undefined data of internal registers and output of the ports. 3. ACCESS TO UNUSED MEMORY If reading from unused address area or writing to unused address area of the memory, the operations are not guaranteed. 4. CHARACTERISTICS DIFFERENCE BETWEEN THE PRODUCT Electrical characteristics, noise tolerance, noise radiation amount, and the other characteristics are different from each microcontroller product. When replacing from other product to LAPIS Technology microcontroller products, please evaluate enough the apparatus/system which implemented LAPIS Technology microcontroller products. 5. USE ENVIRONMENT When using LAPIS Technology microcontroller products in a high humidity environment and an environment where dew condensation, take moisture-proof measures.

1) The information contained herein is subject to change without notice. 2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are within the ranges specified. LAPIS Technology disclaims any and all liability for any malfunctions, failure or accident arising out of or in connection with the use of LAPIS Technology Products outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within such usage conditions specified ranges, semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent personal injury, fire or the other damage from break down or malfunction of LAPIS Technology Products, please take safety at your own risk measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you. 3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. And the peripheral conditions must be taken into account when designing circuits for mass production. LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, and other related information. 4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Technology or any third party with respect to LAPIS Technology Products or the information contained in this document (including but not limited to, the Product data, drawings, charts, programs, algorithms, and application examples 、etc.). Therefore LAPIS Technology shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems, gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in applications requiring a high degree of reliability (as exemplified below), please be sure to contact a LAPIS Technology representative and must obtain written agreement: transportation equipment (cars, ships, trains, etc.), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising by using the Product for purposes not intended by us. Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters, etc. 6) The Products specified in this document are not designed to be radiation tolerant. 7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However, LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 9) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.. 10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or LAPIS Technology's Products. 11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology. (Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd. Copyright 2023 LAPIS Technology Co., Ltd. 2-4-8 Shinyokohama, Kouhoku-ku,Yokohama 222-8575, Japan https://www.lapis-tech.com/en/

Product Information

FEDL62Q2500 specifications and overview.

Summary

16-bit micro controller

Description

16-bit micro controller

Source title FEDL62Q2500 Datasheet(PDF) - Rohm

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