MD56V62160E
Document overview
- Manufacturer or author: Lapis Semiconductor Co., Ltd.
- PDF pages: 33
Technical content
Issue Date: Nov. 18, 2013 MD56V62160E 4-Bank 1,048,576-Word 16-Bit SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
The MD56V62160E is a 4-Bank 1,048,576-word 16-bit Synchronous dynamic RAM fabricated in LAPIS Semiconductor’s silicon-gate CMOS technology. The device operates at 3.3 V . The inputs and outputs are LVTTL compatible.
FEATURES
- Silicon gate, quadruple poly-silicon CMOS, 1-transistor memory cell
- 4-Bank 1,048,576-word 16-bit configuration
- Single 3.3 V power supply, 0.3 V tolerances
- Input : LVTTL compatible
- Output : LVTTL compatible
- Refresh : 4096 cycles/64 ms
- Programmable data transfer mode - CAS Latency (2, 3) - Burst Length (1, 2, 4, 8, Full Page) - Data scramble (sequential, interleave)
- CBR auto-refresh, Self-refresh capability
- Packages: 54-pin 400 mil plastic TSOP (TypeII) (P-TSOP(2)54-400-0.80-UK6) (Product: MD56V62160E-xxTA) xx indicates speed rank. PRODUCT FAMILY Access Time (Max.) Family Max. Frequency tAC2 t AC3 MD56V62160E-10 100 MHz 6 ns 6 ns
PIN CONFIGURATION (TOP VIEW) Pin Name Function Pin Name Function CLK System Clock UDQM, LDQM Data Input/ Output Mask CS Chip Select DQi Data Input/ Output CKE Clock Enable V CC Power Supply (3.3 V) A0–A11 Address V SS Ground (0 V) A12, A13 Bank Select Address VCCQ Data Output Power Supply (3.3 V) RAS Row Address Strobe V SSQ Data Output Ground (0 V) CAS Column Address Strobe NC No Connection WE Write Enable Note : The same power supply voltage must be provided to every V CC pin and VCCQ pin. The same GND voltage level must be provided to every V SS pin and VSSQ pin. 54-Pin Plastic TSOP(II) (K Type) DQ1 V CCQ DQ3 VCC VSS DQ16 V SSQ DQ14 VSSQVCCQ DQ7 VSSQ DQ8 DQ10 VCCQ NC DQ5 CA S VCC VSSQ A12 A10 C S RA S LDQM A13 WE V CCQ DQ12 V SS NC A11 UDQM CLK CKE
30 A5 A2
28 VSS VCC
CLK Fetches all inputs at the “H” edge. CS Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, UDQM and LDQM. CKE Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address : RA0 – RA11 Column Address : CA0 – CA7 A13, A12 (BA0, BA1) Slects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. RAS CAS WE Functionality depends on the combination. For details, see the function truth table. UDQM, LDQM Masks the read data of two clocks later when UDQM and LDQM are set “H” at the “H” edge of the clock signal. Masks the write data of the same clock when UDQM and LDQM are set “H” at the “H” edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte. DQi Data inputs/outputs are mu ltiplexed on the same pin.
ELECTRICAL CHARACTERISTICS
Parameter Symbol Value Unit Voltage on Any Pin Relative to VSS V IN, VOUT –0.5 to V CC+ 0.5 V VCC Supply Voltage VCC , VCCQ –0.5 to 4.6 V Storage Temperature Tstg –55 to 150 °C Power Dissipation PD* 1000 mW Short Circuit Output Current IOS 50 mA Operating Temperature Topr 0 to 70 °C *: Ta = 25C Recommended Operating Conditions (Voltages referenced to VSS = 0 V) Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage VCC, VCCQ 3.0 3.3 3.6 V Input High Voltage VIH 2.0 V CC + 0.3 V Input Low Voltage VIL 0.3 0.8 V Pin Capacitance (Vbias = 1.4 V, Ta = 25°C, f = 1 MHz) Parameter Symbol Min. Max. Unit Input Capacitance (CLK) CCLK 2.5 4 pF Input Capacitance (RAS, CAS, WE, CS, CKE, UDQM, LDQM, A0 – A13) CIN 2.5 5 pF Input/Output Capacitance (DQ1 – DQ16) COUT 4 6.5 pF
Bank CKE Others Min. Max. Unit Note Output High Voltage VOH IOH = 2.0mA 2.4 V Output Low Voltage V OL IOL = 2.0mA 0.4 V Input Leakage Current I Output Leakage Current I ICC1 One Bank Active CKE V IH tCC = Min. tRC = Min. No Burst 70 mA 1,2 Average Power Supply Current (Operating) I CC1D Both Banks Active CKE VIH tCC = Min. tRC = Min. tRRD = Min. No Burst 115 mA 1,2 Power Supply Current (Standby) ICC2 Both Banks Precharge CKE VIH tCC = Min. 30 mA 3 Average Power Supply Current (Clock Suspension) ICC3S Both Banks Active CKE VIL tCC = Min. 3 mA 2 Average Power Supply Current (Active Standby) ICC3 One Bank Active CKE VIH tCC = Min. 30 mA 3 Power Supply Current (Burst) I CC4 Both Banks Active CKE VIH tCC = Min. 90 mA 1,2 Power Supply Current (Auto-Refresh) ICC5 One Bank Active CKE VIH tCC = Min. tRC = Min. 115 mA 2 Average Power Supply Current (Self-Refresh) I CC6 Both Banks Precharge CKE VIL tCC = Min. 2 mA Average Power Supply Current (Power Down) ICC7 Both Banks Precharge CKE VIL tCC = Min. 2 mA Notes: 1. Measured with outputs open. 2. The address and data can be changed once or left unchanged during one cycle. 3. The address and data can be changed once or left unchanged during two cycles. DC
Single Write CAS Latency Burst Type Burst Length A9 BRSW A6 A5 A4 CL A3 BT A2 A1 A0 BT = 0 BT = 1
0 Normal 0 0 0 Reserved 0 Sequential 000 1 1
1 Single Write 0 0 1 Reserved 1 Interleave 0 0 1 2 2
1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Full Page Reserved Notes: A7, A8, A10, A11, A12 and A13 should stay “L” during mode set cycle. MD56V62160E supports two methods of Power on Sequence. POWER ON SEQUENCE 1 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the V CC voltage has reached the specified level, pause for 200 s or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. POWER ON SEQUENCE 2 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the V CC voltage has reached the specified level, pause for 200 s or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Enter the mode register setting command. 5. Apply a CBR auto-refresh eight or more times.
AC Characteristics (1/2) Note1, 2 MD56V62160 E-10 Parameter Symbol Min. Max. Unit Note CL = 3 tCC3 10 ns Clock Cycle Time CL = 2 tCC2 10 ns CL = 3 tAC3 6 ns 3, 4 Access Time from Clock CL = 2 tAC2 6 ns 3, 4 Clock High Pulse Time tCH 3 ns 4 Clock Low Pulse Time tCL 3 ns 4 Input Setup Time tSI 3 ns Input Hold Time tHI 1 ns Output Low Impedance Time from Clock tOLZ 1 ns Output High Impedance Time from Clock tOHZ 6 ns Output Hold from Clock tOH 3 ns 3 Random Read or Write Cycle Time t RC 70 ns RAS Precharge Time t RP 20 ns RAS Pulse Width t RAS 50 100,000 ns RAS to CAS Delay Time tRCD 20 ns Write Recovery Time tWR 10 ns RAS to CAS Bank Active Delay Time tRRD 20 ns Refresh Time tREF 64 ms Power-down Exit setup Time t PDE t SI +1CLK ns CAS to CAS Delay Time (Min.) l CCD 1 Cycle Clock Disable Time from CKE l CKE 1 Cycle Data Output High Impedance Time from UDQM, LDQM lDOZ 2 Cycle Dada Input Mask Time from UDQM, LDQM l DOD 0 Cycle
AC Characteristics (2/2) Note1, 2 Parameter Symbol MD56V62160 E-10 Unit Note Data Input Mask Time from Write Command lDWD 0 Cycle Data Output High Impedance Time from Precharge Command l ROH CL Cycle Active Command Input Time from Mode Register Set Command Input (Min.) lMRD 2 Cycle Write Command Input Time from Output l OWD 2 Cycle Notes: 1. AC measurements assume that t T = 1 ns. 2. The reference level for timing of input signals is 1.4 V. The input signal conditions are below. V IH = 2.4 V, VIL = 0.4 V 3. Output load. 4. The access time is defined at 1.4 V. 5. If t T is longer than 1 ns, then the reference level for timing of input signals is VIH and VIL. Output Z = 50 50 pF (External Load)
Read & Write Cycle (Same Bank) @CAS La tency 2, Burst Length 4 CLK CKE CS RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM tOH Ra Ca0 tRP tRC Qa1 Cb0Rb RbRa Qa0 Qa2 Qa3 Db0 Db1 Db2 Db3 tAC tOH Row Active Read Command Prechar ge Command Row Active Write Command Prechar ge Command tRCD
Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency 2, Burst Length = 4 CLK CKE CS RAS CAS ADDR A12. A13 A10 DQ WE UDQM, LDQM Row Active High tOLZ Db tSI Qc tHI Qa tOH Ra lOWD BS BS BSBSBS Ra Cc CbCa tOHZ tAC tHI tSI tSI tHI tHI tSI tSI tHI tHI tSI ICCD tSI tCL tCC tCH Read Command Write Command Read Command Precharge Command
*Notes: 1. When CS is set “High” at a clock transition from “L ow” to “High”, all inputs except CLK, CKE, UDQM and LDQM are invalid. 2. When issuing an active, read or write co mmand, the bank is selected by A12 and A13. A11 A12 Active, read or write 0 0 Bank A 0 1 Bank B 1 0 Bank C 1 1 Bank D 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 A12 A13 Operation 0 0 0 After the end of burst, bank A holds the idle status. 1 0 0 After the end of burst, bank A is precharged automatically. 0 0 1 After the end of burst, bank B holds the idle status. 1 0 1 After the end of burst, bank B is precharged automatically. 0 1 0 After the end of burst, bank C holds the idle status. 1 1 0 After the end of burst, bank C is precharged automatically. 0 1 1 After the end of burst, bank D holds the idle status. 1 1 1 After the end of burst, bank D is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10 and A11 inputs. A10 A12 A13 Operation 0 0 0 Bank A is precharged. 0 0 1 Bank B is precharged. 0 1 0 Bank C is precharged. 0 1 1 Bank D is precharged. 1 X X All banks are precharged. 5. The input data and the write command are la tched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1CLK+ t OHZ ) after UDQM, LDQM entry.
Page Read & Write Cycle (Same Bank) @CAS La tency 2, Burst Length = 4 *Notes: 1. To write data before a burst read ends, UDQM and LDQM should be asserted three cycles prior to the write command to avoid bus contention. 2. To assert row precharge before a burst write ends, wait t WR after the last write data input. Input data during the precharge input cycle will be masked internally. CLK CKE CS RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM Read Command Read Command Write Command Write Command Precharge Command Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Cc0 Cd0Ca0 Cb0 tWR ICCD Note 2 Note 1 Bank A Active lOWD High
Burst Read & Single Write Cycle (Same Bank) @CAS La tency 2, Burst Length = 4 *Note: 1. If you set A9 to high during mode register set cycle, the write burst length is set to 1. CLK CKE CS RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM tOH Ra Ca0 Qa1 Cc0Cb0 Ra Qa0 Qa2 Qa3 Qc0 Qc1 Qc2 Qc3 tAC tOH Row Active Read Command Write Command Read Command Prechar ge Command tRCD Db0 BS BS BSBS Note 1
Read & Write Cycle with Auto Precharge @ Burst Length 4 CLK CKE CS RAS CAS ADDR A12, A13 A10 WE A-Bank Precharge Start Row Active (B-Bank) A Bank Read with Auto Precharge B Bank Write with Auto Precharge B Bank Precharge Start Point A-Bank Precharge Start High Ra tRRD tWR Rb Ra Rb Ca Cb Db0 Db1 Db2 Db3 Qa0 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 CAS Latency=2 CAS Latency=3 Row Active (A-Bank) DQ DQ UDQM, LDQM UDQM, LDQM
Bank Interleave Rando m Row Read Cycle @CAS Latency = 2, Burst Length = 4 CLK CKE CS RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM RAa CAa RBb CBb RAc CAc RAa RBb RAc QAa0 QAa1 QAa2 QAa3 QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc 3 Row Active (A-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Row Active (B-Bank) Read Command (B-Bank) Precharge Command (B-Bank) Row Active (A-Bank) Read Command (A-Bank) tRRD tRC High
Bank Interleave Random Row Write Cycle @CAS L atency = 2, Burst Length = 4 CLK CKE CS RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM RAa CAa RBb CBb RAc CAc RAa RBb RAc DAa0 DAa1 DAa2 DAa3 Row Active (A-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Row Active (B-Bank) Write Command (B-Bank) Precharge Command (B-Bank) Row Active (A-Bank) Write Command (A-Bank) DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 High Precharge Command (A-Bank)
Bank Interleave Page Read Cycle @CA S Latency = 2, Burst Length = 4 *Note: 1. CS is ignored when RAS, CAS and WE are high at the same cycle. CLK CKE CS RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM RAa CAa RBb CBb CAc CBd CAe RAa RBb QAa0 QAa1 QAa2 QAa3 QBb 0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 Note 1 Row Active (A-Bank) Read Command (A-Bank) Row Active (B-Bank) Read Command (B-Bank) Precharge Command (A-Bank) Read Command (A-Bank) Read Command (A-Bank) Read Command (B-Bank) IROH High
Bank Interleave Page Write Cycle @CAS La tency = 2, Burst Length 4 CLK CKE CS RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Precharge Command (Both Bank) High RAa CAa RAa RBb RBb CBd DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 Write Command (B-Bank) Write Command (A-Bank) Write Command (B-Bank) DAa2 DAa1 DAa0 CAcCBb
Bank Interleave Random Ro w Read/Write Cycle @CAS Latency = 2, Burst Length = 4 CLK CKE CS RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM RAa CAa RBb CBb RAc CAc RAa RBb RAc QAa0 QAa1 QAa2 QAa3 QBb 0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3 Row Active (A-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Row Active (B-Bank) Write Command (B-Bank) Row Active (A-Bank) Read Command (A-Bank) High
Bank Interleave Page Read/Write Cycle @CAS L atency = 2, Burst Length = 4 CLK CKE CS RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM CAa0 CBb0 CAc0 QAa0 QAa1 QAa2 QAa3 Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 High QAc2 QAc3
Clock Suspension & DQM Operation Cycle @CAS L atency = 2, Burst Length = 4 *Note: 1. When Clock Suspension is asse rted, the next clock cycle is ignored. 2. When UDQM and LDQM are asserted, the read data after two clock cycles is masked. 3. When UDQM and LDQM are asserted, the write data in the same clock cycle is masked. 4. When LDQM is set High, the input/output data of DQ1 – DQ8 is masked. 5. When UDQM is set High, the input/output data of DQ9 – DQ16 is masked. CLK CKE CS RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM Ra Ca Cb Cc Ra Qa0 Qa1 Qa2 Qb0 Qb1 Dc0 Note 1 Row Active Read Command CLOCK Suspension Read DQM CLOCK Suspension Read Command Write Command Read DQM Note 1 Note 2 Note 3 tOHZ Write DQM Write DQM tOHZ Dc2
Read to Write Cycle (Same Bank) @CAS La tency = 2, Burst Length = 4 *Note: 1. In Case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles. UDQM, LDQM must be high at least 3 clocks prior to the write command. CLK CKE CS RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM Ra Ca0 Cb0 Ra Db0 Db1 Note 1 Row Active Read Command Write Command Precharge Command tWR tRCD Db2 Db3Da0
Read Interruption by Precharge Command @Burst Length 8 *Note: 1. If row precharge is asserted before a burs t read ends, then the read data will not output after l ROH equals CAS latency. CLK CKE CS RAS CAS ADDR A12, A13 A10 WE CAS Latency=2 CAS Latency=3 Ra Ca Ra Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Row Active Read Command Precharge Command lROH Qa5 lROH High DQ DQ UDQM, LDQM UDQM, LDQM
Burst Stop Command @Burst Length = 8 CLK CKE CS RAS CAS ADDR A12, A13 A10 WE CAS Latency = 2 CAS Latency = 3 Qa0 Qa1 Qa2 Qa3 Qa4 Qa0 Qa1 Qa2 Qa3 Qa4 Read Command Cb Qb0 Qb1 Qb2 Qb3 Qb4 Qb0 Qb1 Qb2 Qb3 Qb4 Burst Stop Command Write Command Burst Stop Command High Ca DQ DQ UDQM, LDQM UDQM, LDQM
Power Down Mode @CAS Latency = 2, Burst Length = 4 ote: 1. When both banks are in precharge state, and if CKE is set low, then the MD56V62160E enters power-down mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for longer than t PDE (tSI + 1CLK). CLK CKE CS RAS CAS ADDR A12, A13 A10 DQ WE UDQM, LDQM Ra Ca Ra Qa0 Qa1 Qa2 Note 2 Power-down Entry Row Active Power-down Exit Precharge Command Read Command Clock Suspension Exit tSI Note 1 Clock Suspension Entry tPDE tSI tSI tREF (min.)
A12, A13 A10 DQ WE UDQM, LDQM Ra BS Ra Self Refresh Entry Self Refresh Exit Row Active tSI tRC Hi-Z
Mode Register Set Cycle Auto Refresh Cycle CLK CKE CS RAS CAS ADDR DQ WE UDQM, LDQM New Command lMRD Auto Refresh tRC MRS Auto Refresh Key Ra Hi - Z Hi - Z High High
FUNCTION TRUTH TABLE (Table 1) (1/2) Current State1 CS RAS CAS WE BA ADDR Action H X X X X X NOP L H H H X X NOP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA Row Active L L H L BA A10 NOP 4 L L L H X X Auto-Refresh or Self-Refresh 5 Idle L L L L L OP Code Mode Register Write H X X X X X NOP L H H X X X NOP L H L H BA CA, A10 Read L H L L BA CA, A10 Write L L H H BA RA ILLEGAL 2 L L H L BA A10 Precharge Row Active L L L X X X ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L X X Term Burst --> Row Active L H L H BA CA, A10 Term Burst, start new Burst Read 3 L H L L BA CA, A10 Term Burst, start new Burst Write 3 L L H H BA RA ILLEGAL 2 L L H L BA A10 Term Burst, execute Row Precharge Read L L L X X X ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L X X Term Burst --> Row Active L H L H BA CA, A10 Term Burst, start new Burst Read 3 L H L L BA CA, A10 Term Burst, start new Burst Write 3 L L H H BA RA ILLEGAL 2 L L H L BA A10 Term Burst, execute Row Precharge 3 Write L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End and enter Row Precharge) L H H H X X NOP (Continue Burst to End and enter Row Precharge) L H H L BA X ILLEGAL 2 L H L H BA CA, A10 ILLEGAL 2 L H L L X X ILLEGAL L L H X BA RA, A10 ILLEGAL 2 Read with Auto Precharge L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End and enter Row Precharge) L H H H X X NOP (Continue Burst to End and enter Row Precharge) L H H L BA X ILLEGAL 2 Write with Auto Precharge L H L H BA CA, A10 ILLEGAL 2
FUNCTION TRUTH TABLE (Table 1) (2/2) Current State1 CS RAS CAS WE BA ADDR Action L H L L X X ILLEGAL L L H X BA RA, A10 ILLEGAL 2 Write with Auto Precharge L L L X X X ILLEGAL H X X X X X NOP --> Idle after tRP L H H H X X NOP --> Idle after tRP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 NOP 4 Precharge L L L X X X ILLEGAL H X X X X X NOP L H H H X X NOP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 Write Recovery L L L X X X ILLEGAL H X X X X X NOP --> Row Active after tRCD L H H H X X NOP --> Row Active after tRCD L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 Row Active L L L X X X ILLEGAL H X X X X X NOP --> Idle after tRC L H H X X X NOP --> Idle after tRC L H L X X X ILLEGAL L L H X X X ILLEGAL Refresh L L L X X X ILLEGAL H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL L H L X X X ILLEGAL Mode Register Access L L X X X X ILLEGAL ABBREVIATIONS RA = Row Address BA = Bank Address NOP = No OPeration command CA = Column Address AP = Auto Precharge Notes : 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of l CCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle.
FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) CKEn-1 CKEn CS RAS CAS WE ADDR Action H X X X X X X INVALID L H H X X X X Exit Self Refresh --> ABI L H L H H H X Exit Self Refresh --> ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL Self Refresh 6 L L X X X X X NOP (Maintain Self Refresh) H X X X X X X INVALID L H H X X X X Exit Power Down --> ABI L H L H H H X Exit Power Down --> ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL 6 Power Down 6 L L X X X X X NOP (Continue power down mode) H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H L X ILLEGAL H L L L L H X Enter Self Refresh H L L L L L X ILLEGAL All Banks Idle 7 (ABI) L L X X X X X NOP H H X X X X X Refer to Operations in Table 1 H L X X X X X Begin Clock Suspend Next Cycle L H X X X X X Enable Clock of Next Cycle Any State Other than Listed Above L L X X X X X Continue Clock Suspension *Notes : 6. If the minimum set-up time t PDE is satisfied when CKE transition from “L” to “H”, CKE operates asynchronously so that a command can be input in the same internal clock cycle. 7. Power-down and self-refresh can be entered only when all the banks are in an idle state.
Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (Unit: mm)
REVISION HISTORY
No. Date Previous Edition Current Edition FEDD56V62160E-01 Feb. 4, 2002 – – First edition FEDD56V62160E-02 Feb. 22, 2002 8 8 Change tRAS and tRC Specification FEDD56V62160E-03 Mar. 18, 2002 1, 7, 8, 15, 24, 25 1, 7, 8, 15, 24, 25 Delete “CAS latency =1” FEDD56V62160E-04 Oct. 15, 2011 – – Company name and Logo changed. FEDD56V62160E-05 Feb. 13, 2012 4 Deleted BLOCK DIAGRAM Deleted PACKAGE DIMENSIONS FEDD56V62160E-06 May 29, 2012 1,5,7,8 1,5,7,8 Deleted Speed rank 7 FEDD56V62160E-07 Nov. 18, 2013 1 Added package code Added PACKAGE DIMENSIONS
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