FE3V3C4S1 FUTUREWAFER | Alldatasheet
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Chip low capacitance 4 - fold ESD protection diode Mechanical Data Notes Dice size AX:1400um,AY:800um/BX=290um,BY:200um/P1,2,4,6-290*200um Wafer size 4” (Gross die:5,940pcs/Good die>5,525pcs) Chip Thickness 230um±20um Scribe line width 60um Top metal Al/Au/Ag Back side metal Al/Au/Ag/Sn Parameter Symbol Conditions Value Unit Reverse stand-off voltage VRWM 3.3 V Peak pulse power PPP Tp=8/20us 200* W Peak pulse current IPP Tp=8/20us 12.0* A Electrostatic discharge VESD IEC61000-4-2 Level 4 >15(Contact) >25(Air) KV Max.junction temp. Tj +125 °C Parameter Symbol Condition Min. Typ. Max. Unit Snap Back Voltage VSB IR=50mA 2.85 V Reverse leakage current IR V=3.3V 0.4 uA Punch Through Voltage VPT IR=1.5uA 3.55 V Forward Voltage (pins 1,3,4,6 to pins 2,5) VF IF=1A 1.7 V Clamping voltage (pins 1,3,4,6 to pins 2,5) VC IPP=1.0A IPP=5.0A 4.5* 6.8* V Junction capacitance (pins 1,3,4,6 to pins 2,5) Cj VR=0V f=1MHZ 40 pf Characteristics TA=25°C FE3V3C4S1 EW1608D6-FW-A Notes: (1)sampling testing:no bad dice inking/guaranteed good die >93% (2)Testing follow customer (3)Tj=Ta+Rth(j-a)*(pf+pr),where Rth(j-a)-thermal resistance,Pf-forward power dissipation, Pr-revers power dissipation (4)**For device testing Futurewafer Technology Co.,Ltd www.futurewafer.com.tw+886-3-3573583