FE175D480C033FP-00

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Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 20

Technical content

Features

• Com plete A C-D C PCB-m ounted solution
• A ctive Pow er Factor Correction (PFC)
• Rectification
• Filtering
• Transient protection
• Low profile package, 9 .5 5 m m height above board
• Pow er density: 121 W /in 3 , 3 3 0 W in 7 .2 in 2 footprint
• Consistent high efficiency over w orld-w ide A C m ains (85 – 26 4 Vac)
• Secondary-side energy storage
• SELV 48 V O utput – Efficient pow er distribution to PO L converters
• 3 ,000 Vac /4,242 Vdc isolation
• PFC (TH D ) exceeds EN 6 1000-3 -2 requirem ents
• Conducted em issions EN 5 5 022, Class B (w ith a few external com ponents)
• Surge im m unity EN 6 1000-4-5
• ZVS high frequency (M H z) sw itching
• Low profile, high-density filtering
• 100 °C baseplate operation Typical A pplications
• LED - Lighting, display, signage
• Telecom (W iM A X, Pow er A m plifiers, O ptical Sw itches)
• A utom atic Test Equipm ent (A TE)
• H igh Efficiency Server Pow er
• O ffice Equipm ent (Printers, Copiers, Projectors)
• Industrial Equipm ent (Process Controllers, M aterial H andling, Factory A utom ation) Product O verview The VI BRICK® AC Front End is an AC-to-DC converter, operating from a universal AC input to generate an isolated and regulated 48 Vdc output with power factor correction. The module incorporates rectification, transient and surge suppression and AC to DC conversion to provide a complete AC to DC solution in a thin profile package. With its ZVS high frequency Adaptive CellTM topology, the VI BRICK AC Front End module consistently delivers high efficiency across worldwide AC mains. Downstream DC-DC converters support secondary- side energy storage and efficient power distribution, providing superior power system performance and connectivity from the wall plug to the point-of-load. C US

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 2 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 85 -

264 Vac

1.0 V Load +OUT +OUT –OUT –OUT AC (L) AC (N) DC-DC Converter MOV VI BRICK® AC Front End Holdup Capacitor Gnd Gnd FUSE Typical A pplication: U niversal A C to 1 2 V and 1 V, total 3 0 0 W Param eter Com m ents M in M ax U nit Input voltage A C (L) to A C (N) C ontinuous 27 5 VA C Input voltage A C (L) to A C (N) 1 m s 0 600 Vpk Input voltage slew rate 25 V/µs R SV1 to –IN Do not connect to this pin -0.3 5 .3 VDC EN to –IN 5 V tolerant 3 .3 V logic -0.3 5 .3 VDC R SV3 to –IN Do not connect to this pin -0.3 5 .3 VDC O utput voltage (+O ut to -O ut) -0.5 5 7 .0 VDC O utput current 0.0 10.2 A Tem perature O perating junction W orst case sem iconductor 0 125 °C O perating tem perature C -G rade; baseplate -20 100 °C T-G rade; baseplate -4 0 100 °C M -G rade; baseplate -5 5 100 °C Storage tem perature C -G rade -4 0 125 °C T-G rade -4 0 125 °C M -G rade -65 125 °C D ielectric W ithstand Dielectric W ithstand Input – O utput 3 000 VR M S Dielectric W ithstand Input – Base 15 00 VR M S Dielectric W ithstand O utput – Base 15 00 VR M S A bsolute M axim um Ratings The A BSO LUTE M A XIM UM R atings below are stress ratings only. O peration at or beyond these m axim um ratings can cause perm anent dam age to device. Electrical specifications do not apply w hen operating beyond rated operating conditions. P ositive pin current represents current flow ing out of the pin.

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 3 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0

Electrical Characteristics

Specifications apply over all line and load conditions, 5 0 H z and 60 H z line frequencies, T C = 25 °C , unless otherw ise noted. Boldface specifications apply over the tem perature range of the specified P roduct G rade. C O UT is 6800uF +/- 20% unless otherw ise specified. A ttribute Sym bol Conditions / N otes M in Typ M ax U nit Pow er Input Specification Input voltage range, VIN 8 5 2 64 VR M S continuous operation Input voltage cell reconfiguration VIN -C R + 14 5 1 48 VR M S low -to-high threshold Input voltage cell reconfiguration VIN -C R - 1 3 2 13 5 VR M S high-to-low threshold Input current (peak) IINR P 12 A Source line frequency range fline 4 7 63 H z P ow er factor P F Input pow er > 100 W 0.9 - Input inductance, (external) LIN Differential-m ode inductance, com m on- 1 m H m ode inductance m ay be higher N o Load Specification Input pow er – no load, m axim um P NL EN floating, see Figure 4 1.1 1.5 W Input pow er – disa bled, m axim um P Q EN pulled low , see Figure 5 1.6 W Pow er O utput Specification O utput voltage set point VO UT Vin = 23 0 Vrm s, 10% Load 4 7 .5 4 9 5 0.5 V O utput voltage, no load VO UT -NL O ver all operating steady 46 5 1.5 55 Vstate line conditions O utput voltage range (transient) VO UT Non-faulting abnorm al line and load 3 0 55 Vtransient conditions O utput pow er P O UT See Figure 1, Safe O perating A rea 3 3 0 W VIN = 23 0 V, full load 91 94 % Efficiency h 85 V < V IN < 264 V, full load, see Fig. 2 8 8 .5 %

85 V < V IN < 264 V, 7 5 % load 89 %

O utput voltage ripple, VO UT -P P -H F O ver all operating steady-state line and sw itching frequency load conditions, 20 M H z BW , m easured at C 3 , Fig 28. 100 3 0 0 m V O utput voltage ripple VO UT -P P -LF O ver all operating steady-state line and line frequency load conditions, 20 M H z BW 3 .8 5V O utput capacitance (external) C O UT -EXT 6,0 0 0 1 2 ,0 0 0 µF O utput turn-on delay TO N From V IN applied, EN floating 4 00 1 0 0 0 m s From EN pin release, V IN applied Start-up setpoint acquisition tim e Tss Full load 4 00 5 00 m s C ell reconfiguration response tim e TC R Full load 5 .5 11 m s Voltage deviation (load transient) % V O UT -TR A NS C O UT = M ax 8% R ecovery tim e TTR A NS 25 0 5 00 m s Line regulation % V O UT -LINE Full load 0.5 1% Load regulation % V O UT -LO A D 10% to 100% load 0.5 1% O utput current (continuous) IO UT See Figure 1, SO A 6.9 A

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 5 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 No connections should be m ade to these pins RESERVED : RSV1, RSV3

• W arning: -IN and N are not at the sam e potential and m ust not be connected together.
• The -IN pin is the signal reference ground for the EN pin
• The -IN pin also serves as an access point for the com m on m ode bypass filter to com ply w ith EN5 5 022 C lass B for C onducted Em issions. -IN EN A BLE : EN
• The EN pin enables and disables the VI BR IC K ® A C Front End; w hen held below 0.8 V the unit w ill be disabled.
• The EN pin can reset the VI BR IC K A C Front End after a latching O VP event.
• The EN pin voltage is 3 .3 V during norm al operation.
• The EN pin is referenced to the –IN pin of the m odule. Signal Type State A ttribute Sym bol Conditions / N otes M in Typ M ax U nit Startup EN enable threshold VEN _EN 2 .0 0 V Digital Input EN disable tim e TEN _DIS From any point in line cycle 9 1 6 m s Standby EN disable threshold VEN _DIS 0 .8 0 V EN resistance to R EN _EXT M ax allow able resistance to 1 4 kΩ disable -IN required to disable the m odule Signal Characteristics Specifications apply over all line and load conditions, 5 0 H z and 60 H z line frequencies, T C = 25 °C , unless otherw ise noted. Boldface specifications apply over the tem perature range of the specified P roduct G rade.

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 6 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 +OUT -OU T Prima ry & Se cond ary Powertrain Cell Conf ig uati on Co ntrolle r VEAO RSV3 EN RSV1 Input UVP & OVP Internal OTP / UTP Out put OV P Output OCP/SCP Enabl e PFC Cont rol Micr o contr oller Fault Latch & Re se t L ogi c 3.3 V Q3 T Ref erence Volta ge wit h Ri pple Twice the Sup ply Fr equ ency Q1 T Q2 T Q4 T Auto Ranger Cont rol VIN- B VIN-B Output Voltage with Offset Fault monitoring Error Amplifi er COUT-INT CIN -T CIN-B -I N -IN -I N -I N 49.9 kΩ Q3 B Q1 B Q2 B Q4 B VEA OPowertrain En abl e Adapti ve Cell ™ Top olo gy Bott om Cell Top Cell -I N Microcontroller: Fault Monitoring and PFC Prima ry- side Volta ge Se nse Rectifier Filter Transient Supression Modulator AC L N Functional Block D iagram

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 7 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 OPERAT IONAL VOUT Ra mp Up (tss) Regulate s VOUT Powertr ain : Act ive RNG: A uto PFC : Auto STAN DBY Po wer train : St oppe d RNG: Hig h Appli catio n of VIN EN = True and No Fault s LATCH ED FAULT Po wer trai n: Stopp ed RNG: Hi gh VIN > VIN- UVL O+ START UP SE QUENCE Li ne Freq uenc y Acqui sitio n Po wer trai n: Stopp ed RNG: Auto tON Expiry EN = Fals e or VIN Out of Rang e EN = False or VIN Out of Range NON LATCHED FAULT tOFF delay Po wer trai n: Stopp ed RNG: Hi gh Overtem p, Output Short, or Ov erlo ad Output OV P No Fault s EN Fall ing Edge H igh Level Functional State D iagram Conditions that cause state transitions are show n along arrow s. Sub-sequence activities listed inside the state bubbles.

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 8 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 VIN-RM S EN VOUT ILOAD Input Po wer On & UV Turn-on Ful l Load App lied EN Force d Low EN High Rang e Ch ang e LO to HI Rang e Ch ang e HI to LO Load Du mp Load Step Input Po wer Off & UV Turn-off In put Output tCR tON VIN-UVL O+ ≈30 VRMS 10% Load App lied tCR tTRANS (2 p lace s) VIN-UVL O- VIN-C R+ VIN-CR- VOUT-NL VOU T tON tUV LOtEN-DIS tSS VIN-RM S VOUT ILOAD tON VIN-UVL O+ tOC tOFF+tON tOFF+tON tOC ≥tOFF+tON VOU T-OVLO + tSOV P tON tSS VIN -UVLO- tSC tOFF+tON tOF F+tON EN tOC Input Po wer ON & UV Turn-o n Output OC Fault Outp ut OC Recovery Output OVP Faul t Togg le EN (O utput OVP Recovery) Out put OV P Fault Re cycle Inpu t Power (Ou tput OVP Re covery) Output SC Fault Outp ut SC Re covery OT F ault Re covery Lin e Drop-Out In put Power Off & UV Turn-off In put Output tON VIN-UVL O+ )))) )))) )))) * * Figure 3 — Tim ing diagram - *N egative current is externally forced and show n for the purpose of O VP protection scenario. Tim ing D iagram s M odule Inputs are show n in blue ; M odule O utputs are show n in brow n .

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 10 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 Figure 10 – Typical startup w aveform , EN pin release, V IN = 2 3 0 V, RLO AD = 7 .1 Ω, C O U T = 6,8 0 0 µF. Figure 11 – Line drop out, 5 0 Hz, 0 ° phase, PLO AD = 3 3 0 W , C O U T = 6,8 0 0 µF. Figure 12 – Line drop out, 5 0 Hz, 9 0 ° phase, V IN = 2 3 0 V, PLO AD = 3 3 0 W , C O U T = 6,8 0 0 µF. C Output: 90% Load (297W) SGL 1QP 150 kHz 30 MHz Unit dBÌV ResBW 9 kHz Meas T 20 ms Det QP/AV Att 20 dB INPUT 2 29.Aug 2012 11:01 Trd 55022RED

1 MHz 10 MHz

Date: 29.AUG.2012 11:01:40 Figure 13 – Typical EM I spectrum , Q uasi-Peak Scan, 9 0 % load, 2 3 0 V IN , C O U T = 6,8 0 0 µF. Test circuit - Figure 2 8 . Figure 15 – Typical EM I spectrum , Q uasi-Peak Scan, 9 0 % load, 115 V IN , C O U T = 6,8 0 0 µF. Test circuit - Figure 2 8 . C Output: 90% Load (297W) SGL 150 kHz 30 MHz Unit dBÌV ResBW 9 kHz Meas T 20 ms Det QP/AV Att 20 dB INPUT 2 Trd 55022RED 2AV 29.Aug 2012 11:02 Date: 29.AUG.2012 11:02:41 Figure 14 – Typical EM I spectrum , Average Scan, 9 0 % load, 2 3 0 V IN , C O U T = 6,8 0 0 µF. Test circuit - Figure 2 8 . A pplication Characteristics (cont.) The follow ing figures present typical perform ance at T C= 25 ºC, unless otherw ise noted. See associated figures for general trend data.

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 11 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 Figure 18 – Typical input current harm onics, full load vs. V IN . Figure 17 – Typical line current w aveform , 60 Hz, V IN = 12 0 V, PLO AD = 3 3 0 W . C O U T = 6,8 0 0 µF. Load Current (A) Power Factor Power Factor vs. Load and VIN at 25 °C V :IN 100 V 115 V 240 V .750 .800 .850 .900 .950 1.000 0 1 2 3 4 5 6 7 Efficiency & Power Dissipation -55 °C Case Efficiency (%) Load Current (A)

100 V Power Diss 115 V Power Diss 240 V Power Diss

V :IN 100 V Eff 115 V Eff 240 V Eff 76% 78% 80% 82% 84% 86% 88% 90% 92% 94% 96% Figure 19 – Typical pow er factor vs. V IN and I O U T . Figure 20 – VIN to V O U T efficiency and pow er dissipation vs. V IN and I O U T , T C ASE = -5 5 ºC . C O SGL 150 kHz 30 MHz Unit dBÌV Trd 55022RED ResBW 9 kHz Meas T 1 s Det MA/AV Att 20 dB INPUT 2 26.Jul 2012 16:36 2AV Date: 26.JUL.2012 16:36:57 Figure 16 – Typical EM I spectrum , Average Scan, 9 0 % load, 115 V IN , C O U T = 6,8 0 0 µF. Test circuit - Figure 2 8 . Efficiency & Power Dissipation 25 °C Case Efficiency (%) Load Current (A) V :IN 100 V Eff 115 V Eff 240 V Eff 76% 78% 80% 82% 84% 86% 88% 90% 92% 94% 96% Figure 21 – VIN to V O U T efficiency and pow er dissipation vs. V IN and I O U T , T C ASE = 2 5 ºC . A pplication Characteristics (cont.) The follow ing figures present typical perform ance at T C= 25 ºC, unless otherw ise noted. See associated figures for general trend data. Current [mA] Input Current Harmonics vs. Input Voltage 100 200 300 400 500 600 700 800 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

230 V, 50 Hz 1/3x EN61000-3-2, Class A EN61000-3-2, Class D

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 12 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 Efficiency & Power Dissipation 100 °C Case Efficiency (%) Power Dissipation (W) 76% 78% 80% 82% 84% 86% 88% 90% 92% 94% 96% Load Current (A) V :IN 100 V Eff 115 V Eff 240 V Eff Figure 22 – VIN to V O U T efficiency and pow er dissipation vs. V IN and I O U T , T C ASE = 10 0 ºC . 0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 Thermal Resistance (°C/W) Air Flow (LFM) Thermal Resistance (Baseplate to Air) vs. Air Flow INSULATED UNINSULATED Figure 23 – Baseplate to air therm al resistance Insulated – no therm al dissipation through pins to pcb; U ninsulated – therm al dissipation to typical pcb. A pplication Characteristics (cont.) The follow ing figures present typical perform ance at T C= 25 ºC, unless otherw ise noted. See associated figures for general trend data.

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 13 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 G eneral Characteristics Specifications apply over all line and load conditions, 5 0 H z and 6 0 H z line frequencies, TC = 25 °C, unless otherw ise noted. Boldface specifications apply over the tem perature range of the specified Product G rade. A ttribute Sym bol Conditions / N otes M in Typ M ax U nit M echanical Length L 95 .3 /[3 .7 5 ] m m /[in] W idth W 4 8.6 /[1.91] m m /[in] H eight H 9.5 5 /[0.3 8] m m /[in] Volum e Vol 4 4 .2 /[2.69] cm 3 /[in 3 ] W eight W 111 /[3 .9] g/[oz] P in m aterial C 10200 copper, full hard Underplate Nickel 100 15 0 µin P in finish P ure m atte tin, 200 3 00 w hisker resistant chem istry Therm al O perating baseplate (case) A ny operating C - G rade -20 100 °C tem perature TC condition T - G rade -4 0 100 °C M - G rade -5 5 100 °C Therm al resistance, baseplate- 0.13 °C /Wto-sink, flat greased surface Therm al resistance, baseplate- 0.17 °C /Wto-sink, therm al pad (P N 3 6967 ) Therm al capacity 84 .5 W s /°C Therm al design See Therm al Design on page 18 A ssem bly ESD H BM H um an Body M odel, 1,000 “JEDEC JESD 22-A 114 C .01” ESD rating ESD M M M achine M odel, N/A V “JEDEC JESD 22-A 115 B” ESD C DM C harged Device M odel, 200 “JEDEC JESD 22-C 101D” Soldering See application note Soldering M ethods and P rocedure for Vicor P ow er M odules » Safety & Reliability cTÜ Vus (EN6095 0-1) cUR us (UL/C SA 6095 0-1) A gency approvals /standards C E, Low Voltage Directive 2006/95 /EC Touch C urrent m easured in accordance w ith IEC 60990 using 0.5 6 0.68 m A m easuring netw ork Fig. 4 EM I/EM C Com pliance FC C P art 15 , EN5 5 022, C lass B Lim its - w ith C ISP R 22: 2006 + A 1: 2007 , com ponents connected C onducted Em issions as show n in Figure 28 EN61000-3 -2: 2009, C lass A H arm onic C urrent Em issions EN61000-3 -3 : 2005 , P ST <1.0; P LT <0.65 ; dc<3 .3 % ; Voltage C hanges & Flicker dm ax<6%

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 14 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 Figure 24 — Product outline draw ing; Product outline draw ings are available in .pdf and .dxf form ats. 3 D m echanical m odels are available in .pdf and .step form ats. See http://w w w .vicorpow er.com /cm s/hom e/technical_resources/M echanical_Draw ings/M odules for m ore details. A ttribute Sym bol Conditions / N otes M in Typ M ax U nit EM I/EM C Com pliance (cont.) EN61000-4 -4 : 2004 , Level 3 , Electrical Fast Transients P erform ance C riteria A EN61000-4 -5 : 2006, Level 3 , Im m unity C riteria A , Surge Im m unity external TM O V required, lim it input transient to 7 5 0 V EN61000-4 -6: 2009, Level 2, 13 0 dBµV (3 .0 V R M S )C onducted R F Im m unity EN61000-4 -8: 1993 + A 1 2001, P ow er Frequency H -Field 10A /m , Level 3 , P erform ance C riteria A continuous field EN61000-4 -11: 2004 , C lass 2, P erform ance C riteria A Voltage Dips & Interrupts Dips, P erform ance C riteria B Interrupts G eneral Characteristics (cont.) Specifications apply over all line and load conditions, 5 0 H z and 6 0 H z line frequencies, TC = 25 °C, unless otherw ise noted. Boldface specifications apply over the tem perature range of the specified Product G rade. Product O utline D raw ing and Recom m ended PCB Footprint M odule O utline

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 15 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 Figure 25 — Recom m ended PC B pattern; Product outline draw ings are available in .pdf and .dxf form ats. 3 D m echanical m odels are available in .pdf and .step form ats. See http://w w w .vicorpow er.com /cm s/hom e/technical_resources/M echanical_Draw ings/M odules for m ore details. Product O utline D raw ing and Recom m ended PCB Footprint (cont.) M ounting Specifications

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 16 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 Building Blocks and System D esigns The VI BRICK® AC Front End is a high efficiency AC-to-DC converter, operating from a universal AC input to generate an isolated SELV 48 VDC output bus with power factor correction. It is the key component of an AC-to-DC power supply system such as the one shown in Figure 26 above. The input to the VI BRICK AC Front End is a sinusoidal AC source with a power factor maintained by the module with harmonics conforming to IEC 61000-3-2. Internal filtering enables compliance with the standards relevant to the application (Surge, EMI, etc.). See EMI/EMC Compliance standards on page 13. The module uses secondary-side energy storage (at the SELV

48 V bus) and optional PRM™ regulators to maintain output hold up

through line dropouts and brownouts. Downstream regulators also provide tighter voltage regulation, if required. The FE175D480C033FP-00 is designed for standalone operation ; however, it may be part of a system that is paralleled by downstream DC-DC converters. Contact Vicor Sales or refer to our website, www.vicorpower.com , regarding new models that can be paralleled directly for higher power applications . Traditional PFC Topology To cope with input voltages across worldwide AC mains (85 –264 Vac), traditional AC-DC power supplies (Figure 27) use two power conversion stages: 1) a PFC boost stage to step up from a rectified input as low as 85 Vac to ~380 Vdc; and 2) a D C-DC down converter from 380 Vdc to a 12 V bus. The efficiency of the boost stage and of traditional power supplies is significantly compromised operating from worldwide AC lines as low as 85 Vac. A daptive Cell™ Topology With its single stage Adaptive Cell™ topology, the VI BRICK AC Front End enables consistently high efficiency conversion from worldwide AC mains to a 48 V bus and efficient secondary-side power distribution. Pow er Factor Correction The module provides power factor correction over worldwide AC mains. For most static loads, PFC approaches unity, see Figure 19. Load transients that approach the line frequency should be filtered or avoided as these may reduce PFC. Input Fuse Selection VI BRICK products are not internally fused in order to provide flexibility in configuring power systems. Input line fusing is recommended at system level, in order to provide thermal protection in case of catastrophic failure. The fuse shall be selected by closely matching system requirements with the following characteristics: – R ecom m ended fuse: 5 A , 216 Series Littelfuse – C urrent rating (usually greater than the VI BRIC K AC Front End m axim um current) – M axim um voltage rating (usually greater than the m axim um possible input voltage) – A m bient tem perature – Breaking capacity per application requirem ents – Nom inal m elting I 2t Fault H andling Input U ndervoltage (U V) Fault Protection The VI BRICK AC Front End’s input voltage (proportional to V In -Bas shown on page 6) is monitored by the micro-controller to detect an input under voltage condition. When the input voltage is less than the VIn -uVLo -, a fault is detected, the fault latch and reset logic disables the modulator, the modulator stops powertrain switching, and the output voltage of the unit falls. Aer a time t uVLo , the unit shuts down. Faults lasting less than t uVLo may not be detected. Such a fault does not go through an auto-restart cycle. once the input voltage rises above V In - uVLo +, the unit recovers from the input uV fault, the powertrain resumes normal switching aer a time t on and the output voltage of the unit reaches the set-point voltage within a time t SS . O vercurrent (O C) Fault Protection The unit’s output current, determined by V EAo , V In _Band the primary- side sensed output voltage, (as shown on page 6) is monitored by the microcontroller to detect an output oC condition. If the output current exceeds its current limit, a fault is detected, the reset logic disables the modulator, the modulator stops powertrain switching, and the output voltage of the module falls aer a time t oC . As long as the fault persists, the module goes through an auto-restart cycle with off time equal to toFF + t on and on time equal to t oC . Faults shorter than a time t oC may not be detected. once the fault is cleared, the module follows its normal start up sequence aer a time t oFF . Short Circuit (SC) Fault Protection The microcontroller determines a short circuit on the output of the unit by measuring its primary sensed output voltage and EAo (as shown on page 6). Most commonly, a drop in the primary-sensed output voltage triggers a short circuit event. The module responds to a short circuit event within a time t SC . The module then goes through an auto restart cycle, with an off time equal to t oFF + t on and an on time equal to t SC , for as long as the short circuit fault condition persists. once the fault is cleared, the unit follows its normal start up sequence aer a time t oFF . Faults shorter than a time t SC may not be detected. Figure 26 – 3 0 0 W U niversal AC -to-DC Supply Full Wave Rectifier EMI/TVS Filter Isolated DC / DC Converter

12 V Bus

Figure 27 – Traditional PFC AC -to-DC supply

85 V – 264 Vac

48 Vdc

(Optional) VI BRICK AC Front End Holdup Capacitor MOV* +OUT +OUT –OUT –OUT AC (L) AC (N) Product D etails and D esign G uidelines

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 18 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 Based on the output current waveform, as seen in Figure 29, the following formula can be used to determine peak-to-peak line frequency output voltage ripple: In certain applications, the choice of bulk capacitance may be determined by hold-up requirements and low frequency output voltage filtering requirements. Such applications may use the greater capacitance value determined from these requirements. The ripple current rating for the bulk capacitors can be determined from the following equation: Sw itching Frequency Filtering Some applications require the output filtering shown in figure 28 to meet radiated emissions limits. In such a situation, the output switching ripple shown in figure 6 should be expected at the output of the filter. In cases where other means are used to control radiated emissions, and more ripple can be tolerated, the output filter can be simplified by removal of the common mode inductor, and C5, which is used to reduce the Q of the LC resonant tank. output switching frequency voltage ripple is the function of the output bypass ceramic capacitor. output bypass ceramic capacitor values should be calculated based on switching frequency voltage ripple. normally bypass capacitors with low ESR are used with a sufficient voltage rating. output bypass ceramic capacitor value for allowable peak-to-peak switching frequency voltage ripple can be determined by: EM I Filtering and Transient Voltage Suppression EM I Filtering The VI BRICK AC Front End with PFC is designed such that it will comply with En55022 Class B for Conducted Emissions with the filter connected across -In and GnD as shown in Figure 28. The emissions spectrum is shown in Figures 13-16. If one of the outputs is connected to earth ground, a small (single turn) output common mode choke is also required. EMI performance is subject to a wide variety of external influences such as PCB construction, circuit layout etc. As such, external components in addition to those listed herein may be required in specific instances to gain full compliance to the standards specified. Transient Voltage Suppression The VI Brick AC Front End contains line transient suppression circuitry to meet specifications for surge (i.e. En61000-4-5) and fast transient conditions (i.e. En61000-4-4 fast transient/“burst”). Therm al D esign Thermal management of internally dissipated heat should maximize heat removed from the baseplate surface, since the baseplate represents the lowest aggregate thermal impedance to internal components. The baseplate temperature should be maintained below 100 °C. Cooling of the system PCB should be provided to keep the leads below 100 °C, and to control maximum PCB temperatures in the area of the module. Pow ering a Constant Pow er Load When the output voltage of the VI BRICK AC Front End module is applied to the input of the PRM™ regulator, the regulator turns on and acts as a constant-power load. When the module’s output voltage reaches the input undervoltage turn on of the regulator, the regulator will attempt to start. However, the current demand of the PRM regulator at the undervoltage turn-on point and the hold-up capacitor charging current may force the VI BRICK AC Front End into current limit. In this case, the unit may shut down and restart repeatedly. In order to prevent this multiple restart scenario, it is necessary to delay enabling a constant-power load when powered up by the upstream AC to 48 V front end until aer the output set point of the VI BRICK AC Front End is reached. This can be achieved by 1) keeping the downstream constant-power load off during power up sequence and 2) turning the downstream constant-power load on aer the output voltage of the module reaches 48 V steady state. Aer the initial startup, the output of the VI BRICK AC Front End can be allowed to fall to 30 V during a line dropout at full load. In this case, the circuit should not disable the PRM™ regulator if the input voltage falls aer it is turned on; therefore, some form of hysteresis or latching is needed on the enable signal for the constant power load. The output capacitance of the VI BRICK AC Front End should also be sized appropriately for a constant power load to prevent collapse of the output voltage of the module during line dropout (see Hold up Capacitance on page 17). A constant-power load can be turned off aer completion of the required hold up time during the power-down sequence or can be allowed to turn off when it reaches its own undervoltage shutdown point. Product D etails and D esign G uidelines (cont.) C3 = QTOT / VOUT-PP -HF – COUT-INT where: VOUT-PP -HF Allowable peak-to-peak output switching frequency voltage ripple in volts QTOT The total output charge per switching cycle at full load, maximum 13.5 µC COUT_INT The module internal effective capacitance C3 Required output bypass ceramic capacitor 0.8 * P OUT / VOUTIripple = ~ = 0.2 * P OUT / ( VOUT * f LINE * C)VPP l where: VPP l Output voltage ripple Peak-to-peak line frequency POUT Average output power VOUT Output voltage set point, nominally 48 V fLINE Frequency of line voltage C Output bulk capacitance IDC Maximum average output current IPK Peak-to-peak line frequency output current ripple

The timing diagram in Figure 30 shows the output voltage of the VI BRICK AC Front End module and the PRM PC pin voltage and output voltage of the PRM regulator for the power up and power down sequence. It is recommended to keep the time delay approximately 10 to 20 ms. Special care should be taken when enabling the constant-power load near the auto-ranger threshold, especially with an inductive source upstream of the VI BRICK AC Front End. A load current spike may cause a large input voltage transient, resulting in a range change which could temporarily reduce the available power (see Adaptive Cell™ Topology below). A daptive Cell™ Topology The Adaptive Cell™ topology utilizes magnetically coupled “top” and “bottom” primary cells that are adaptively configured in series or parallel by a configuration controller comprised of an array of switches. A microcontroller monitors operating conditions and defines the configuration of the top and bottom cells through a range control signal. A comparator inside the microcontroller monitors the line voltage and compares it to an internal voltage reference. If the input voltage of the VI BRICK AC Front End crosses above the positive going cell reconfiguration threshold voltage, the output of the comparator transitions, causing switches S 1and S 2to open and switch S3to close (see Functional Block Diagram on page 6). With the top cell and bottom cell configured in series, the unit operates in “high” range and input capacitances C In -Tand C In -Bare in series. If the peak of input voltage of the unit falls below the negative-going range threshold voltage for two line cycles, the cell configuration controller opens switch S 3and closes switches S 1and S 2. With the top cell and bottom cells configured in parallel, the unit operates in “low” range and input capacitances C In -Tand C In -Bare in parallel. Power processing is held off while transitioning between ranges and the output voltage of the unit may temporarily droop. External output hold up capacitance should be sized to support power delivery to the load during cell reconfiguration. The minimum specified external output capacitance of 6,000 µ F is sufficient to provide adequate ride- through during cell reconfiguration for typical applications. VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 19 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 Product D etails and D esign G uidelines (cont.) VI BRICK™ AC Front End PRM™ Regulator PRM UV Turn on 49V – 3% PRM™ Regulator VOUT tDELAY tHOLD -UP VOUT PC Figure 30 – PRM Enable Hold off W aveform s

VI BRICK ® A C Front End Rev 1.1 vicorpow er.com Page 20 of 20 11/2012 800 7 3 5 .6 200 FE1 75D 48 0 C0 3 3 FP-0 0 Vicor’s com prehensive line of pow er solutions includes high density A C-D C and D C-D C m odules and accessory com ponents, fully configurable A C-D C and D C-D C pow er supplies, and com plete custom pow er system s. Inform ation furnished by Vicor is believed to be accurate and reliable. H ow ever, no responsibility is assum ed by Vicor for its use. Vicor m akes no representations or w arranties w ith respect to the accuracy or com pleteness of the contents of this publication. Vicor reserves the right to m ake changes to any products, specifications, and product descriptions at any tim e w ithout notice. Inform ation published by Vicor has been checked and is believed to be accurate at the tim e it w as printed; how ever, Vicor assum es no responsibility for inaccuracies. Testing and other quality controls are used to the extent Vicor deem s necessary to support Vicor’s product w arranty. Except w here m andated by governm ent requirem ents, testing of all param eters of each product is not necessarily perform ed. Specifications are subject to change w ithout notice. Vicor’s Standard Term s and Conditions A ll sales are subject to Vicor’s Standard Term s and C onditions of Sale, w hich are available on Vicor’s w ebpage or upon request. Product W arranty In Vicor’s standard term s and conditions of sale, Vicor w arrants that its products are free from non-conform ity to its Standard Specifications (the “Express Lim ited W arranty”). This w arranty is extended only to the original Buyer for the period expiring tw o (2) years after the date of shipm ent and is not transferable. UNLESS O TH ER W ISE EXP R ESSLY STA TED IN A W R ITTEN SA LES A G R EEM ENT SIG NED BY A DULY A UTH O R IZED VIC O R SIG NA TO R Y, VIC O R DISC LA IM S A LL R EP R ESENTA TIO NS, LIA BILITIES, A ND W A R R A NTIES O F A NY KIND (W H ETH ER A R ISING BY IM P LIC A TIO N O R BY O P ER A TIO N O F LA W ) W ITH R ESP EC T TO TH E P R O DUC TS, INC LUDING , W ITH O UT LIM ITA TIO N, A NY W A R R A NTIES O R R EP R ESENTA TIO NS A S TO M ER C H A NTA BILITY, FITNESS FO R P A R TIC ULA R P UR P O SE, INFR ING EM ENT O F A NY P A TENT, C O P Y R IG H T, O R O TH ER INTELLEC TUA L P R O P ER TY R IG H T, O R A NY O TH ER M A TTER . This w arranty does not extend to products subjected to m isuse, accident, or im proper application, m aintenance, or storage. Vicor shall not be liable for collateral or consequential dam age. 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Life Support Policy VIC O R ’S P R O DUC TS A R E NO T A UTH O R IZED FO R USE A S C R ITIC A L C O M P O NENTS IN LIFE SUP P O R T DEVIC ES O R SY STEM S W ITH O UT TH E EXP R ESS P R IO R W R ITTEN A P P R O VA L O F TH E C H IEF EXEC UTIVE O FFIC ER A ND G ENER A L C O UNSEL O F VIC O R C O R P O R A TIO N. A s used herein, life support devices or system s are devices w hich (a) are intended for surgical im plant into the body, or (b) support or sustain life and w hose failure to perform w hen properly used in accordance w ith instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical com ponent is any com ponent in a life support device or system w hose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. P er Vicor Term s and C onditions of Sale, the user of Vicor products and com ponents in life support applications assum es all risks of such use and indem nifies Vicor against all liability and dam ages. Intellectual Property N otice Vicor and its subsidiaries ow n Intellectual P roperty (including issued U.S. and Foreign P atents and pending patent applications) relating to the products described in this data sheet. No license, w hether express, im plied, or arising by estoppel or otherw ise, to any intellectual property rights is granted by this docum ent. Interested parties should contact Vicor's Intellectual P roperty Departm ent. The products described on this data sheet are protected by the follow ing U.S. P atents Num bers: 5 ,94 5 ,13 0; 6,4 03 ,009; 6,7 10,25 7 ; 6,911,84 8; 6,93 0,893 ; 6,93 4 ,166; 6,94 0,013 ; 6,969,909; 7 ,03 8,917 ; 7 ,166,898; 7 ,187 ,263 ; 7 ,3 61,84 4 ; D4 96,906; D5 05 ,114 ; D5 06,4 3 8; D5 09,4 7 2; and for use under 6,97 5 ,098 and 6,984 ,965 . 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