FCM8531

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Technical content

Features

Advanced Motor Controller (AMC)  Configurable Processing Core ­ Sensorless Field-Oriented Control (FOC) with Speed Integral Method ­ Sensorless FOC with Sliding Mode ­ Hall Interface  Space Vector Modulation (SVM)  Sine-Wave & Square-Wave Generator  Programmable Current Leading Phase Control  Programmable Soft-Switching Control (Dead Time)  FCM8531RQY Certified by UL for IEC-60730-1 Class B Compliance with recognized marking: Embedded MCU  MCS® 51 Compatible  63% of Instructions’ Execution Cycle <3 System Clocks (3T)  Memory Size: ­ 12 KB Flash Program Memory ­ 256 +1 KB SRAM Data Memory  Extended16-Bit Multiplication / Division Unit (MDU)  ≤17 General-Purpose Input / Output (GPIO) Pins  Full Duplex Serial Interface (UART)  I2C Interface  Serial Peripheral Interface (SPI)  Three External Interrupts  Three 16-Bit Timers  Programmable 15-Bit Watchdog Timer (WDT)  Built-in Power-On Reset (POR)  Built-in Clock Generator  Two-Level Program Memory Lock ADC and DAC  8-Channel, 10-Bit ADC ­ Auto-Trigger Sample & Hold ­ Four Trigger Mode Selections ­ Three Pre-AMP Gain Selections  1-Channel, 8-Bit DAC Protections  Three Levels of Over-Current Protection (OCP) Power Management  Idle Mode, Stop Mode, Sleep Mode Development Supports  In System Programming (ISP) On-Chip Debug Support (OCDS)

Description

The FCM8531 is an application -specific parallel-core processor for motor control that consists of an Advanced Motor Controller (AMC ) processor and a MCS® 51-compatible MCU p rocessor. The AMC is the core processor specifically designed for motor control. It integrates a configurable processing core and peripheral circuits to perform FOC and “Sensorless” motor control. System control, user interface, communication interface, and input/output interface can be programmed through the embedded MCS® 51 for different motor applications. The advantage of FCM8531’s parallel-core processors is that the two processors can work independently and complement each other. The AMC processes the tasks dedicated for motor controls, such as the motor control algorithms, PWM controls, current sensing, real -time over-current protection , and motor angle calculation. The embedded MCU provides motor control commands to the AMC to perform motor control activities through a communication interface. This approach reduces the software burden and simplifies the control system program because complex motor control algorithms are executed in the AMC. Fairchild provides the Motor Control Development System (MCDS) IDE and MCDS Programming Kit for users to develop software, compile programs, and perform online debugging. To meet IEC 60730-1 Class B safety standard for household appliances, FCM8531 has FCM8531RQY version in its family that has been certificated by U L for the compliance . Users can directly utilize the UL certificated AMC to quicken product development cycle for electronic controlled PMSM/BLDC motor.

Applications

 Sensorless IPM / SPM, BLDC / PMSM Motor  Fan, Blower, Pump, Compressor, etc. Related Resources  AN-8202— FCM8531 User Manual - Hardware  AN-8203— FCM8531 User Manual - Instruction Set  User Guide for FCM8531 Evaluation Board

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FCM8531 • Rev. 1.0.2 2 FCM8531 — MCU Embedded and Configurable 3-Phase PMSM/BLDC Motor Controller

Ordering Information

Part Number Operating Temperature Range Package Packing Method FCM8531QY -40oC to 85oC 32-Lead, LQFP, JEDEC MS-026, Variation BBA, 7 mm Square Tray FCM8531RQY -40oC to 85oC 32-Lead, LQFP, JEDEC MS-026, Variation BBA, 7 mm Square Tray Application Diagram FCM8531 CW/CCW RUN/STOP ISP Port +5V RST VPP SCL SDA GND FAULT SPEED VSEN

12 RST

26 VPP

3 P12

4 P13

A A A A A A A A DC-DC Converter A D DD D D D D D 0.1µF 1µF 0.1µF 1nF 0.1µF 10K 10K 3.3 40K 1% <100p 40K 1% 40K 1% Figure 1. Typical Application Circuit

Figure 5. Pin Configuration P10 I/O Bit 0 of Port 1. General-purpose input/output pin with internal pull-up resistor. P11 I/O Bit 1 of Port 1. General-purpose input/output pin with internal pull-up resistor. P12 I/O Bit 2 of Port 1. General-purpose input/output pin with internal pull-up resistor. ISP_SCL I ISP Serial Clock. Serial clock input in ISP Mode. P13 I/O Bit 3 of Port 1. General-purpose input/output pin with internal pull-up resistor. ISP_SDA I/O ISP Serial Data. Serial data input/output pin in ISP Mode. P14 I/O Bit 4 of Port 1. General-purpose input/output pin with internal pull-up resistor. TDO O Test Data Output. Test data output in OCDS Mode.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FCM8531 • Rev. 1.0.2 5 FCM8531 — MCU Embedded and Configurable 3-Phase PMSM/BLDC Motor Controller Pin Definitions (Continued) Pin # Name Type Description P15 I/O Bit 5 of Port 1. General-purpose input/output pin with internal pull-up resistor. MOSI I/O Master Data Output and Slave Data Input (SPI) TX O Serial Data Transmit (UART) SDA I/O Serial Data (I2C) TDI I Test Data Input. Test data input in OCDS Mode. P16 I/O Bit 6 of Port 1. General-purpose input/output pin with internal pull-up resistor. MISO I/O Master Data Input and Slave Data Output (SPI) SCL I/O Serial Clock (I2C) RX I Data Receive (UART) TMS I Test Mode Select. Test mode select in OCDS Mode. P17 I/O Bit 7 of Port 1. General-purpose input/output pin with internal pull-up resistor. SCK I/O Serial Clock (SPI) SDA I/O Serial Data (I2C) TX O Serial Data Transmit (UART) TCK I Test Clock. Test clock input in OCDS Mode. P24 I/O Bit 4 of Port 2. General-purpose input/output pin with internal pull-up resistor. CC0 I/O TIMER2 Compare/Capture Channel 0 T0 I TIMER0 External Input T2 I TIMER2 External Input P25 I/O Bit 5 of Port 2. General-purpose input/output pin with internal pull-up resistor. CC1 I/O TIMER2 Compare/Capture Channel 1 T1 I TIMER1 External Input T2EX I TIMER2 External Trigger P26 I/O Bit 6 of Port 2. General-purpose input/output pin with internal pull-up resistor. CC2 I/O TIMER2 Compare/Capture Channel 2 T2 I TIMER2 External Input T0 I TIMER0 External Input 12 RST I System Reset. Hardware reset input, active HIGH. 13 VC AI Analog Input. 10-bit ADC input (middle sampling rate). The ADC result stores in VCL and VCH registers (2Ch, 2Dh) of MSFR. 14 VB AI Analog Input. 10-bit ADC input (middle sampling rate). The ADC result stores in VBL and VBH registers (2Ah, 2Bh) of MSFR. 15 VA AI Analog Input. 10-bit ADC input (middle sampling rate). The ADC result stores in VAL and VAH registers (28h, 29h) of MSFR. ADC3 AI Analog Input. 10-bit ADC input (low sampling rate).The ADC result stores in ADC3L and ADC3H registers (36h, 37h) of MSFR. AOUT AO Analog Output. 8-bit DAC output set by DAC3 register (47h) of MSFR.

17 AVSS P Analog Ground

18 ADC0 AI Analog Input. 10-bit ADC input (low sampling rate). The ADC result stores in ADC0L and ADC0H registers (30h, 31h) of MSFR. 19 IC AI Phase C Current Input. 10-bit ADC input (high sampling rate). The ADC result stores in ICL and ICH registers (24h, 25h) of MSFR. Continued on the following page…

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FCM8531 • Rev. 1.0.2 6 FCM8531 — MCU Embedded and Configurable 3-Phase PMSM/BLDC Motor Controller Pin Definitions (Continued) Pin # Name Type Description 20 IB AI Phase B Current Input. 10-bit ADC input (high sampling rate). The ADC result stores in IBL and IBH registers (22h, 23h) of MSFR. 21 IA AI Phase A Current Input. 10-bit ADC input (High sampling rate). The ADC result stores in IAL and IAH registers (20h, 21h) of MSFR. 22 AVDD P 5.0 V Analog Voltage Input. A 0.1 µF (minimum) capacitor should be connected between this pin and AVSS. 23 DVDD P 5.0 V Digital Voltage Input. A 0.1 µF (minimum) capacitor should be connected between this pin and DVSS. 24 V25 O 2.5 V Voltage Regulator Output. A 0.1 µF (minimum) capacitor should be connected between this pin and DVSS.

25 DVSS P Digital Ground

26 VPP P Programming Supply Voltage. VPP = 12 V for flash memory programming. U O PWM Output. High-side gate control signal of phase A. P02 I/O Bit 2 of Port 0. General-purpose input/output pin with internal pull-down resistor. X O PWM Output. Low-side gate control signal of phase A. P03 I/O Bit 3 of Port 0. General-purpose input/output pin with internal pull-down resistor. V O PWM Output. High-side gate control signal of phase B. P04 I/O Bit 4 of Port 0. General-purpose input/output pin with internal pull-down resistor. Y O PWM Output. Low-side gate control signal of phase B. P05 I/O Bit 5 of Port 0. General-purpose input/output pin with internal pull-down resistor. W O PWM Output. High-side gate control signal of phase C. P06 I/O Bit 6 of Port 0. General-purpose input/output pin with internal pull-down resistor. Z O PWM Output. Low-side gate control signal of phase C. P07 I/O Bit 7 of Port 0. General-purpose input/output pin with internal pull-down resistor. Notes: 1. Type P: power pin. 2. Type I: digital input pin. 3. Type O: digital output pin. 4. Type I/O: bidirectional input/output pin. 5. Type AI: analog input pin. 6. Type AO: analog output pin.

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FCM8531 • Rev. 1.0.2 7 FCM8531 — MCU Embedded and Configurable 3-Phase PMSM/BLDC Motor Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VPP Programming Supply Voltage -0.7 13 V VDD Supply Voltage -0.7 7 V VVIH Voltage of I/O Pin and RST Pin with Respect to GND -0.2 VDD+0.2 V VAN Analog Input Voltage -0.2 VDD+0.2 V JA Thermal Resistance (Junction-to-Air) 80 C/W TA Operating Ambient Temperature Range -40 85 C TSTG Storage Temperature Range -65 150 C ESD Electrostatic Discharge Capability Human Body Model, JESD22-A114 3,000 V Charged Device Model, JESD22-C101 1,250 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairc hild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V VPP Programming Supply Voltage 11.8 12.0 12.2 V

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FCM8531 • Rev. 1.0.2 8 FCM8531 — MCU Embedded and Configurable 3-Phase PMSM/BLDC Motor Controller

Electrical Characteristics

VDD=5 V, and TA=25C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Unit fSYS System Frequency 29.4 30.0 30.6 MHz fSYS System Frequency At -40C 28.5 31.5 MHz Power Management VDD_ON Turn-On Voltage 4.5 V VDD_OFF Turn-Off Voltage 3.2 V VOUT V25 Output Voltage Range Load Current < 10 mA 2.35 2.50 2.65 V IDD_OPER VDD Current at Operation Mode 20 kHz PWM Output 20 29 35 mA IDD_SLEEP (7) VDD Current at Sleep Mode Wake-up Period = 37 ms 500 µA tSLEEP (7) Sleep Mode Period Initial Setting 40 ms Flash Memory(7) VPP Program/Erase Supply Voltage 11.8 12.0 12.2 V IVPP Mass Program Current 8 mA tWRITE Page Write Time 1.55 ms tERASE Erase Time 500 600 ms Endurance Erase + Write 1000 cycle Data Retention 100 year 10-Bit ADC(7) RI Input Impedance 3 MΩ VI_MIN Minimum Conversion Voltage Code 000h 0 V VI_MAX Maximum Conversion Voltage Code 3FFh 4 V DNL Differential Nonlinearity ±2.0 LSB INL Integral Nonlinearity ±2.0 LSB ErrADC Offset Error ±3.0 LSB 8-Bit DAC(7) RO Output Impedance W/I, W/O Current Bias 10 kΩ VO_MIN Minimum Conversion Voltage Code 00h 50 mV VO_MAX Maximum Conversion Voltage Code FFh 4 V DNL Differential Nonlinearity ±1.0 LSB INL Integral Nonlinearity ±2.0 LSB Current Limit VOCL_OFFSET OCL Comparator Offset OCL = 10h -50 50 mV VOCH_OFFSET OCH Comparator Offset OCH = C0h -50 50 mV VSHORT_OFFSET SHORT Comparator Offset SHORT = C0h -50 50 mV VOCL_RNG (7) OCL Comparator Operation Range 0 3.5 V VOCH_RNG (7) OCH Comparator Operation Range 1 4 V VSHORT_RNG (7) SHORT Comparator Operation Range 1 4 V IBIAS Current Source of IA/IB/IC 47.5 50.0 52.5 µA IBIAS (7) Current Source of IA/IB/IC At -40C 46 51 µA Continued on the following page…

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FCM8531 • Rev. 1.0.2 9 FCM8531 — MCU Embedded and Configurable 3-Phase PMSM/BLDC Motor Controller VDD=5 V, and TA=25C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Unit GPIO VIH Input High Voltage 3.3 V VIL Input Low Voltage 1.8 V RUP (7) P1, P2 Pull-Up Resistor 40 kΩ RDOWN (7) P0, RST Pull-Down Resistor 45 kΩ IOL Low Level Output Current VOL = 0.4 V 2.3 mA IOH High Level Output Current VOH = 0.8 x VDD 2.5 mA SPI(7,9) tR(SCK) SPI Clock Rising Time Master Mode, CL = 20 pF 60 ns tF(SCK) SPI Clock Falling Time Master Mode, CL = 20 pF 60 ns tSCK SPI Clock Cycle Time tSYS x 8 ns tENS SSN Setup Time tSYS x 3 ns tHS SSN Hold Time Slave Mode tSYS x 3 ns tDS Data Input Setup Time Master Mode tSYS ns Slave Mode tSYS ns tDH(MO) Data Output Hold Time Master Mode tSYS ns tDH(SO) Data Output Hold Time Slave Mode tSYS ns tDH(MI) Data Input Hold Time Master Mode tSYS ns tDH(SI) Data Input Hold Time Slave Mode tSYS ns tDIS(SO) Data Output Disable Time Slave Mode tSYS x 3 ns I2C Interface(7,10) tSCL I2C Clock Cycle Time tSYS x 120 ns tSTART I2C Start Bit Setup Time tSCL / 2 ns tSTOP I2C Stop Bit Setup Time tSCL / 2 ns tSETUP I2C Data Setup Time tSYS ns tHOLD I2C Data Hold Time tSYS ns Notes: 7. These parameters are not tested in manufacturing. 8. tSYS = 1 / fSYS = 33.33 ns. 9. SPI timing diagrams as Figure 6 and Figure 7. 10. I2C timing diagram as Figure 8.

Figure 19. Default Sine-Wave PWM Output (CW=1) debounce, blanking, regulation, and inversion. improve the motor efficiency. assembler and compiler can be used for development. Figure 20. Embedded MCU Block Diagram groups of user-definable wave tables and one lock byte. Flash memory must first be erased and then re-written.

12 KBytes Flash

Figure 21. Program Memory Map

256 Bytes SRAM

1024 Bytes SRAM

Figure 22. Data Memory Map displacement and normalization calculations. calculation is completed, the result is stored in SFR. Figure 23. MDU Mode open drain through DIR0, DIR1 , and DIR2 of the SFR. 5 V with internal resistors. Figure 24. GPIO Driver & Buffer other DIO pins are pre-set as GPIO (see Table 2). Table 2. Port 0 Function Configuration Table 3. Port 1 Function Configuration Table 4. Port 2 Function Configuration set to low-level trigger and falling-edge trigger.

for developing the motor control system. source with a higher priority level occurs. Table 5. Interrupt Vector or hardware abnormalities, it resets automatically. refreshed. After timeout, the program restarts. modules. They are accessed through MCU SFRs. protection level can be set in MSFRs. status, and PWM status) can be obtained via MSFRs. output voltage is set via the DAC in the MSFR. to the speed of the sampling rate (see Table 6). Table 6. ADC Sampling Rate Pins IA, IB, and IC are preset as current-sensing input. goes through a pre -amplifier to a 10 -bit A-D converter. SAW valley, Timer0, and manual trigger. Figure 25. ADC Trigger Mode protection and over-current (cycle-by-cycle) protection. turned off until the error status is released. is turned off until the next cycle. Table 7. Fault and Protection

Table 8. SFRs (Special Function Registers) Map

98 SCON SBUF IEN2 9F

90 P1 DPS DPC MSFRADR MSFRDAT 97

88 TCON TMOD TL0 TL1 TH0 TH1 CKCON 8F

80 P0 SP DPL DPH DPL1 DPH1 WDTREL PCON 87

Table 9. MSFRs (Motor Special Function Registers) Map

40 MBUSCTL PT01 PT23 SLEEP OCH OCL SHORT DACO 47

38 Reserved Reserved Reserved Reserved Reserved Reserved ANGLE MSTAT 3F

30 ADC0L ADC0H ADC3L ADC3H 37

28 VAL VAH VBL VBH VCL VCH ADCINX BAK 2F

20 IAL IAH IBL IBH ICL ICH OCCNTL OCSTA 27

18 HALMXU HALFLT HALSTA HALINT HPERL HPERM HPERH ADCCFG 1F

10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 17

08 PWMCFG SAWCNTL SPRDL SPRDH SDLYBL SDLYBH SDLYCL SDLYCH 0F

00 MCNTL ANGCTL AS ANGDET DUTYAL DUTYA DUTYB DUTYC 07

Figure 28. 32-Low-Profile, Quad, Flat Pack Package (LQFP) specifically the warranty therein, which covers Fairchild products. http://www.fairchildsemi.com/dwg/VB/VBE32A.pdf. B) ALL DIMENSIONS IN MILLIMETERS. FLASH, AND TIE BAR PROTRUSIONS.

0.20 MIN

1.6 MAX

0.20 C A-B D

© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FCM8531 • Rev. 1.0.2 20 FCM8531 — MCU Embedded and Configurable 3-Phase PMSM/BLDC Motor Controller